1 files changed, 3 insertions, 0 deletions
diff --git a/fpga/usrp2/top/E1x0/core_compile b/fpga/usrp2/top/E1x0/core_compile
new file mode 100755
index 000000000..dc0cd081e
--- /dev/null
+++ b/fpga/usrp2/top/E1x0/core_compile
@@ -0,0 +1,3 @@
+iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1e_core.v  2>&1  | grep -v timescale | grep -v coregen | grep -v models
+
+