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-rw-r--r--fpga/usrp2/top/B100/u1plus_core.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v
index 6a80eba76..b40083201 100644
--- a/fpga/usrp2/top/B100/u1plus_core.v
+++ b/fpga/usrp2/top/B100/u1plus_core.v
@@ -89,7 +89,7 @@ module u1plus_core
.in(set_data),.out(),.changed(global_reset));
reset_sync reset_sync_wb(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(wb_rst));
- reset_sync reset_sync_gp(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(gpif_rst));
+ reset_sync reset_sync_gp(.clk(gpif_clk), .reset_in(rst_fpga | global_reset), .reset_out(gpif_rst));
wire [15:0] test_len;
// /////////////////////////////////////////////////////////////////////////////////////