diff options
Diffstat (limited to 'fpga/usrp2/sdr_lib/rx_frontend.v')
| -rw-r--r-- | fpga/usrp2/sdr_lib/rx_frontend.v | 75 |
1 files changed, 40 insertions, 35 deletions
diff --git a/fpga/usrp2/sdr_lib/rx_frontend.v b/fpga/usrp2/sdr_lib/rx_frontend.v index 04b14787e..edfbe62df 100644 --- a/fpga/usrp2/sdr_lib/rx_frontend.v +++ b/fpga/usrp2/sdr_lib/rx_frontend.v @@ -1,6 +1,7 @@ module rx_frontend - #(parameter BASE = 0) + #(parameter BASE = 0, + parameter IQCOMP_EN = 0) (input clk, input rst, input set_stb, input [7:0] set_addr, input [31:0] set_data, @@ -16,7 +17,6 @@ module rx_frontend wire [17:0] adc_i_ofs, adc_q_ofs; wire [35:0] corr_i, corr_q; wire [17:0] mag_corr,phase_corr; wire swap_iq; - wire [23:0] i_final, q_final; setting_reg #(.my_addr(BASE), .width(1)) sr_8 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), @@ -35,39 +35,44 @@ module rx_frontend setting_reg #(.my_addr(BASE+2),.width(18)) sr_2 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(phase_corr),.changed()); - - rx_dcoffset #(.WIDTH(18),.ADDR(BASE+3)) rx_dcoffset_i - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .in({adc_i,2'b00}),.out(adc_i_ofs)); - - rx_dcoffset #(.WIDTH(18),.ADDR(BASE+4)) rx_dcoffset_q - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .in({adc_q,2'b00}),.out(adc_q_ofs)); - - MULT18X18S mult_mag_corr - (.P(corr_i), .A(adc_i_ofs), .B(mag_corr), .C(clk), .CE(1), .R(rst) ); - MULT18X18S mult_phase_corr - (.P(corr_q), .A(adc_i_ofs), .B(phase_corr), .C(clk), .CE(1), .R(rst) ); - - add2_and_clip_reg #(.WIDTH(24)) add_clip_i - (.clk(clk), .rst(rst), - .in1({adc_i_ofs,6'd0}), .in2({{4{corr_i[35]}},corr_i[35:16]}), .strobe_in(1'b1), - .sum(i_final), .strobe_out()); - - add2_and_clip_reg #(.WIDTH(24)) add_clip_q - (.clk(clk), .rst(rst), - .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .strobe_in(1'b1), - .sum(q_final), .strobe_out()); - - assign i_out = i_final; - assign q_out = q_final; - - /* - round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_i - (.clk(clk), .reset(rst), .in(i_final), .strobe_in(1'b1), .out(i_out), .strobe_out()); + generate + if(IQCOMP_EN == 1) + begin + rx_dcoffset #(.WIDTH(18),.ADDR(BASE+3)) rx_dcoffset_i + (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .in({adc_i,2'b00}),.out(adc_i_ofs)); + + rx_dcoffset #(.WIDTH(18),.ADDR(BASE+4)) rx_dcoffset_q + (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .in({adc_q,2'b00}),.out(adc_q_ofs)); + + MULT18X18S mult_mag_corr + (.P(corr_i), .A(adc_i_ofs), .B(mag_corr), .C(clk), .CE(1), .R(rst) ); + + MULT18X18S mult_phase_corr + (.P(corr_q), .A(adc_i_ofs), .B(phase_corr), .C(clk), .CE(1), .R(rst) ); + + add2_and_clip_reg #(.WIDTH(24)) add_clip_i + (.clk(clk), .rst(rst), + .in1({adc_i_ofs,6'd0}), .in2({{4{corr_i[35]}},corr_i[35:16]}), .strobe_in(1'b1), + .sum(i_out), .strobe_out()); + + add2_and_clip_reg #(.WIDTH(24)) add_clip_q + (.clk(clk), .rst(rst), + .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .strobe_in(1'b1), + .sum(q_out), .strobe_out()); + end // if (IQCOMP_EN == 1) + else + begin + rx_dcoffset #(.WIDTH(24),.ADDR(BASE+3)) rx_dcoffset_i + (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .in({adc_i,8'b00}),.out(i_out)); + + rx_dcoffset #(.WIDTH(24),.ADDR(BASE+4)) rx_dcoffset_q + (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .in({adc_q,8'b00}),.out(q_out)); + end // else: !if(IQCOMP_EN == 1) + endgenerate - round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_q - (.clk(clk), .reset(rst), .in(q_final), .strobe_in(1'b1), .out(q_out), .strobe_out()); - */ endmodule // rx_frontend |