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-rw-r--r--fpga/usrp2/sdr_lib/cordic_z24.v2
1 files changed, 0 insertions, 2 deletions
diff --git a/fpga/usrp2/sdr_lib/cordic_z24.v b/fpga/usrp2/sdr_lib/cordic_z24.v
index 97b7beaf7..51b074a33 100644
--- a/fpga/usrp2/sdr_lib/cordic_z24.v
+++ b/fpga/usrp2/sdr_lib/cordic_z24.v
@@ -119,8 +119,6 @@ module cordic_z24(clock, reset, enable, xi, yi, zi, xo, yo, zo );
assign xo = x20[bitwidth:1];
assign yo = y20[bitwidth:1];
assign zo = z20;
- //assign xo = x20[bitwidth+1:2]; // CORDIC gain is ~1.6, plus gain from rotating vectors
- //assign yo = y20[bitwidth+1:2];
endmodule // cordic