45 files changed, 6894 insertions, 0 deletions
diff --git a/fpga/usrp2/opencores/spi_boot/COMPILE_LIST b/fpga/usrp2/opencores/spi_boot/COMPILE_LIST
new file mode 100644
index 000000000..fc8f7d418
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/COMPILE_LIST
@@ -0,0 +1,33 @@
+
+Compile list for the spi_boot core
+==================================
+Version: $Date: 2005/04/14 21:26:22 $
+
+bench/vhdl/tb.vhd
+rtl/vhdl/spi_boot_pack-p.vhd
+bench/vhdl/tb_pack-p.vhd
+bench/vhdl/tb_elem.vhd
+rtl/vhdl/chip-e.vhd
+rtl/vhdl/chip-full-a.vhd
+rtl/vhdl/spi_boot.vhd
+rtl/vhdl/spi_counter.vhd
+rtl/vhdl/spi_counter-c.vhd
+rtl/vhdl/spi_boot-c.vhd
+rtl/vhdl/chip-full-c.vhd
+bench/vhdl/card.vhd
+bench/vhdl/card-c.vhd
+bench/vhdl/tb_elem-full-c.vhd
+rtl/vhdl/chip-mmc-a.vhd
+rtl/vhdl/chip-mmc-c.vhd
+bench/vhdl/tb_elem-mmc-c.vhd
+rtl/vhdl/chip-sd-a.vhd
+rtl/vhdl/chip-sd-c.vhd
+bench/vhdl/tb_elem-sd-c.vhd
+rtl/vhdl/chip-minimal-a.vhd
+rtl/vhdl/chip-minimal-c.vhd
+bench/vhdl/tb_elem-minimal-c.vhd
+bench/vhdl/tb-c.vhd
+bench/vhdl/tb_rl.vhd
+rtl/vhdl/sample/ram_loader.vhd
+rtl/vhdl/sample/ram_loader-c.vhd
+bench/vhdl/tb_rl-c.vhd
diff --git a/fpga/usrp2/opencores/spi_boot/COPYING b/fpga/usrp2/opencores/spi_boot/COPYING
new file mode 100644
index 000000000..60549be51
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/COPYING
@@ -0,0 +1,340 @@
+		    GNU GENERAL PUBLIC LICENSE
+		       Version 2, June 1991
+
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+ Everyone is permitted to copy and distribute verbatim copies
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diff --git a/fpga/usrp2/opencores/spi_boot/KNOWN_BUGS b/fpga/usrp2/opencores/spi_boot/KNOWN_BUGS
new file mode 100644
index 000000000..298e4ba2e
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/KNOWN_BUGS
@@ -0,0 +1,4 @@
+
+Known bugs of the spi_boot core
+===============================
+Version: $Date: 2005/02/13 18:28:35 $
diff --git a/fpga/usrp2/opencores/spi_boot/README b/fpga/usrp2/opencores/spi_boot/README
new file mode 100644
index 000000000..926b35bff
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/README
@@ -0,0 +1,170 @@
+
+README for the spi_boot core
+============================
+Version: $Date: 2005/04/14 21:32:58 $
+
+
+Description
+-----------
+
+The SD/MMC Bootloader is a CPLD design that manages configuration and
+bootstrapping of FPGAs. It is able to retrieve the required data from
+SecureDigital (SD) cards or MultiMediaCards (MMC) and manages the FPGA
+configuration process. SD cards as well as MMCs are operated in SPI mode which
+is part of both standards thus eliminating the need for dedicated
+implementations. The SD/MMC Bootloader fits both. Beyond configuration, this
+core supports a bootstrapping strategy where multiple images are stored on one
+single memory card.
+For example consider a system completely based on SRAM. The bootloader
+provides the initial configuration data from the first image to the FPGA. This
+image contains a design which pulls the next image from the memory card and
+transfers this data to SRAM. In the third step the final FPGA design is loaded
+from the third image.
+These images are clustered in sets which can be selected by external switches
+for example. Several configuration sets can be stored on one memory card
+allowing you to provide a number of applications which are downloaded quickly
+to the FPGA.
+The schematic (rev. B) shows how the core can be used with an FPGA board. I
+use it to configure/boot the Xilinx Spartan IIe on BurchED's B5-X300
+board. SV2 fits the "SERIAL MODE" connector on this board but you will have to
+add a separate wire from R6 to attach INIT. Please check the proper use of the
+pull-up resistors for your specific board.
+
+
+Features
+--------
+
+* Configuration mode: configures SRAM based FPGAs via slave serial mode
+  (Xilinx and Altera)
+* Data mode: provides stored data over a simple synchronous serial interface
+* Broad compatability using SPI mode
+    + SecureDigital cards using dedicated initialization command
+    + MultiMediaCards (see below)
+* Operation triggerd by power-up or card insertion
+* Multiple configuration sets stored on on single memory card
+
+
+Compatability
+-------------
+
+These cards have been tested with the SD/MMC Bootloader:
+
+  * Hama 64 MB SD
+  * SanDisk 128 MB SD
+  * SanDisk 64 MB MMC
+  * Panasonic 32 MB SD 
+
+Some MMC might fail with this core as not all cards support CMD18
+(READ_MULTIPLE_BLOCK). Please consult the data sheet of your specific
+model. In case your MMC does not implement CMD18 you might want to have a look
+at the FPGA MMC-Card Config project.
+
+
+Tools
+-----
+
+Downloading the configuration data to the card is a straight forward
+process. The images have to be written starting at dedicated locations. For
+the provided toplevel designs, these locations are multiples of 256 K. I.e. 0,
+0x40000, 0x80000 and so forth.
+
+dd (part of the GNU coreutils) serves this purpose:
+$ dd if=ram_loader.bin of=/dev/sdX bs=512
+$ dd if=pongrom_6.bin of=/dev/sdX bs=512 seek=512
+$ dd if=pacman.bin of=/dev/sdX bs=512 seek=1024
+
+The name of the device node depends on how the card reader is attached to the
+kernel. For Linux systems this is most often something like /dev/sdX with X
+ranging from a-z. Please note that it is essential to use the device without
+any trailing numbers as they refer to partitions leading to wrong offsets for
+data written to the card.
+All this works perfectly for my Spartan IIe device as this FPGA expects the
+configuration data as it is delivered from the card: Consecutive bytes each
+with its most significant bit first. Altera devices like the FLEX family are
+different here. They expect the bytes with least significant bit
+first. Therefore, the configuration data has to be swapped bitwise before it
+is written to the card.
+
+
+Verification
+------------
+
+The spi_boot core comes with a simple testbench that simulates an SD/MMC
+card. All four implementations of the core are verified there in parallel
+while transferring the data for several sets.
+You should normally not need to run the testbench. But in case you modified
+the VHDL code the testbench gives some hints if the design has been broken.
+
+
+Directory Structure
+-------------------
+
+The core's directory structure follows the proposal of OpenCores.org.
+
+spi_boot
+ |
+ \--+-- doc                 : Documentation
+    |    |
+    |    \-- src            : Source files of documentation
+    |
+    +-- rtl
+    |    |
+    |    \-- vhdl           : VHDL code containing the RTL description
+    |                         of the core.
+    |
+    +-- bench
+    |    |
+    |    \-- vhdl           : VHDL testbench code.
+    |
+    \-- sim
+         |
+         \-- rtl_sim        : Directory for running simulations.
+
+
+RAM Loader
+----------
+
+Directory rtl/vhdl/ram_loader contains the sample design which loads the next
+image from the card and stores its contents to external asynchronous
+RAM. After reading 64 KB it triggers a new configuration process for the final
+FPGA design.
+Refer to the code for the mechanisms involved.
+
+
+Compiling the VHDL Code
+-----------------------
+
+VHDL compilation and simulation tasks take place inside in sim/rtl_sim
+directory. The project setup supports only the GHDL simulator (see
+http://ghdl.free.fr).
+
+To compile the code simply type at the shell
+
+$ make
+
+This should result in a file called tb_behav_c0 which can be executed as any
+other executable.
+
+The basic simple sequence list can be found in COMPILE_LIST. This can be
+useful to quickly set up the analyze stage of any compiler or
+synthesizer. Especially when synthesizing the code, you want to skip the VHDL
+configurations in *-c.vhd and everything below the bench/ directory.
+
+
+References
+----------
+
+  * SanDisk SD Card Product Manual
+    http://www.sandisk.com/pdf/oem/ProdManualSDCardv1.9.pdf
+
+  * SanDisk MMC Product Manual
+    http://www.sandisk.com/pdf/oem/manual-rs-mmcv1.0.pdf
+
+  * Toshiba SD Card Specification
+    http://i.cmpnet.com/chipcenter/memory/images/prod055.pdf
+
+  * BurchED
+    http://burched.biz/
+
+  * FPGA MMC-Card Config project
+    http://www.opencores.org/projects.cgi/web/mmcfpgaconfig/overview
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/card-c.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/card-c.vhd
new file mode 100644
index 000000000..797eb1c90
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/card-c.vhd
@@ -0,0 +1,14 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: card-c.vhd,v 1.1 2005/02/08 21:09:18 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration card_behav_c0 of card is
+
+  for behav
+  end for;
+
+end card_behav_c0;
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/card.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/card.vhd
new file mode 100644
index 000000000..dcd676095
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/card.vhd
@@ -0,0 +1,446 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Simple SD and MMC model
+--
+-- $Id: card.vhd,v 1.2 2005/02/13 17:06:22 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity card is
+
+  generic (
+    card_type_g  : string := "none";
+    is_sd_card_g : integer := 1
+  );
+
+  port (
+    spi_clk_i  : in  std_logic;
+    spi_cs_n_i : in  std_logic;
+    spi_data_i : in  std_logic;
+    spi_data_o : out std_logic
+  );
+
+end card;
+
+
+library ieee;
+use ieee.numeric_std.all;
+library std;
+use std.textio.all;
+
+use work.tb_pack.all;
+
+architecture behav of card is
+
+  signal power_on_n_s : std_logic;
+  signal soft_res_n_s : std_logic;
+  signal res_n_s      : std_logic;
+
+  signal rx_s : std_logic_vector(47 downto 0);
+
+  signal set_spi_mode_s,
+         spi_mode_q       : boolean;
+  signal set_idle_mode_s,
+         poll_idle_mode_s : boolean;
+  signal idle_mode_q      : natural;
+
+  signal block_len_q,
+         block_len_s     : unsigned(31 downto 0);
+  signal set_block_len_s : boolean;
+
+  signal new_read_addr_s,
+         read_addr_q     : unsigned(31 downto 0);
+  signal set_read_addr_s,
+         inc_read_addr_s : boolean;
+
+  signal cmd_spi_data_s,
+         read_spi_data_s : std_logic;
+  signal start_read_s    : boolean;
+  signal reading_s       : boolean;
+
+  procedure rise_clk is
+  begin
+    wait until spi_clk_i'event and to_X01(spi_clk_i) = '1';
+  end rise_clk;
+
+--  procedure rise_clk(num : natural) is
+--  begin
+--    for i in 1 to num loop
+--      rise_clk;
+--    end loop;
+--  end rise_clk;
+
+  procedure fall_clk is
+  begin
+    wait until spi_clk_i'event and to_X01(spi_clk_i) = '0';
+  end fall_clk;
+
+  procedure fall_clk(num : natural) is
+  begin
+    for i in 1 to num loop
+      fall_clk;
+    end loop;
+  end fall_clk;
+
+begin
+
+  res_n_s <= power_on_n_s and soft_res_n_s;
+
+  -----------------------------------------------------------------------------
+  -- Power on reset
+  -----------------------------------------------------------------------------
+  por: process
+  begin
+    power_on_n_s <= '0';
+    wait for 200 ns;
+    power_on_n_s <= '1';
+    wait;
+  end process por;
+
+
+  -----------------------------------------------------------------------------
+  --
+  ctrl: process
+
+    function check_crc(payload : in std_logic_vector(47 downto 0))
+      return boolean is
+
+    begin
+
+      return calc_crc(payload(47 downto 8)) = payload(7 downto 1);
+    end check_crc;
+
+    variable rx_v        : std_logic_vector(47 downto 0);
+    variable cmd_v       : std_logic_vector( 5 downto 0);
+    variable arg_v       : std_logic_vector(31 downto 0);
+    variable crc_v       : std_logic_vector( 6 downto 0);
+    variable wrong_v     : std_logic;
+    variable read_data_v : boolean;
+
+  begin
+    rx_s <= (others => '0');
+    set_spi_mode_s   <= false;
+    set_idle_mode_s  <= false;
+    poll_idle_mode_s <= false;
+    cmd_spi_data_s   <= '1';
+    soft_res_n_s     <= '1';
+    set_block_len_s  <= false;
+    block_len_s      <= (others => '0');
+    new_read_addr_s  <= (others => '0');
+    set_read_addr_s  <= false;
+    start_read_s     <= false;
+    read_data_v      := false;
+
+    loop
+
+      rise_clk;
+      -- wait for startbit of command
+      while to_X01(spi_data_i) = '1' loop
+        rise_clk;
+      end loop;
+      rx_v(47) := '0';
+
+      -- read remaining 47 bits of command
+      for i in 46 downto 0 loop
+        rise_clk;
+        rx_v(i) := to_X01(spi_data_i);
+      end loop;
+      rx_s <= rx_v;
+
+      -- dissect received data
+      cmd_v := rx_v(45 downto 40);
+      arg_v := rx_v(39 downto  8);
+      crc_v := rx_v( 7 downto  1);
+
+      assert spi_mode_q or check_crc(payload => rx_v)
+        report "CRC mismatch"
+        severity error;
+
+      wrong_v     := '0';
+      case cmd_v is
+        -- CMD0: GO_IDLE_STATE ------------------------------------------------
+        when "000000" =>
+          set_spi_mode_s  <= true;
+          set_idle_mode_s <= true;
+        -- CMD1: SEND_OP_COND -------------------------------------------------
+        when "000001" =>
+          poll_idle_mode_s <= true;
+        -- CMD12: STOP_TRANSMISSION -------------------------------------------
+        when "001100" =>
+          start_read_s <= false;
+          read_data_v  := false;
+        -- CMD16: SET_BLOCKLEN ------------------------------------------------
+        when "010000" =>
+          block_len_s     <= unsigned(arg_v);
+          set_block_len_s <= true;
+        -- CMD18: READ_MULTIPLE_BLOCK -----------------------------------------
+        when "010010" =>
+          new_read_addr_s <= unsigned(arg_v);
+          set_read_addr_s <= true;
+          read_data_v     := true;
+        -- CMD55: APPL_CMD ----------------------------------------------------
+        when "110111" =>
+          -- command only available for SD card
+          if is_sd_card_g /= 1 then
+            wrong_v := '1';
+          end if;
+        -- ACMD41: SEND_OP_COND -----------------------------------------------
+        when "101001" =>
+          -- command only available for SD card
+          if is_sd_card_g /= 1 then
+            wrong_v := '1';
+          else
+            poll_idle_mode_s <= true;
+          end if;
+
+        when others =>
+          wrong_v := '1';
+          null;
+      end case;
+
+
+      -- spend some time before removing control signals
+      fall_clk(2);
+      poll_idle_mode_s <= false;
+      set_idle_mode_s <= false;
+      fall_clk(6);
+      set_spi_mode_s  <= false;
+      set_block_len_s <= false;
+      set_read_addr_s <= false;
+
+      if reading_s then
+        wait until not reading_s;
+      end if;
+
+
+      -- wait for a total two "bytes" before sending out response
+      for i in 1 to 8 loop
+        fall_clk;
+      end loop;
+
+      for i in 7 downto 0 loop
+        fall_clk;
+        case i is
+          when 2 =>
+            cmd_spi_data_s <= wrong_v;
+          when 0 =>
+            if idle_mode_q = 0 then
+              cmd_spi_data_s <= '0';
+            else
+              cmd_spi_data_s <= '1';
+            end if;
+          when others =>
+            cmd_spi_data_s <= '0';
+        end case;
+      end loop;
+      fall_clk;
+      cmd_spi_data_s <= '1';
+
+      -- transmit data if requested
+      start_read_s <= read_data_v;
+
+    end loop;
+  end process ctrl;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  --
+  seq: process (res_n_s,
+                spi_clk_i,
+                set_spi_mode_s,
+                set_idle_mode_s,
+                poll_idle_mode_s,
+                set_block_len_s,
+                block_len_s)
+
+  begin
+    if res_n_s = '0' then
+      spi_mode_q  <= false;
+      idle_mode_q <= 5;
+      block_len_q <= (others => '0');
+      read_addr_q <= (others => '0');
+
+    elsif spi_clk_i'event and spi_clk_i = '1' then
+      if set_spi_mode_s then
+        spi_mode_q  <= true;
+      end if;
+
+      if set_idle_mode_s then
+        idle_mode_q  <= 5;
+      elsif poll_idle_mode_s then
+        if idle_mode_q > 0 then
+          idle_mode_q <= idle_mode_q - 1;
+        end if;
+      end if;
+
+      if set_block_len_s then
+        block_len_q <= block_len_s;
+      end if;
+
+      if set_read_addr_s then
+        read_addr_q <= new_read_addr_s;
+      elsif inc_read_addr_s then
+        read_addr_q <= read_addr_q + 1;
+      end if;
+
+    end if;
+  end process seq;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  --
+  read_block: process
+
+    variable t_v : unsigned(7 downto 0);
+
+  begin
+    -- default assignments
+    inc_read_addr_s <= false;
+    reading_s       <= false;
+    read_spi_data_s <= '1';
+
+    loop
+      if not start_read_s then
+        wait until start_read_s;
+      end if;
+
+      reading_s <= true;
+
+      fall_clk(8);                    -- delay for one "byte"
+
+      -- send data token
+      fall_clk(7);                    -- 7 ones in a data token
+      read_spi_data_s <= '0';
+
+      -- send payload
+      payload: for i in 0 to to_integer(block_len_q)-1 loop
+        t_v := read_addr_q(0) & calc_crc(read_addr_q);
+        for bit in 7 downto 0 loop
+          fall_clk;
+          read_spi_data_s <= t_v(bit);
+
+          exit payload when not start_read_s;
+        end loop;
+        inc_read_addr_s <= true;
+        rise_clk;
+        inc_read_addr_s <= false;
+        wait for 10 ns;
+      end loop;
+
+      if start_read_s then
+        -- send crc
+        for i in 0 to 15 loop
+          fall_clk;
+          t_v := to_unsigned(i, 8);
+          read_spi_data_s <= t_v(0);
+        end loop;
+        fall_clk;
+      end if;
+
+      read_spi_data_s <= '1';
+      reading_s <= false;
+      -- loop for one "byte"
+      fall_clk(8);
+
+    end loop;
+  end process read_block;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  --
+  clk_check: process (spi_clk_i)
+
+    variable last_rising_v : time := 0 ns;
+    variable dump_line     : line;
+
+  begin
+    if spi_clk_i'event and spi_clk_i = '1' then
+      if is_sd_card_g = 0 and card_type_g /= "Minimal Chip" and
+         idle_mode_q > 0 then
+        if now - last_rising_v < 2.5 us and last_rising_v > 0 ns then
+          write(dump_line, card_type_g);
+          write(dump_line, string'(" @ "));
+          write(dump_line, now);
+          write(dump_line, string'(": Last rising edge of SPI clock "));
+          write(dump_line, now - last_rising_v);
+          write(dump_line, string'(" ago."));
+          writeline(output, dump_line);
+        end if;
+
+        last_rising_v := now;
+      end if;
+    end if;
+  end process clk_check;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Output Mapping
+  -----------------------------------------------------------------------------
+  spi_data_o <=   cmd_spi_data_s and read_spi_data_s
+                when spi_cs_n_i = '0' else
+                  'Z';
+
+end behav;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: card.vhd,v $
+-- Revision 1.2  2005/02/13 17:06:22  arniml
+-- handle termination properly
+--
+-- Revision 1.1  2005/02/08 21:09:20  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb-c.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb-c.vhd
new file mode 100644
index 000000000..caa171362
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb-c.vhd
@@ -0,0 +1,31 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: tb-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration tb_behav_c0 of tb is
+
+  for behav
+
+    for tb_elem_full_b : tb_elem
+      use configuration work.tb_elem_behav_full;
+    end for;
+
+    for tb_elem_mmc_b : tb_elem
+      use configuration work.tb_elem_behav_mmc;
+    end for;
+
+    for tb_elem_sd_b : tb_elem
+      use configuration work.tb_elem_behav_sd;
+    end for;
+
+    for tb_elem_minimal_b : tb_elem
+      use configuration work.tb_elem_behav_minimal;
+    end for;
+
+  end for;
+
+end tb_behav_c0;
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb.vhd
new file mode 100644
index 000000000..b359fa7c5
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb.vhd
@@ -0,0 +1,201 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Testbench
+--
+-- $Id: tb.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+entity tb is
+
+end tb;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb is
+
+  component tb_elem
+    generic (
+      chip_type_g   : string := "none";
+      has_sd_card_g : integer := 1
+    );
+    port (
+      clk_i   : in  std_logic;
+      reset_i : in  std_logic;
+      eos_o   : out boolean
+    );
+  end component;
+
+  constant period_c      : time := 100 ns;
+  constant reset_level_c : integer := 0;
+
+  signal clk_s   : std_logic;
+  signal reset_s : std_logic;
+
+  signal eos_full_s,
+         eos_mmc_s,
+         eos_sd_s,
+         eos_minimal_s : boolean;
+
+begin
+
+
+  -----------------------------------------------------------------------------
+  -- Testbench element including full featured chip
+  -----------------------------------------------------------------------------
+  tb_elem_full_b : tb_elem
+    generic map (
+      chip_type_g   => "Full Chip",
+      has_sd_card_g => 1
+    )
+    port map (
+      clk_i   => clk_s,
+      reset_i => reset_s,
+      eos_o   => eos_full_s
+    );
+
+
+  -----------------------------------------------------------------------------
+  -- Testbench element including MMC chip
+  -----------------------------------------------------------------------------
+  tb_elem_mmc_b : tb_elem
+    generic map (
+      chip_type_g   => "MMC Chip",
+      has_sd_card_g => 0
+    )
+    port map (
+      clk_i   => clk_s,
+      reset_i => reset_s,
+      eos_o   => eos_mmc_s
+    );
+
+
+  -----------------------------------------------------------------------------
+  -- Testbench element including SD chip
+  -----------------------------------------------------------------------------
+  tb_elem_sd_b : tb_elem
+    generic map (
+      chip_type_g   => "SD Chip",
+      has_sd_card_g => 1
+    )
+    port map (
+      clk_i   => clk_s,
+      reset_i => reset_s,
+      eos_o   => eos_sd_s
+    );
+
+
+  -----------------------------------------------------------------------------
+  -- Testbench element including cip with minimal features
+  -----------------------------------------------------------------------------
+  tb_elem_minimal_b : tb_elem
+    generic map (
+      chip_type_g   => "Minimal Chip",
+      has_sd_card_g => 0
+    )
+    port map (
+      clk_i   => clk_s,
+      reset_i => reset_s,
+      eos_o   => eos_minimal_s
+    );
+
+
+  -----------------------------------------------------------------------------
+  -- Clock Generator
+  -----------------------------------------------------------------------------
+  clk: process
+  begin
+    clk_s <= '0';
+    wait for period_c / 2;
+    clk_s <= '1';
+    wait for period_c / 2;
+  end process clk;
+
+
+  -----------------------------------------------------------------------------
+  -- Reset Generator
+  -----------------------------------------------------------------------------
+  reset: process
+  begin
+    if reset_level_c = 0 then
+      reset_s <= '0';
+    else
+      reset_s <= '1';
+    end if;
+
+    wait for period_c * 4 + 10 ns;
+
+    reset_s <= not reset_s;
+
+    wait;
+  end process reset;
+
+
+  -----------------------------------------------------------------------------
+  -- End Of Simulation Detection
+  -----------------------------------------------------------------------------
+  eos: process (eos_full_s,
+                eos_mmc_s,
+                eos_sd_s,
+                eos_minimal_s)
+  begin
+
+    if eos_full_s and eos_mmc_s and eos_sd_s and eos_minimal_s then
+      assert false
+        report "End of Simulation."
+        severity failure;
+    end if;
+
+  end process eos;
+
+end behav;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: tb.vhd,v $
+-- Revision 1.1  2005/02/08 21:09:20  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd
new file mode 100644
index 000000000..3c0fb902f
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd
@@ -0,0 +1,23 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: tb_elem-full-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration tb_elem_behav_full of tb_elem is
+
+  for behav
+
+    for dut_b : chip
+      use configuration work.chip_full_c0;
+    end for;
+
+    for card_b : card
+      use configuration work.card_behav_c0;
+    end for;
+
+  end for;
+
+end tb_elem_behav_full;
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd
new file mode 100644
index 000000000..1c33ac3d0
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd
@@ -0,0 +1,23 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: tb_elem-minimal-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration tb_elem_behav_minimal of tb_elem is
+
+  for behav
+
+    for dut_b : chip
+      use configuration work.chip_minimal_c0;
+    end for;
+
+    for card_b : card
+      use configuration work.card_behav_c0;
+    end for;
+
+  end for;
+
+end tb_elem_behav_minimal;
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd
new file mode 100644
index 000000000..b5baf604e
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd
@@ -0,0 +1,23 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: tb_elem-mmc-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration tb_elem_behav_mmc of tb_elem is
+
+  for behav
+
+    for dut_b : chip
+      use configuration work.chip_mmc_c0;
+    end for;
+
+    for card_b : card
+      use configuration work.card_behav_c0;
+    end for;
+
+  end for;
+
+end tb_elem_behav_mmc;
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd
new file mode 100644
index 000000000..9cdf3eaa1
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd
@@ -0,0 +1,23 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: tb_elem-sd-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration tb_elem_behav_sd of tb_elem is
+
+  for behav
+
+    for dut_b : chip
+      use configuration work.chip_sd_c0;
+    end for;
+
+    for card_b : card
+      use configuration work.card_behav_c0;
+    end for;
+
+  end for;
+
+end tb_elem_behav_sd;
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem.vhd
new file mode 100644
index 000000000..689cec037
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem.vhd
@@ -0,0 +1,376 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Generic testbench element for a specific feature set
+--
+-- $Id: tb_elem.vhd,v 1.7 2005/04/07 20:43:36 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity tb_elem is
+
+  generic (
+    chip_type_g   : string := "none";
+    has_sd_card_g : integer := 1
+  );
+  port (
+    clk_i   : in  std_logic;
+    reset_i : in  std_logic;
+    eos_o   : out boolean
+  );
+
+end tb_elem;
+
+
+library ieee;
+use ieee.numeric_std.all;
+library std;
+use std.textio.all;
+
+use work.spi_boot_pack.all;
+use work.tb_pack.all;
+
+architecture behav of tb_elem is
+
+  component chip
+    port (
+      clk_i          : in  std_logic;
+      reset_i        : in  std_logic;
+      set_sel_n_i    : in  std_logic_vector(3 downto 0);
+      spi_clk_o      : out std_logic;
+      spi_cs_n_o     : out std_logic;
+      spi_data_in_i  : in  std_logic;
+      spi_data_out_o : out std_logic;
+      start_i        : in  std_logic;
+      mode_i         : in  std_logic;
+      config_n_o     : out std_logic;
+      detached_o     : out std_logic;
+      cfg_init_n_i   : in  std_logic;
+      cfg_done_i     : in  std_logic;
+      dat_done_i     : in  std_logic;
+      cfg_clk_o      : out std_logic;
+      cfg_dat_o      : out std_logic
+    );
+  end component;
+
+  component card
+    generic (
+      card_type_g  : string := "none";
+      is_sd_card_g : integer := 1
+    );
+    port (
+      spi_clk_i  : in  std_logic;
+      spi_cs_n_i : in  std_logic;
+      spi_data_i : in  std_logic;
+      spi_data_o : out std_logic
+    );
+  end component;
+
+  signal reset_s : std_logic;
+
+  -- SPI interface signals
+  signal spi_clk_s            : std_logic;
+  signal spi_data_to_card_s   : std_logic;
+  signal spi_data_from_card_s : std_logic;
+  signal spi_cs_n_s           : std_logic;
+
+  -- config related signals
+  signal start_s      : std_logic;
+  signal mode_s       : std_logic;
+  signal config_n_s   : std_logic;
+  signal cfg_init_n_s : std_logic;
+  signal cfg_done_s   : std_logic;
+  signal dat_done_s   : std_logic;
+  signal cfg_clk_s    : std_logic;
+  signal cfg_dat_s    : std_logic;
+  signal data_s       : unsigned(7 downto 0);
+
+  signal set_sel_n_s : std_logic_vector(3 downto 0);
+
+  constant verbose_c : boolean := false;
+
+begin
+
+  -- weak pull-ups
+  spi_clk_s          <= 'H';
+  spi_cs_n_s         <= 'H';
+  spi_data_to_card_s <= 'H';
+
+  -----------------------------------------------------------------------------
+  -- DUT
+  -----------------------------------------------------------------------------
+  dut_b : chip
+    port map (
+      clk_i          => clk_i,
+      reset_i        => reset_s,
+      set_sel_n_i    => set_sel_n_s,
+      spi_clk_o      => spi_clk_s,
+      spi_cs_n_o     => spi_cs_n_s,
+      spi_data_in_i  => spi_data_from_card_s,
+      spi_data_out_o => spi_data_to_card_s,
+      start_i        => start_s,
+      mode_i         => mode_s,
+      config_n_o     => config_n_s,
+      detached_o     => open,
+      cfg_init_n_i   => cfg_init_n_s,
+      cfg_done_i     => cfg_done_s,
+      dat_done_i     => dat_done_s,
+      cfg_clk_o      => cfg_clk_s,
+      cfg_dat_o      => cfg_dat_s
+    );
+
+  card_b : card
+    generic map (
+      card_type_g  => chip_type_g,
+      is_sd_card_g => has_sd_card_g
+    )
+    port map (
+      spi_clk_i  => spi_clk_s,
+      spi_cs_n_i => spi_cs_n_s,
+      spi_data_i => spi_data_to_card_s,
+      spi_data_o => spi_data_from_card_s
+    );
+
+
+  -----------------------------------------------------------------------------
+  -- DUT Stimuli
+  --
+  stim: process
+
+    procedure rise_cfg_clk(num : integer) is
+    begin
+      for i in 1 to num loop
+        wait until cfg_clk_s'event and cfg_clk_s = '1';
+      end loop;
+    end rise_cfg_clk;
+
+--     procedure fall_cfg_clk(num : integer) is
+--     begin
+--       for i in 1 to num loop
+--         wait until cfg_clk_s'event and cfg_clk_s = '0';
+--       end loop;
+--     end fall_cfg_clk;
+
+    procedure rise_clk(num : integer) is
+    begin
+      for i in 1 to num loop
+        wait until clk_i'event and clk_i = '1';
+      end loop;
+    end rise_clk;
+
+    procedure read_check_byte(ref : unsigned(7 downto 0)) is
+      variable byte_v : unsigned(7 downto 0);
+      variable dump_line : line;
+    begin
+      for bit in 7 downto 0 loop
+        rise_cfg_clk(1);
+        byte_v(bit) := cfg_dat_s;
+      end loop;
+      data_s <= byte_v;
+
+      if byte_v /= ref then
+        write(dump_line, chip_type_g);
+        write(dump_line, string'(" at "));
+        write(dump_line, now);
+        write(dump_line, string'(": read_check_byte failed "));
+        write(dump_line, to_integer(byte_v));
+        write(dump_line, string'(" "));
+        write(dump_line, to_integer(ref));
+        writeline(output, dump_line);
+      end if;
+    end read_check_byte;
+
+    variable dump_line : line;
+    variable addr_v    : unsigned(31 downto 0);
+    variable temp_v    : unsigned( 7 downto 0);
+    variable set_sel_v : unsigned(3 downto 0);
+
+  begin
+    -- default assignments
+    -- these defaults show the required pull resistors
+    -- except start_i as this must be pulled high for automatic start
+    start_s      <= '0';
+    mode_s       <= '1';
+    cfg_init_n_s <= '1';
+    cfg_done_s   <= '0';
+    dat_done_s   <= '1';
+    data_s       <= (others => '1');
+    addr_v       := (others => '0');
+    eos_o        <= false;
+    set_sel_n_s  <= (others => '1');
+    reset_s      <= '0';
+
+    -- loop through some sets
+    for set in 0 to 3 loop
+      set_sel_v := to_unsigned(set, 4);
+      addr_v(23 downto 20) := set_sel_v;  -- must match num_bits_per_img_g
+                                          -- plus width_img_cnt_g
+      set_sel_n_s <= not std_logic_vector(set_sel_v);
+
+      assert not verbose_c
+        report chip_type_g & ": Processing set " & to_string(set)
+        severity note;
+
+      wait for 100 us;
+      reset_s <= '1';
+
+      assert not verbose_c
+        report chip_type_g & ": Requesting image 0"
+        severity note;
+
+      -- signal start
+      start_s    <= '1';
+      mode_s     <= '1';
+      cfg_done_s <= '0';
+      addr_v(19 downto 0) := (others => '0');
+      wait until config_n_s = '0';
+      -- run through configuration sequence
+      rise_clk(1);
+      cfg_init_n_s <= '0';
+      rise_clk(3);
+      cfg_init_n_s <= '1';
+
+      -- and receive 32 bytes from image 0
+      for i in 1 to 32 loop
+        temp_v := addr_v(0) & calc_crc(addr_v);
+        read_check_byte(temp_v);
+        addr_v := addr_v + 1;
+      end loop;
+      start_s    <= '0';
+      cfg_done_s <= '1';
+
+      rise_clk(10);
+
+      assert not verbose_c
+        report chip_type_g & ": Requesting image 1"
+        severity note;
+
+      -- request next image
+      mode_s  <= '0';
+      start_s <= '1';
+      addr_v(17 downto  0) := (others => '0');
+      addr_v(19 downto 18) := "01"; -- must match num_bits_per_img_g in chip-*-a.vhd
+      dat_done_s <= '0';
+
+      -- receive another 32 bytes from image 1
+      for i in 1 to 32 loop
+        temp_v := addr_v(0) & calc_crc(addr_v);
+        read_check_byte(temp_v);
+        addr_v := addr_v + 1;
+      end loop;
+      start_s    <= '0';
+      dat_done_s <= '1';
+      
+
+      rise_clk(10);
+
+      assert not verbose_c
+        report chip_type_g & ": Requesting image 2"
+        severity note;
+
+      -- request next image
+      mode_s  <= '1';
+      start_s <= '1';
+      addr_v(17 downto  0) := (others => '0');
+      addr_v(19 downto 18) := "10"; -- must match num_bits_per_img_g in chip-*-a.vhd
+
+      wait until config_n_s = '0';
+      -- run through configuration sequence
+      rise_clk(1);
+      cfg_done_s   <= '0';
+      cfg_init_n_s <= '0';
+      rise_clk(3);
+      cfg_init_n_s <= '1';
+
+      -- receive another 32 bytes from image 2
+      for i in 1 to 32 loop
+        temp_v := addr_v(0) & calc_crc(addr_v);
+        read_check_byte(temp_v);
+        addr_v := addr_v + 1;
+      end loop;
+      start_s    <= '0';
+      cfg_done_s <= '1';
+
+      -- give dut a chance to stop current transfer
+      wait until spi_cs_n_s = '1';
+      rise_clk(10);
+
+      reset_s <= '0';
+    end loop;
+
+    eos_o <= true;
+    wait;
+  end process stim;
+  --
+  -----------------------------------------------------------------------------
+
+end behav;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: tb_elem.vhd,v $
+-- Revision 1.7  2005/04/07 20:43:36  arniml
+-- add new port detached_o
+--
+-- Revision 1.6  2005/03/09 19:48:04  arniml
+-- make verbosity level switchable
+--
+-- Revision 1.5  2005/03/08 22:06:21  arniml
+-- added set selection
+--
+-- Revision 1.4  2005/02/17 18:59:23  arniml
+-- clarify wording for images
+--
+-- Revision 1.3  2005/02/16 19:34:56  arniml
+-- add weak pull-ups for SPI lines
+--
+-- Revision 1.2  2005/02/13 17:14:03  arniml
+-- change dat_done handling
+--
+-- Revision 1.1  2005/02/08 21:09:20  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd
new file mode 100644
index 000000000..7534aafdc
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd
@@ -0,0 +1,93 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: tb_pack-p.vhd,v 1.2 2005/03/08 22:06:39 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package tb_pack is
+
+  function calc_crc(payload : in std_logic_vector) return std_logic_vector;
+  function calc_crc(payload : in unsigned) return unsigned;
+
+  function to_string(value : in integer) return string;
+
+end tb_pack;
+
+
+package body tb_pack is
+
+  function calc_crc(payload : in std_logic_vector) return std_logic_vector is
+
+    variable crc_v  : std_logic_vector(6 downto 0);
+    variable temp_v : std_logic;
+
+  begin
+
+    crc_v := (others => '0');
+
+    for i in payload'high downto payload'low loop
+      temp_v := payload(i) xor crc_v(6);
+
+      crc_v(6 downto 4) := crc_v(5 downto 3);
+      crc_v(3) := crc_v(2) xor temp_v;
+      crc_v(2 downto 1) := crc_v(1 downto 0);
+      crc_v(0) := temp_v;
+    end loop;
+
+    return crc_v;
+  end calc_crc;
+
+  function calc_crc(payload : in unsigned) return unsigned is
+  begin
+    return unsigned(calc_crc(std_logic_vector(payload)));
+  end calc_crc;
+
+  function to_string(value : in integer) return string is
+    variable str: string (11 downto 1);
+    variable val: integer := value;
+    variable digit: natural;
+    variable index: natural := 0;
+  begin
+    -- Taken from:
+    --  textio package body.  This file is part of GHDL.
+    --  Copyright (C) 2002 Tristan Gingold.
+    --  Note: the absolute value of VAL cannot be directly taken, since
+    --  it may be greather that the maximum value of an INTEGER.
+    loop
+      --  LRM93 7.2.6
+      --  (A rem B) has the sign of A and an absolute value less then
+      --   the absoulte value of B.
+      digit := abs (val rem 10);
+      val := val / 10;
+      index := index + 1;
+      str (index) := character'val(48 + digit);
+      exit when val = 0;
+    end loop;
+    if value < 0 then
+      index := index + 1;
+      str(index) := '-';
+    end if;
+
+    return str;
+  end to_string;
+
+end tb_pack;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: tb_pack-p.vhd,v $
+-- Revision 1.2  2005/03/08 22:06:39  arniml
+-- added integer->string conversion function
+--
+-- Revision 1.1  2005/02/08 21:09:20  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd
new file mode 100644
index 000000000..84273abc5
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd
@@ -0,0 +1,27 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: tb_rl-c.vhd,v 1.1 2005/04/10 18:07:26 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration tb_rl_behav_c0 of tb_rl is
+
+  for behav
+
+    for dut_b : chip
+      use configuration work.chip_full_c0;
+    end for;
+
+    for card_b : card
+      use configuration work.card_behav_c0;
+    end for;
+
+    for rl_b : ram_loader
+      use configuration work.ram_loader_rtl_c0;
+    end for;
+
+  end for;
+
+end tb_rl_behav_c0;
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_rl.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_rl.vhd
new file mode 100644
index 000000000..9f28e62b4
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_rl.vhd
@@ -0,0 +1,259 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Testbench for ram_loader
+--
+-- $Id: tb_rl.vhd,v 1.1 2005/04/10 18:07:25 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+entity tb_rl is
+
+end tb_rl;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_rl is
+
+  component chip
+    port (
+      clk_i          : in  std_logic;
+      reset_i        : in  std_logic;
+      set_sel_n_i    : in  std_logic_vector(3 downto 0);
+      spi_clk_o      : out std_logic;
+      spi_cs_n_o     : out std_logic;
+      spi_data_in_i  : in  std_logic;
+      spi_data_out_o : out std_logic;
+      start_i        : in  std_logic;
+      mode_i         : in  std_logic;
+      config_n_o     : out std_logic;
+      detached_o     : out std_logic;
+      cfg_init_n_i   : in  std_logic;
+      cfg_done_i     : in  std_logic;
+      dat_done_i     : in  std_logic;
+      cfg_clk_o      : out std_logic;
+      cfg_dat_o      : out std_logic
+    );
+  end component;
+
+  component card
+    generic (
+      card_type_g  : string := "none";
+      is_sd_card_g : integer := 1
+    );
+    port (
+      spi_clk_i  : in  std_logic;
+      spi_cs_n_i : in  std_logic;
+      spi_data_i : in  std_logic;
+      spi_data_o : out std_logic
+    );
+  end component;
+
+  component ram_loader
+    port (
+      clk_i      : in    std_logic;
+      reset_i    : in    std_logic;
+      lamp_o     : out   std_logic;
+      cfg_clk_i  : in    std_logic;
+      cfg_data_i : in    std_logic;
+      start_o    : out   std_logic;
+      mode_o     : out   std_logic;
+      done_o     : out   std_logic;
+      detached_i : in    std_logic;
+      ram_addr_o : out   std_logic_vector(15 downto 0);
+      ram_data_b : out   std_logic_vector( 7 downto 0);
+      ram_ce_no  : out   std_logic_vector( 3 downto 0);
+      ram_oe_no  : out   std_logic;
+      ram_we_no  : out   std_logic
+    );
+  end component;
+
+  constant period_c      : time := 100 ns;
+  constant rl_period_c   : time :=  20 ns;
+  constant reset_level_c : integer := 0;
+
+  signal clk_s   : std_logic;
+  signal rl_clk_s: std_logic;
+  signal reset_s : std_logic;
+
+  -- SPI interface signals
+  signal spi_clk_s            : std_logic;
+  signal spi_data_to_card_s   : std_logic;
+  signal spi_data_from_card_s : std_logic;
+  signal spi_cs_n_s           : std_logic;
+
+  -- config related signals
+  signal start_s      : std_logic;
+  signal mode_s       : std_logic;
+  signal config_n_s   : std_logic;
+  signal cfg_init_n_s : std_logic;
+  signal cfg_done_s   : std_logic;
+  signal dat_done_s   : std_logic;
+  signal cfg_clk_s    : std_logic;
+  signal cfg_dat_s    : std_logic;
+  signal detached_s   : std_logic;
+
+  signal set_sel_n_s : std_logic_vector(3 downto 0);
+
+begin
+
+  set_sel_n_s  <= (others => '1');
+  cfg_init_n_s <= '1';
+  cfg_done_s   <= '1';
+
+  -----------------------------------------------------------------------------
+  -- DUT
+  -----------------------------------------------------------------------------
+  dut_b : chip
+    port map (
+      clk_i          => clk_s,
+      reset_i        => reset_s,
+      set_sel_n_i    => set_sel_n_s,
+      spi_clk_o      => spi_clk_s,
+      spi_cs_n_o     => spi_cs_n_s,
+      spi_data_in_i  => spi_data_from_card_s,
+      spi_data_out_o => spi_data_to_card_s,
+      start_i        => start_s,
+      mode_i         => mode_s,
+      config_n_o     => config_n_s,
+      detached_o     => detached_s,
+      cfg_init_n_i   => cfg_init_n_s,
+      cfg_done_i     => cfg_done_s,
+      dat_done_i     => dat_done_s,
+      cfg_clk_o      => cfg_clk_s,
+      cfg_dat_o      => cfg_dat_s
+    );
+
+  card_b : card
+    generic map (
+      card_type_g  => "Full Chip",
+      is_sd_card_g => 1
+    )
+    port map (
+      spi_clk_i  => spi_clk_s,
+      spi_cs_n_i => spi_cs_n_s,
+      spi_data_i => spi_data_to_card_s,
+      spi_data_o => spi_data_from_card_s
+    );
+
+  rl_b : ram_loader
+    port map (
+      clk_i      => rl_clk_s,
+      reset_i    => reset_s,
+      lamp_o     => open,
+      cfg_clk_i  => cfg_clk_s,
+      cfg_data_i => cfg_dat_s,
+      start_o    => start_s,
+      mode_o     => mode_s,
+      done_o     => dat_done_s,
+      detached_i => detached_s,
+      ram_addr_o => open,
+      ram_data_b => open,
+      ram_ce_no  => open,
+      ram_oe_no  => open,
+      ram_we_no  => open
+    );
+
+  -----------------------------------------------------------------------------
+  -- Clock Generator
+  -----------------------------------------------------------------------------
+  clk: process
+  begin
+    clk_s <= '0';
+    wait for period_c / 2;
+    clk_s <= '1';
+    wait for period_c / 2;
+  end process clk;
+
+  rl_clk: process
+  begin
+    rl_clk_s <= '0';
+    wait for rl_period_c / 2;
+    rl_clk_s <= '1';
+    wait for rl_period_c / 2;
+  end process rl_clk;
+
+
+  -----------------------------------------------------------------------------
+  -- Reset Generator
+  -----------------------------------------------------------------------------
+  reset: process
+  begin
+    if reset_level_c = 0 then
+      reset_s <= '0';
+    else
+      reset_s <= '1';
+    end if;
+
+    wait for period_c * 4 + 10 ns;
+
+    reset_s <= not reset_s;
+
+    wait;
+  end process reset;
+
+
+  -----------------------------------------------------------------------------
+  -- End of Simulation
+  -----------------------------------------------------------------------------
+  eos: process
+  begin
+    wait for 4 ms;
+    assert false
+      report "No checks have been performed. Investigate waveforms."
+      severity note;
+    assert false
+      report "End of simulation."
+      severity failure;
+  end process eos;
+
+end behav;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: tb_rl.vhd,v $
+-- Revision 1.1  2005/04/10 18:07:25  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/doc/spi_boot.pdf b/fpga/usrp2/opencores/spi_boot/doc/spi_boot.pdf
new file mode 100644
index 000000000..a889c3f22
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/doc/spi_boot.pdf
diff --git a/fpga/usrp2/opencores/spi_boot/doc/spi_boot_schematic.pdf b/fpga/usrp2/opencores/spi_boot/doc/spi_boot_schematic.pdf
new file mode 100644
index 000000000..92755d5f3
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/doc/spi_boot_schematic.pdf
diff --git a/fpga/usrp2/opencores/spi_boot/doc/src/architecture.eps b/fpga/usrp2/opencores/spi_boot/doc/src/architecture.eps
new file mode 100644
index 000000000..3e70efdb1
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/doc/src/architecture.eps
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diff --git a/fpga/usrp2/opencores/spi_boot/doc/src/transfer.fig b/fpga/usrp2/opencores/spi_boot/doc/src/transfer.fig
new file mode 100644
index 000000000..3d1724050
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/doc/src/transfer.fig
@@ -0,0 +1,119 @@
+#FIG 3.2
+Landscape
+Center
+Metric
+A4      
+65.00
+Single
+-2
+1200 2
+6 2700 4725 4860 5445
+6 2970 4860 4590 5265
+4 1 0 50 0 16 10 0.0000 4 120 435 3780 5017 CMD18\001
+4 1 0 50 0 16 10 0.0000 4 120 1560 3780 5242 READ_MULTIPLE_BLOCKS\001
+-6
+2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5
+	 2745 4770 4815 4770 4815 5400 2745 5400 2745 4770
+-6
+6 3015 2745 4545 3465
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+	 3060 2790 4500 2790 4500 3420 3060 3420 3060 2790
+4 1 0 50 0 16 10 0.0000 4 120 705 3780 3150 Wait for start\001
+-6
+6 3015 3735 4545 4455
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+	 3780 3780 4500 4050 3780 4410 3060 4050 3780 3780
+4 1 0 50 0 16 10 0.0000 4 135 615 3780 4132 mode = 1?\001
+-6
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+	 3060 5760 4500 5760 4500 6390 3060 6390 3060 5760
+4 1 0 50 0 16 10 0.0000 4 120 645 3780 6120 Read block\001
+-6
+6 3015 6705 4545 7425
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+	 3780 6750 4500 7020 3780 7380 3060 7020 3780 6750
+4 1 0 50 0 16 10 0.0000 4 120 675 3780 7102 ???_done?\001
+-6
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+6 3105 7830 4455 8235
+4 1 0 50 0 16 10 0.0000 4 120 435 3780 7987 CMD12\001
+4 1 0 50 0 16 10 0.0000 4 120 1290 3780 8212 STOP_TRANSMISSION\001
+-6
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+-6
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+4 1 0 50 0 16 10 0.0000 4 135 960 6660 5130 Activate config_n\001
+-6
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+	 6660 5760 7380 6030 6660 6390 5940 6030 6660 5760
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+-6
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+	 5940 6750 7380 6750 7380 7380 5940 7380 5940 6750
+4 1 0 50 0 16 10 0.0000 4 135 1125 6660 7110 Deactivate config_n\001
+-6
+6 5895 7695 7425 8415
+2 3 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5
+	 6660 7740 7380 8010 6660 8370 5940 8010 6660 7740
+4 1 0 50 0 16 10 0.0000 4 135 915 6660 8092 cfg_init_n high?\001
+-6
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
+	1 1 1.00 45.00 90.00
+	 3780 3420 3780 3780
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
+	1 1 1.00 45.00 90.00
+	 3780 4410 3780 4770
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
+	1 1 1.00 45.00 90.00
+	 3780 5400 3780 5760
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
+	1 1 1.00 45.00 90.00
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+	1 1 1.00 45.00 90.00
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+	1 1 1.00 45.00 90.00
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+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
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+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
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+	 6660 5400 6660 5760
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
+	1 1 1.00 45.00 90.00
+	 6660 6390 6660 6750
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
+	1 1 1.00 45.00 90.00
+	 6660 7380 6660 7740
+4 0 0 50 0 16 10 0.0000 4 105 210 3870 7560 Yes\001
+4 0 0 50 0 16 10 0.0000 4 105 165 4590 6930 No\001
+4 0 0 50 0 16 10 0.0000 4 105 240 4770 3600 start\001
+4 2 0 50 0 16 10 0.0000 4 105 165 3690 4590 No\001
+4 0 0 50 0 16 10 0.0000 4 105 210 4590 3960 Yes\001
+4 0 0 50 0 16 10 0.0000 4 105 165 7470 5940 No\001
+4 2 0 50 0 16 10 0.0000 4 105 210 6570 6570 Yes\001
+4 0 0 50 0 16 10 0.0000 4 105 165 7470 7920 No\001
+4 0 0 50 0 16 10 0.0000 4 105 210 6750 8550 Yes\001
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-e.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-e.vhd
new file mode 100644
index 000000000..0bdd05aff
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-e.vhd
@@ -0,0 +1,91 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Chip toplevel
+--
+-- $Id: chip-e.vhd,v 1.3 2005/04/07 20:44:23 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity chip is
+
+  port (
+    -- System Interface -------------------------------------------------------
+    clk_i          : in  std_logic;
+    reset_i        : in  std_logic;
+    set_sel_n_i    : in  std_logic_vector(3 downto 0);
+    -- SD Card Interface ------------------------------------------------------
+    spi_clk_o      : out std_logic;
+    spi_cs_n_o     : out std_logic;
+    spi_data_in_i  : in  std_logic;
+    spi_data_out_o : out std_logic;
+    -- FPGA Configuration Interface -------------------------------------------
+    start_i        : in  std_logic;
+    mode_i         : in  std_logic;
+    config_n_o     : out std_logic;
+    detached_o     : out std_logic;
+    cfg_init_n_i   : in  std_logic;
+    cfg_done_i     : in  std_logic;
+    dat_done_i     : in  std_logic;
+    cfg_clk_o      : out std_logic;
+    cfg_dat_o      : out std_logic
+  );
+
+end chip;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: chip-e.vhd,v $
+-- Revision 1.3  2005/04/07 20:44:23  arniml
+-- add new port detached_o
+--
+-- Revision 1.2  2005/03/08 22:07:11  arniml
+-- added set selection
+--
+-- Revision 1.1  2005/02/08 20:41:30  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd
new file mode 100644
index 000000000..e43ecb3c4
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd
@@ -0,0 +1,164 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Chip toplevel design with full feature set
+--
+-- $Id: chip-full-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+architecture full of chip is
+
+  component spi_boot
+    generic (
+      width_set_sel_g      : integer := 4;
+      width_bit_cnt_g      : integer := 6;
+      width_img_cnt_g      : integer := 2;
+      num_bits_per_img_g   : integer := 18;
+      sd_init_g            : integer := 0;
+      mmc_compat_clk_div_g : integer := 0;
+      width_mmc_clk_div_g  : integer := 0;
+      reset_level_g        : integer := 0
+    );
+    port (
+      clk_i          : in  std_logic;
+      reset_i        : in  std_logic;
+      set_sel_i      : in  std_logic_vector(width_set_sel_g-1 downto 0);
+      spi_clk_o      : out std_logic;
+      spi_cs_n_o     : out std_logic;
+      spi_data_in_i  : in  std_logic;
+      spi_data_out_o : out std_logic;
+      spi_en_outs_o  : out std_logic;
+      start_i        : in  std_logic;
+      mode_i         : in  std_logic;
+      config_n_o     : out std_logic;
+      detached_o     : out std_logic;
+      cfg_init_n_i   : in  std_logic;
+      cfg_done_i     : in  std_logic;
+      dat_done_i     : in  std_logic;
+      cfg_clk_o      : out std_logic;
+      cfg_dat_o      : out std_logic
+    );
+  end component;
+
+  signal spi_clk_s      : std_logic;
+  signal spi_cs_n_s     : std_logic;
+  signal spi_data_out_s : std_logic;
+  signal spi_en_outs_s  : std_logic;
+
+  signal set_sel_s      : std_logic_vector(3 downto 0);
+
+begin
+
+  set_sel_s <= not set_sel_n_i;
+
+  spi_boot_b : spi_boot
+    generic map (
+      width_set_sel_g      => 4,        -- 16 sets
+      width_bit_cnt_g      => 12,       -- 512 bytes per block
+      width_img_cnt_g      => 2,        -- 4 images
+      num_bits_per_img_g   => 18,       -- 256 kByte per image
+      sd_init_g            => 1,        -- use SD specific initialization
+      mmc_compat_clk_div_g => 13,       -- MMC compat 400 kHz > 10 MHz / (13*2)
+      width_mmc_clk_div_g  => 4         -- need 5 bits for MMC compat divider
+    )
+    port map (
+      clk_i                => clk_i,
+      reset_i              => reset_i,
+      set_sel_i          => set_sel_s,
+      spi_clk_o            => spi_clk_s,
+      spi_cs_n_o           => spi_cs_n_s,
+      spi_data_in_i        => spi_data_in_i,
+      spi_data_out_o       => spi_data_out_s,
+      spi_en_outs_o        => spi_en_outs_s,
+      start_i              => start_i,
+      mode_i               => mode_i,
+      config_n_o           => config_n_o,
+      detached_o           => detached_o,
+      cfg_init_n_i         => cfg_init_n_i,
+      cfg_done_i           => cfg_done_i,
+      dat_done_i           => dat_done_i,
+      cfg_clk_o            => cfg_clk_o,
+      cfg_dat_o            => cfg_dat_o
+    );
+
+  -----------------------------------------------------------------------------
+  -- Three state drivers for SPI outputs.
+  -----------------------------------------------------------------------------
+  spi_clk_o      <=   spi_clk_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+  spi_cs_n_o     <=   spi_cs_n_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+  spi_data_out_o <=   spi_data_out_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+
+end full;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: chip-full-a.vhd,v $
+-- Revision 1.6  2005/04/07 20:44:23  arniml
+-- add new port detached_o
+--
+-- Revision 1.5  2005/03/09 19:48:34  arniml
+-- invert level of set_sel input
+--
+-- Revision 1.4  2005/03/08 22:07:12  arniml
+-- added set selection
+--
+-- Revision 1.3  2005/02/18 06:42:11  arniml
+-- clarify wording for images
+--
+-- Revision 1.2  2005/02/16 18:54:37  arniml
+-- added tri-state drivers for spi outputs
+--
+-- Revision 1.1  2005/02/08 20:41:31  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd
new file mode 100644
index 000000000..da88552c4
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd
@@ -0,0 +1,19 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: chip-full-c.vhd,v 1.1 2005/02/08 20:41:31 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration chip_full_c0 of chip is
+
+  for full
+
+    for spi_boot_b : spi_boot
+      use configuration work.spi_boot_rtl_c0;
+    end for;
+
+  end for;
+
+end chip_full_c0;
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd
new file mode 100644
index 000000000..090d0b79c
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd
@@ -0,0 +1,164 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Chip toplevel design with minimal feature set
+--
+-- $Id: chip-minimal-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+architecture minimal of chip is
+
+  component spi_boot
+    generic (
+      width_set_sel_g      : integer := 4;
+      width_bit_cnt_g      : integer := 6;
+      width_img_cnt_g      : integer := 2;
+      num_bits_per_img_g   : integer := 18;
+      sd_init_g            : integer := 0;
+      mmc_compat_clk_div_g : integer := 0;
+      width_mmc_clk_div_g  : integer := 0;
+      reset_level_g        : integer := 0
+    );
+    port (
+      clk_i          : in  std_logic;
+      reset_i        : in  std_logic;
+      set_sel_i      : in  std_logic_vector(width_set_sel_g-1 downto 0);
+      spi_clk_o      : out std_logic;
+      spi_cs_n_o     : out std_logic;
+      spi_data_in_i  : in  std_logic;
+      spi_data_out_o : out std_logic;
+      spi_en_outs_o  : out std_logic;
+      start_i        : in  std_logic;
+      mode_i         : in  std_logic;
+      config_n_o     : out std_logic;
+      detached_o     : out std_logic;
+      cfg_init_n_i   : in  std_logic;
+      cfg_done_i     : in  std_logic;
+      dat_done_i     : in  std_logic;
+      cfg_clk_o      : out std_logic;
+      cfg_dat_o      : out std_logic
+    );
+  end component;
+
+  signal spi_clk_s      : std_logic;
+  signal spi_cs_n_s     : std_logic;
+  signal spi_data_out_s : std_logic;
+  signal spi_en_outs_s  : std_logic;
+
+  signal set_sel_s      : std_logic_vector(3 downto 0);
+
+begin
+
+  set_sel_s <= not set_sel_n_i;
+
+  spi_boot_b : spi_boot
+    generic map (
+      width_set_sel_g      => 4,        -- 16 sets
+      width_bit_cnt_g      => 6,        -- 8 bytes per block
+      width_img_cnt_g      => 2,        -- 4 images
+      num_bits_per_img_g   => 18,       -- 256 kByte per image
+      sd_init_g            => 0,        -- no SD specific initialization
+      mmc_compat_clk_div_g => 0,        -- no MMC compatibility
+      width_mmc_clk_div_g  => 0         -- no MMC compatibility
+    )
+    port map (
+      clk_i                => clk_i,
+      reset_i              => reset_i,
+      set_sel_i            => set_sel_s,
+      spi_clk_o            => spi_clk_s,
+      spi_cs_n_o           => spi_cs_n_s,
+      spi_data_in_i        => spi_data_in_i,
+      spi_data_out_o       => spi_data_out_s,
+      spi_en_outs_o        => spi_en_outs_s,
+      start_i              => start_i,
+      mode_i               => mode_i,
+      config_n_o           => config_n_o,
+      detached_o           => detached_o,
+      cfg_init_n_i         => cfg_init_n_i,
+      cfg_done_i           => cfg_done_i,
+      dat_done_i           => dat_done_i,
+      cfg_clk_o            => cfg_clk_o,
+      cfg_dat_o            => cfg_dat_o
+    );
+
+  -----------------------------------------------------------------------------
+  -- Three state drivers for SPI outputs.
+  -----------------------------------------------------------------------------
+  spi_clk_o      <=   spi_clk_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+  spi_cs_n_o     <=   spi_cs_n_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+  spi_data_out_o <=   spi_data_out_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+
+end minimal;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: chip-minimal-a.vhd,v $
+-- Revision 1.6  2005/04/07 20:44:23  arniml
+-- add new port detached_o
+--
+-- Revision 1.5  2005/03/09 19:48:34  arniml
+-- invert level of set_sel input
+--
+-- Revision 1.4  2005/03/08 22:07:12  arniml
+-- added set selection
+--
+-- Revision 1.3  2005/02/18 06:42:12  arniml
+-- clarify wording for images
+--
+-- Revision 1.2  2005/02/16 18:54:39  arniml
+-- added tri-state drivers for spi outputs
+--
+-- Revision 1.1  2005/02/08 20:41:31  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd
new file mode 100644
index 000000000..5547747b2
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd
@@ -0,0 +1,19 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: chip-minimal-c.vhd,v 1.1 2005/02/08 20:41:32 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration chip_minimal_c0 of chip is
+
+  for minimal
+
+    for spi_boot_b : spi_boot
+      use configuration work.spi_boot_rtl_c0;
+    end for;
+
+  end for;
+
+end chip_minimal_c0;
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd
new file mode 100644
index 000000000..cef42d268
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd
@@ -0,0 +1,164 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Chip toplevel design with MMC feature set
+--
+-- $Id: chip-mmc-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+architecture mmc of chip is
+
+  component spi_boot
+    generic (
+      width_set_sel_g      : integer := 4;
+      width_bit_cnt_g      : integer := 6;
+      width_img_cnt_g      : integer := 2;
+      num_bits_per_img_g   : integer := 18;
+      sd_init_g            : integer := 0;
+      mmc_compat_clk_div_g : integer := 0;
+      width_mmc_clk_div_g  : integer := 0;
+      reset_level_g        : integer := 0
+    );
+    port (
+      clk_i          : in  std_logic;
+      reset_i        : in  std_logic;
+      set_sel_i      : in  std_logic_vector(width_set_sel_g-1 downto 0);
+      spi_clk_o      : out std_logic;
+      spi_cs_n_o     : out std_logic;
+      spi_data_in_i  : in  std_logic;
+      spi_data_out_o : out std_logic;
+      spi_en_outs_o  : out std_logic;
+      start_i        : in  std_logic;
+      mode_i         : in  std_logic;
+      config_n_o     : out std_logic;
+      detached_o     : out std_logic;
+      cfg_init_n_i   : in  std_logic;
+      cfg_done_i     : in  std_logic;
+      dat_done_i     : in  std_logic;
+      cfg_clk_o      : out std_logic;
+      cfg_dat_o      : out std_logic
+    );
+  end component;
+
+  signal spi_clk_s      : std_logic;
+  signal spi_cs_n_s     : std_logic;
+  signal spi_data_out_s : std_logic;
+  signal spi_en_outs_s  : std_logic;
+
+  signal set_sel_s      : std_logic_vector(3 downto 0);
+
+begin
+
+  set_sel_s <= not set_sel_n_i;
+
+  spi_boot_b : spi_boot
+    generic map (
+      width_set_sel_g      => 4,        -- 16 sets
+      width_bit_cnt_g      => 12,       -- 512 bytes per block
+      width_img_cnt_g      => 2,        -- 4 images
+      num_bits_per_img_g   => 18,       -- 256 kByte per image
+      sd_init_g            => 0,        -- no SD specific initialization
+      mmc_compat_clk_div_g => 13,       -- MMC compat 400 kHz > 10 MHz / (13*2)
+      width_mmc_clk_div_g  => 4         -- need 5 bits for MMC compat divider
+    )
+    port map (
+      clk_i                => clk_i,
+      reset_i              => reset_i,
+      set_sel_i            => set_sel_s,
+      spi_clk_o            => spi_clk_s,
+      spi_cs_n_o           => spi_cs_n_s,
+      spi_data_in_i        => spi_data_in_i,
+      spi_data_out_o       => spi_data_out_s,
+      spi_en_outs_o        => spi_en_outs_s,
+      start_i              => start_i,
+      mode_i               => mode_i,
+      config_n_o           => config_n_o,
+      detached_o           => detached_o,
+      cfg_init_n_i         => cfg_init_n_i,
+      cfg_done_i           => cfg_done_i,
+      dat_done_i           => dat_done_i,
+      cfg_clk_o            => cfg_clk_o,
+      cfg_dat_o            => cfg_dat_o
+    );
+
+  -----------------------------------------------------------------------------
+  -- Three state drivers for SPI outputs.
+  -----------------------------------------------------------------------------
+  spi_clk_o      <=   spi_clk_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+  spi_cs_n_o     <=   spi_cs_n_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+  spi_data_out_o <=   spi_data_out_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+
+end mmc;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: chip-mmc-a.vhd,v $
+-- Revision 1.6  2005/04/07 20:44:23  arniml
+-- add new port detached_o
+--
+-- Revision 1.5  2005/03/09 19:48:34  arniml
+-- invert level of set_sel input
+--
+-- Revision 1.4  2005/03/08 22:07:12  arniml
+-- added set selection
+--
+-- Revision 1.3  2005/02/18 06:42:13  arniml
+-- clarify wording for images
+--
+-- Revision 1.2  2005/02/16 18:54:39  arniml
+-- added tri-state drivers for spi outputs
+--
+-- Revision 1.1  2005/02/08 20:41:32  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd
new file mode 100644
index 000000000..6131013e4
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd
@@ -0,0 +1,19 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: chip-mmc-c.vhd,v 1.1 2005/02/08 20:41:32 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration chip_mmc_c0 of chip is
+
+  for mmc
+
+    for spi_boot_b : spi_boot
+      use configuration work.spi_boot_rtl_c0;
+    end for;
+
+  end for;
+
+end chip_mmc_c0;
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd
new file mode 100644
index 000000000..c955a5f3a
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd
@@ -0,0 +1,164 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Chip toplevel design with SD feature set
+--
+-- $Id: chip-sd-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+architecture sd of chip is
+
+  component spi_boot
+    generic (
+      width_set_sel_g      : integer := 4;
+      width_bit_cnt_g      : integer := 6;
+      width_img_cnt_g      : integer := 2;
+      num_bits_per_img_g   : integer := 18;
+      sd_init_g            : integer := 0;
+      mmc_compat_clk_div_g : integer := 0;
+      width_mmc_clk_div_g  : integer := 0;
+      reset_level_g        : integer := 0
+    );
+    port (
+      clk_i          : in  std_logic;
+      reset_i        : in  std_logic;
+      set_sel_i      : in  std_logic_vector(width_set_sel_g-1 downto 0);
+      spi_clk_o      : out std_logic;
+      spi_cs_n_o     : out std_logic;
+      spi_data_in_i  : in  std_logic;
+      spi_data_out_o : out std_logic;
+      spi_en_outs_o  : out std_logic;
+      start_i        : in  std_logic;
+      mode_i         : in  std_logic;
+      config_n_o     : out std_logic;
+      detached_o     : out std_logic;
+      cfg_init_n_i   : in  std_logic;
+      cfg_done_i     : in  std_logic;
+      dat_done_i     : in  std_logic;
+      cfg_clk_o      : out std_logic;
+      cfg_dat_o      : out std_logic
+    );
+  end component;
+
+  signal spi_clk_s      : std_logic;
+  signal spi_cs_n_s     : std_logic;
+  signal spi_data_out_s : std_logic;
+  signal spi_en_outs_s  : std_logic;
+
+  signal set_sel_s      : std_logic_vector(3 downto 0);
+
+begin
+
+  set_sel_s <= not set_sel_n_i;
+
+  spi_boot_b : spi_boot
+    generic map (
+      width_set_sel_g      => 4,        -- 16 sets
+      width_bit_cnt_g      => 12,       -- 512 bytes per block
+      width_img_cnt_g      => 2,        -- 4 images
+      num_bits_per_img_g   => 18,       -- 256 kByte per image
+      sd_init_g            => 1,        -- SD specific initialization
+      mmc_compat_clk_div_g => 0,        -- no MMC compatibility
+      width_mmc_clk_div_g  => 0         -- no MMC compatibility
+    )
+    port map (
+      clk_i                => clk_i,
+      reset_i              => reset_i,
+      set_sel_i            => set_sel_s,
+      spi_clk_o            => spi_clk_s,
+      spi_cs_n_o           => spi_cs_n_s,
+      spi_data_in_i        => spi_data_in_i,
+      spi_data_out_o       => spi_data_out_s,
+      spi_en_outs_o        => spi_en_outs_s,
+      start_i              => start_i,
+      mode_i               => mode_i,
+      config_n_o           => config_n_o,
+      detached_o           => detached_o,
+      cfg_init_n_i         => cfg_init_n_i,
+      cfg_done_i           => cfg_done_i,
+      dat_done_i           => dat_done_i,
+      cfg_clk_o            => cfg_clk_o,
+      cfg_dat_o            => cfg_dat_o
+    );
+
+  -----------------------------------------------------------------------------
+  -- Three state drivers for SPI outputs.
+  -----------------------------------------------------------------------------
+  spi_clk_o      <=   spi_clk_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+  spi_cs_n_o     <=   spi_cs_n_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+  spi_data_out_o <=   spi_data_out_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+
+end sd;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: chip-sd-a.vhd,v $
+-- Revision 1.6  2005/04/07 20:44:23  arniml
+-- add new port detached_o
+--
+-- Revision 1.5  2005/03/09 19:48:34  arniml
+-- invert level of set_sel input
+--
+-- Revision 1.4  2005/03/08 22:07:12  arniml
+-- added set selection
+--
+-- Revision 1.3  2005/02/18 06:42:14  arniml
+-- clarify wording for images
+--
+-- Revision 1.2  2005/02/16 18:54:39  arniml
+-- added tri-state drivers for spi outputs
+--
+-- Revision 1.1  2005/02/08 20:41:32  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd
new file mode 100644
index 000000000..91e41ddfb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd
@@ -0,0 +1,19 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: chip-sd-c.vhd,v 1.1 2005/02/08 20:41:33 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration chip_sd_c0 of chip is
+
+  for sd
+
+    for spi_boot_b : spi_boot
+      use configuration work.spi_boot_rtl_c0;
+    end for;
+
+  end for;
+
+end chip_sd_c0;
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd
new file mode 100644
index 000000000..8b26c4d57
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd
@@ -0,0 +1,10 @@
+-------------------------------------------------------------------------------
+-- $Id: ram_loader-c.vhd,v 1.1 2005/04/10 18:02:32 arniml Exp $
+-------------------------------------------------------------------------------
+
+configuration ram_loader_rtl_c0 of ram_loader is
+
+  for rtl
+  end for;
+
+end ram_loader_rtl_c0;
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd
new file mode 100644
index 000000000..c604876d7
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd
@@ -0,0 +1,355 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Sample client for loading an image to asynchronous SRAM
+--
+-- $Id: ram_loader.vhd,v 1.2 2005/04/10 17:17:23 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity ram_loader is
+
+  port (
+    -- Global Interface -------------------------------------------------------
+    clk_i      : in    std_logic;
+    reset_i    : in    std_logic;
+    lamp_o     : out   std_logic;
+    -- Config Interface -------------------------------------------------------
+    cfg_clk_i  : in    std_logic;
+    cfg_data_i : in    std_logic;
+    start_o    : out   std_logic;
+    mode_o     : out   std_logic;
+    done_o     : out   std_logic;
+    detached_i : in    std_logic;
+    -- Asynchronous RAM Interface ---------------------------------------------
+    ram_addr_o : out   std_logic_vector(15 downto 0);
+    ram_data_b : out   std_logic_vector( 7 downto 0);
+    ram_ce_no  : out   std_logic_vector( 3 downto 0);
+    ram_oe_no  : out   std_logic;
+    ram_we_no  : out   std_logic
+  );
+
+end ram_loader;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture rtl of ram_loader is
+
+  signal addr_q     : unsigned(17 downto 0);
+  signal inc_addr_s : boolean;
+
+  signal shift_dat_q : std_logic_vector(7 downto 0);
+  signal ser_dat_q   : std_logic_vector(7 downto 0);
+  signal bit_q       : unsigned(2 downto 0);
+  signal bit_ovfl_q  : boolean;
+
+  type fsm_t is (IDLE,
+                 WE_ON,
+                 WE_OFF,
+                 INC_ADDR1, INC_ADDR2,
+                 FINISHED);
+  signal fsm_s,
+         fsm_q  : fsm_t;
+  signal done_q          : std_logic;
+  signal done_s          : boolean;
+  signal mode_q,
+         mode_s          : std_logic;
+
+  signal ram_we_n_q,
+         ram_we_n_s  : std_logic;
+  signal ram_ce_n_q,
+         ram_ce_n_s  : std_logic_vector(3 downto 0);
+
+  type start_fsm_t is (WAIT_DETACH,
+                       CHECK_NO_DONE,
+                       WAIT_DONE);
+  signal start_fsm_s,
+         start_fsm_q  : start_fsm_t;
+
+  signal start_s,
+         start_q         : std_logic;
+  signal enable_s,
+         enable_q        : boolean;
+
+begin
+
+  -----------------------------------------------------------------------------
+  -- Process seq
+  --
+  -- Purpose:
+  --   Implements the sequential elements clocked with cfg_clk_i.
+  --
+  seq: process (cfg_clk_i, reset_i)
+  begin
+    if reset_i = '0' then
+      addr_q      <= (others => '0');
+      shift_dat_q <= (others => '0');
+      ser_dat_q   <= (others => '0');
+      bit_q       <= (others => '0');
+      bit_ovfl_q  <= false;
+      fsm_q       <= IDLE;
+      ram_we_n_q  <= '1';
+      ram_ce_n_q  <= (others => '1');
+      done_q      <= '0';
+      mode_q      <= '0';
+
+    elsif cfg_clk_i'event and cfg_clk_i = '1' then
+      if inc_addr_s then
+        addr_q <= addr_q + 1;
+      end if;
+
+      if enable_q then
+        bit_q      <= bit_q + 1;
+        bit_ovfl_q <= bit_q = 7;
+
+        shift_dat_q(0) <= cfg_data_i;
+        shift_dat_q(7 downto 1) <= shift_dat_q(6 downto 0);
+      end if;
+
+      -- update register when 8 serial bits have been shifted in
+      if bit_ovfl_q then
+        ser_dat_q <= shift_dat_q;
+      end if;
+
+      fsm_q <= fsm_s;
+
+      ram_we_n_q <= ram_we_n_s;
+      ram_ce_n_q <= ram_ce_n_s;
+
+      -- done only settable once
+      if done_s then
+        done_q <= '1';
+      end if;
+
+      mode_q <= mode_s;
+
+    end if;
+  end process seq;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Process fsm
+  --
+  -- Purpose:
+  --   Implements the combinational logic of the RAM loader FSM.
+  --
+  fsm: process (fsm_q,
+                bit_ovfl_q,
+                start_q,
+                addr_q)
+  begin
+    -- default assignments
+    inc_addr_s      <= false;
+    ram_we_n_s      <= '1';
+    done_s          <= false;
+    fsm_s           <= IDLE;
+    lamp_o          <= '1';
+    mode_s          <= '0';
+
+    case fsm_q is
+      when IDLE =>
+        lamp_o <= '0';
+        if start_q = '1' then
+          if bit_ovfl_q then
+            fsm_s <= WE_ON;
+          end if;
+        end if;
+
+      when WE_ON =>
+        ram_we_n_s <= '0';
+        fsm_s      <= WE_OFF;
+
+      when WE_OFF =>
+        fsm_s <= INC_ADDR1;
+
+      when INC_ADDR1 =>
+        fsm_s      <= INC_ADDR2;
+
+      when INC_ADDR2 =>
+        if addr_q = "001111111111111111" then  -- load only 64k
+          fsm_s <= FINISHED;
+          done_s <= true;
+          mode_s <= '1';
+        else
+          inc_addr_s <= true;
+          fsm_s      <= IDLE;
+        end if;
+
+      when FINISHED =>
+        fsm_s  <= FINISHED;
+        lamp_o <= '1';
+        mode_s <= '1';
+
+      when others =>
+    end case;
+
+  end process fsm;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Process ce_gen
+  --
+  -- Purpose:
+  --   Generates the four CE signals for the external RAM chips.
+  --
+  ce_gen: process (addr_q)
+  begin
+    ram_ce_n_s <= (others => '1');
+    ram_ce_n_s(to_integer(addr_q(17 downto 16))) <= '0';
+  end process ce_gen;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Process start_seq
+  --
+  -- Purpose:
+  --   Implements the sequential elements clocked with clk_i.
+  --
+  start_seq: process (clk_i, reset_i)
+  begin
+    if reset_i = '0' then
+      start_fsm_q <= WAIT_DETACH;
+      start_q     <= '0';
+      enable_q    <= false;
+
+    elsif clk_i'event and clk_i = '1' then
+      start_fsm_q <= start_fsm_s;
+
+      enable_q    <= enable_s;
+
+      start_q     <= start_s;
+
+    end if;
+  end process start_seq;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Process start_comb
+  --
+  -- Purpose:
+  --   Implements the combinational logic of the start FSM.
+  --
+  start_comb: process (start_fsm_q,
+                       detached_i,
+                       done_q,
+                       enable_q,
+                       start_q)
+  begin
+    -- default assignments
+    start_fsm_s <= WAIT_DETACH;
+    enable_s    <= enable_q;
+    start_s     <= start_q;
+
+    case start_fsm_q is
+      -- Wait for detached_i to become '1'
+      -- This state is entered/left twice:
+      -- 1. after reset to start the data download
+      -- 2. after data download to start the next configuration cycle
+      when WAIT_DETACH =>
+        if detached_i = '1' then
+          start_fsm_s <= CHECK_NO_DONE;
+          enable_s    <= true;
+          start_s     <= '1';
+
+        else
+          start_fsm_s <= WAIT_DETACH;
+        end if;
+
+      -- Wait until done_q is '0'
+      -- This ensures that the FSM stalls when it has started the configuration
+      -- download. There must be no further action in this case.
+      when CHECK_NO_DONE =>
+        if done_q = '0' then
+          start_fsm_s <= WAIT_DONE;
+        else
+          start_fsm_s <= CHECK_NO_DONE;
+        end if;
+
+      -- Wait until done_q is '1'
+      -- done_q is the signal that the main FSM has finished its work. We
+      -- need to start the configuration download.
+      when WAIT_DONE =>
+        if done_q = '1' then
+          start_fsm_s <= WAIT_DETACH;
+          enable_s    <= false;
+          start_s     <= '0';
+        else
+          start_fsm_s <= WAIT_DONE;
+        end if;
+
+      when others =>
+        null;
+
+    end case;
+
+  end process start_comb;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Output Mapping
+  -----------------------------------------------------------------------------
+  start_o    <= start_q;
+  mode_o     <= mode_q;
+  done_o     <=   done_q
+                when start_q = '1' else
+                  '1';
+  ram_addr_o <= std_logic_vector(addr_q(15 downto 0));
+  ram_data_b <= ser_dat_q;
+  ram_oe_no  <= '1';
+  ram_ce_no  <= ram_ce_n_q;
+  ram_we_no  <= ram_we_n_q;
+
+end rtl;
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd
new file mode 100644
index 000000000..6f11ed34b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd
@@ -0,0 +1,27 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: spi_boot-c.vhd,v 1.2 2005/02/18 06:42:11 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration spi_boot_rtl_c0 of spi_boot is
+
+  for rtl
+
+    for img_cnt
+      for img_cnt_b : spi_counter
+        use configuration work.spi_counter_rtl_c0;
+      end for;
+    end for;
+
+    for mmc_cnt
+      for mmc_cnt_b : spi_counter
+        use configuration work.spi_counter_rtl_c0;
+      end for;
+    end for;
+
+  end for;
+
+end spi_boot_rtl_c0;
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot.vhd
new file mode 100644
index 000000000..3d2b81da7
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot.vhd
@@ -0,0 +1,979 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: spi_boot.vhd,v 1.9 2007/02/25 18:24:12 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity spi_boot is
+
+  generic (
+    -- width of set selection
+    width_set_sel_g      : integer := 4;
+    -- width of bit counter: minimum 6, maximum 12
+    width_bit_cnt_g      : integer := 6;
+    -- width of image counter: minimum 0, maximum n
+    width_img_cnt_g      : integer := 2;
+    -- number of bits required to address one image
+    num_bits_per_img_g   : integer := 18;
+    -- SD specific initialization
+    sd_init_g            : integer := 0;
+    -- clock divider to reach 400 kHz for MMC compatibility
+    mmc_compat_clk_div_g : integer := 0;
+    width_mmc_clk_div_g  : integer := 0;
+    -- active level of reset_i
+    reset_level_g        : integer := 0
+  );
+
+  port (
+    -- System Interface -------------------------------------------------------
+    clk_i          : in  std_logic;
+    reset_i        : in  std_logic;
+    set_sel_i      : in  std_logic_vector(width_set_sel_g-1 downto 0);
+    -- Card Interface ---------------------------------------------------------
+    spi_clk_o      : out std_logic;
+    spi_cs_n_o     : out std_logic;
+    spi_data_in_i  : in  std_logic;
+    spi_data_out_o : out std_logic;
+    spi_en_outs_o  : out std_logic;
+    -- FPGA Configuration Interface -------------------------------------------
+    start_i        : in  std_logic;
+    mode_i         : in  std_logic;
+    config_n_o     : out std_logic;
+    detached_o     : out std_logic;
+    cfg_init_n_i   : in  std_logic;
+    cfg_done_i     : in  std_logic;
+    dat_done_i     : in  std_logic;
+    cfg_clk_o      : out std_logic;
+    cfg_dat_o      : out std_logic
+  );
+
+end spi_boot;
+
+
+library ieee;
+use ieee.numeric_std.all;
+use work.spi_boot_pack.all;
+
+architecture rtl of spi_boot is
+
+  component spi_counter
+    generic (
+      cnt_width_g   : integer := 4;
+      cnt_max_g     : integer := 15
+    );
+    port (
+      clk_i      : in  std_logic;
+      reset_i    : in  boolean;
+      cnt_en_i   : in  boolean;
+      cnt_o      : out std_logic_vector(cnt_width_g-1 downto 0);
+      cnt_ovfl_o : out boolean
+    );
+  end component;
+
+
+  -----------------------------------------------------------------------------
+  -- States of the controller FSM
+  --
+  type ctrl_states_t is (POWER_UP1, POWER_UP2,
+                         CMD0,
+                         CMD1,
+                         CMD55, ACMD41,
+                         CMD16,
+                         WAIT_START,
+                         WAIT_INIT_LOW, WAIT_INIT_HIGH,
+                         CMD18, CMD18_DATA,
+                         CMD12,
+                         INC_IMG_CNT);
+  --
+  signal ctrl_fsm_q,
+         ctrl_fsm_s  : ctrl_states_t;
+  --
+  -----------------------------------------------------------------------------
+
+  -----------------------------------------------------------------------------
+  -- States of the command FSM
+  --
+  type cmd_states_t is (CMD, START, R1, PAUSE);
+  --
+  signal cmd_fsm_q,
+         cmd_fsm_s  : cmd_states_t;
+  --
+  -----------------------------------------------------------------------------
+
+  subtype op_r     is integer range 5 downto 0;
+  type    res_bc_t is (NONE, RES_MAX, RES_47, RES_15, RES_7);
+  signal  bit_cnt_q  : unsigned(width_bit_cnt_g-1 downto 0);
+  signal  res_bc_s   : res_bc_t;
+  signal  upper_bitcnt_zero_s : boolean;
+
+  signal cfg_dat_q : std_logic;
+
+  signal spi_clk_q         : std_logic;
+  signal spi_clk_rising_q  : boolean;
+  signal spi_clk_falling_q : boolean;
+  signal spi_dat_q,
+         spi_dat_s         : std_logic;
+  signal spi_cs_n_q,
+         spi_cs_n_s        : std_logic;
+
+  signal cfg_clk_q      : std_logic;
+
+  signal start_q        : std_logic;
+
+  signal img_cnt_s      : std_logic_vector(width_img_cnt_g downto 0);
+  signal cnt_en_img_s   : boolean;
+  signal mmc_cnt_ovfl_s : boolean;
+  signal mmc_compat_s   : boolean;
+
+  signal cmd_finished_s : boolean;
+
+  signal r1_result_q    : std_logic;
+  signal done_q,
+         send_cmd12_q   : boolean;
+
+  signal en_outs_s,
+         en_outs_q      : boolean;
+
+  signal reset_s        : boolean;
+
+  signal true_s         : boolean;
+
+begin
+
+  true_s <= true;
+
+  reset_s <=   true
+             when (reset_level_g = 1 and reset_i = '1') or
+                  (reset_level_g = 0 and reset_i = '0') else
+               false;
+
+  -----------------------------------------------------------------------------
+  -- Process seq
+  --
+  -- Purpose:
+  --   Implements several sequential elements.
+  --
+  seq: process (clk_i, reset_s)
+
+    variable bit_cnt_v : unsigned(1 downto 0);
+
+  begin
+    if reset_s then
+      -- reset bit counter to 63 for power up
+      bit_cnt_q       <= (others => '0');
+      bit_cnt_q(op_r) <= "111111";
+      spi_dat_q    <= '1';
+      spi_cs_n_q   <= '1';
+      cfg_dat_q    <= '1';
+      start_q      <= '0';
+      done_q       <= false;
+      send_cmd12_q <= false;
+      ctrl_fsm_q   <= POWER_UP1;
+      cmd_fsm_q    <= CMD;
+      r1_result_q  <= '0';
+      en_outs_q    <= false;
+
+    elsif clk_i'event and clk_i = '1' then
+      -- bit counter control
+      if spi_clk_rising_q then
+        case res_bc_s is
+          when NONE =>
+            bit_cnt_q       <= bit_cnt_q - 1;
+          when RES_MAX =>
+            bit_cnt_q       <= (others => '1');
+          when RES_47 =>
+            bit_cnt_q       <= (others => '0');
+            bit_cnt_q(op_r) <= "101111";
+          when RES_15 =>
+            bit_cnt_q       <= (others => '0');
+            bit_cnt_q(op_r) <= "001111";
+          when RES_7 =>
+            bit_cnt_q       <= (others => '0');
+            bit_cnt_q(op_r) <= "000111";
+          when others =>
+            bit_cnt_q       <= (others => '0');
+        end case;
+      end if;
+
+      -- Card data output register
+      -- spi_clk_falling_q acts as enable during MMC clock compatibility mode.
+      -- As soon as this mode is left, the register must start latching.
+      -- There is no explicit relation to spi_clk_q anymore in normal mode.
+      -- Instead, spi_dat_s is operated by bit_cnt_q above which changes its
+      -- value after the rising edge of spi_clk_q.
+      --   -> spi_dat_q changes upon falling edge of spi_clk_q
+      if spi_clk_falling_q or not mmc_compat_s then
+        spi_dat_q <= spi_dat_s;
+      end if;
+
+      -- config data output register
+      -- a new value is loaded when config clock is high,
+      -- i.e. input data is sampled with rising spi_clk
+      -- while output value changes on falling edge of cfg_clk
+      if cfg_clk_q = '1' and spi_clk_rising_q then
+        cfg_dat_q <= spi_data_in_i;
+      end if;
+
+      -- Controller FSM state
+      ctrl_fsm_q <= ctrl_fsm_s;
+
+      -- Command FSM state
+      cmd_fsm_q <= cmd_fsm_s;
+
+      -- CS signal for SPI card
+      if spi_clk_q = '1' then
+        spi_cs_n_q <= spi_cs_n_s;
+      end if;
+
+      -- Extract flags from R1 response
+      if cmd_fsm_q = R1 then
+        bit_cnt_v := bit_cnt_q(1 downto 0);
+        case bit_cnt_v(1 downto 0) is
+          when "10" =>
+            -- always save "Illegal Command" flag
+            r1_result_q <= to_X01(spi_data_in_i);
+          when "00" =>
+            -- overwrite with "Idle State" flag when not in CMD55
+            if ctrl_fsm_q /= CMD55 then
+              r1_result_q <= to_X01(spi_data_in_i);
+            end if;
+          when others =>
+            null;
+        end case;
+      end if;
+
+      -- Start trigger register for rising edge detection
+      -- the reset value is '0' thus a rising edge will always be detected
+      -- after reset even though start_i is tied to '1'
+      if start_i = '0' then
+        start_q <= '0';
+      elsif ctrl_fsm_q = WAIT_START and cmd_finished_s then
+        start_q <= start_i;
+      end if;
+
+      -- Marker for cfg_done and dat_done
+      if ctrl_fsm_q = CMD18_DATA then
+        if cfg_done_i = '1' and dat_done_i = '1' then
+          done_q       <= true;
+        end if;
+
+        if done_q and
+           (not upper_bitcnt_zero_s or cmd_fsm_q = START) then
+          -- activate sending of CMD12 when it is safe:
+          -- * upper bits of bit counter are not zero
+          --   -> transmission of CMD12 is not running
+          -- * cmd FSM is in START state
+          --   -> also no transmission running
+          send_cmd12_q <= true;
+        end if;
+      elsif ctrl_fsm_q = WAIT_START then
+        -- reset done_q when WAIT_START has been reached
+        -- this is necessary to let the stop transmission process come to
+        -- an end without interruption or generation of unwanted cfg_clk_q
+        done_q         <= false;
+        send_cmd12_q   <= false;
+      end if;
+
+      -- output enable
+      if spi_clk_rising_q then
+        en_outs_q <= en_outs_s;
+      end if;
+
+    end if;
+
+  end process seq;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Process upper_bits
+  --
+  -- Purpose:
+  --   Detects that the upper bits of the bit counter are zero.
+  --   Upper bits = n downto 6, i.e. the optional part that is not required for
+  --   commands but for extension of data blocks.
+  --
+  upper_bits: process (bit_cnt_q)
+    variable zero_v : boolean;
+  begin
+
+    zero_v     := true;
+    for i in bit_cnt_q'high downto 6 loop
+      if bit_cnt_q(i) = '1' then
+        zero_v := false;
+      end if;
+    end loop;
+
+    upper_bitcnt_zero_s <= zero_v;
+
+  end process upper_bits;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Process clk_gen
+  --
+  -- Purpose:
+  --   Generates clocks for card and FPGA configuration.
+  --   The card clock is free running with a divide by two of clk_i.
+  --   The clock for FPGA config has an enable and is stopped on high level.
+  --   There is a phase shift of half a period between spi_clk and cfg_clk.
+  --
+  clk_gen: process (clk_i, reset_s)
+  begin
+    if reset_s then
+      spi_clk_q        <= '0';
+      cfg_clk_q        <= '1';
+
+    elsif clk_i'event and clk_i = '1' then
+
+      -- spi_clk_q rises according to the flag
+      -- it falls with overflow indication
+      -- the resulting duty cycle is not exactly 50:50,
+      -- high time is a bit longer
+      if mmc_compat_s then
+        -- MMC clock compatibility mode:
+        -- spi_clk_q rises when flagged by spi_clk_rising_q
+        if spi_clk_rising_q then
+          spi_clk_q <= '1';
+        elsif mmc_cnt_ovfl_s then
+          -- upon counter overflow spi_clk_q falls in case it does not rise
+          spi_clk_q <= '0';
+        end if;
+      else
+        -- normal mode
+        -- spi_clk_q follows spi_clk_rising_q
+        if spi_clk_rising_q then
+          spi_clk_q <= '1';
+        else
+          spi_clk_q <= '0';
+        end if;
+      end if;
+
+      -- clock for FPGA config must be enabled and follows spi_clk
+      if ctrl_fsm_q = CMD18_DATA and cmd_fsm_q = CMD and
+         not done_q then
+        cfg_clk_q <= spi_clk_q;
+      else
+        cfg_clk_q <= '1';
+      end if;
+
+    end if;
+
+  end process clk_gen;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Indication flags for rising and falling spi_clk_q.
+  -- Essential for MMC clock compatibility mode.
+  -----------------------------------------------------------------------------
+  mmc_comap: if mmc_compat_clk_div_g > 0 generate
+    mmc_compat_sig: process (clk_i, reset_s)
+    begin
+      if reset_s then
+        spi_clk_rising_q  <= false;
+        spi_clk_falling_q <= false;
+
+      elsif clk_i'event and clk_i = '1' then
+        if mmc_compat_s then
+          -- MMC clock compatibility mode:
+          -- spi_clk_rising_q is an impulse right before rising edge of spi_clk_q
+          -- spi_clk_falling_q is an impulse right before falling edge of spi_clk_q
+          if mmc_cnt_ovfl_s then
+            spi_clk_rising_q  <= spi_clk_q = '0';
+            spi_clk_falling_q <= spi_clk_q = '1';
+          else
+            spi_clk_rising_q  <= false;
+            spi_clk_falling_q <= false;
+          end if;
+        else
+          -- normal mode
+          spi_clk_rising_q  <= not spi_clk_rising_q;
+          spi_clk_falling_q <= true;
+        end if;
+
+      end if;
+    end process mmc_compat_sig;
+  end generate;
+
+  no_mmc_compat: if mmc_compat_clk_div_g = 0 generate
+    -- SPI clock rising whenever spi_clk_q is '0'
+    spi_clk_rising_q  <= spi_clk_q = '0';
+    -- SPI clock falling whenever spi_clk_q is '1'
+    spi_clk_falling_q <= spi_clk_q = '1';
+  end generate;
+
+
+  -----------------------------------------------------------------------------
+  -- Process ctrl_fsm
+  --
+  -- Purpose:
+  --   Implements the controller FSM.
+  --
+  ctrl_fsm: process (ctrl_fsm_q,
+                     cmd_finished_s, r1_result_q,
+                     start_i, start_q, mode_i,
+                     cfg_init_n_i)
+
+    variable mmc_compat_v : boolean;
+
+  begin
+    -- default assignments
+    ctrl_fsm_s   <= POWER_UP1;
+    config_n_o   <= '1';
+    cnt_en_img_s <= false;
+    spi_cs_n_s   <= '0';
+    mmc_compat_v := false;
+    en_outs_s    <= true;
+
+    case ctrl_fsm_q is
+      -- Let card finish power up, step 1 -------------------------------------
+      when POWER_UP1 =>
+        mmc_compat_v := true;
+        spi_cs_n_s   <= '1';
+        if cmd_finished_s then
+          ctrl_fsm_s <= POWER_UP2;
+        else
+          ctrl_fsm_s <= POWER_UP1;
+        end if;
+
+
+      -- Let card finish power up, step 2 -------------------------------------
+      when POWER_UP2 =>
+        mmc_compat_v := true;
+        if cmd_finished_s then
+          ctrl_fsm_s <= CMD0;
+        else
+          spi_cs_n_s <= '1';
+          ctrl_fsm_s <= POWER_UP2;
+        end if;
+
+
+      -- Issue CMD0: GO_IDLE_STATE --------------------------------------------
+      when CMD0 =>
+        mmc_compat_v   := true;
+        if cmd_finished_s then
+          if sd_init_g = 1 then
+            ctrl_fsm_s <= CMD55;
+          else
+            ctrl_fsm_s <= CMD1;
+          end if;
+        else
+          ctrl_fsm_s   <= CMD0;
+        end if;
+
+
+      -- Issue CMD55: APP_CMD -------------------------------------------------
+      when CMD55 =>
+        if sd_init_g = 1 then
+
+          mmc_compat_v   := true;
+          if cmd_finished_s then
+            if r1_result_q = '0' then
+              -- command accepted, it's an SD card
+              ctrl_fsm_s <= ACMD41;
+            else
+              -- command rejected, it's an MMC card
+              ctrl_fsm_s <= CMD1;
+            end if;
+          else
+            ctrl_fsm_s   <= CMD55;
+          end if;
+
+        end if;
+
+
+      -- Issue ACMD41: SEND_OP_COND -------------------------------------------
+      when ACMD41 =>
+        if sd_init_g = 1 then
+
+          mmc_compat_v   := true;
+          if cmd_finished_s then
+            if r1_result_q = '0' then
+              ctrl_fsm_s <= CMD16;
+            else
+              ctrl_fsm_s <= CMD55;
+            end if;
+          else
+            ctrl_fsm_s   <= ACMD41;
+          end if;
+
+        end if;
+
+
+      -- Issue CMD1: SEND_OP_COND ---------------------------------------------
+      when CMD1 =>
+        mmc_compat_v   := true;
+        if cmd_finished_s then
+          if r1_result_q = '0' then
+            ctrl_fsm_s <= CMD16;
+          else
+            ctrl_fsm_s <= CMD1;
+          end if;
+        else
+          ctrl_fsm_s   <= CMD1;
+        end if;
+
+
+      -- Issue CMD16: SET_BLOCKLEN --------------------------------------------
+      when CMD16 =>
+        if cmd_finished_s then
+          ctrl_fsm_s <= WAIT_START;
+        else
+          ctrl_fsm_s <= CMD16;
+        end if;
+
+
+      -- Wait for configuration start request ---------------------------------
+      when WAIT_START =>
+        spi_cs_n_s     <= '1';
+
+        -- detect rising edge of start_i
+        if start_i = '1' and start_q = '0' then
+          -- decide which mode is requested
+          if cmd_finished_s then
+            if mode_i = '0' then
+              ctrl_fsm_s <= CMD18;
+            else
+              ctrl_fsm_s <= WAIT_INIT_LOW;
+            end if;
+          else
+            en_outs_s    <= false;
+            ctrl_fsm_s   <= WAIT_START;
+          end if;
+        else
+          en_outs_s      <= false;
+          ctrl_fsm_s     <= WAIT_START;
+        end if;
+
+
+      -- Wait for INIT to become low ------------------------------------------
+      when WAIT_INIT_LOW =>
+        spi_cs_n_s   <= '1';
+        -- activate FPGA configuration
+        config_n_o   <= '0';
+
+        if cfg_init_n_i = '0' then
+          ctrl_fsm_s <= WAIT_INIT_HIGH;
+        else
+          ctrl_fsm_s <= WAIT_INIT_LOW;
+        end if;
+
+
+      -- Wait for INIT to become high -----------------------------------------
+      when WAIT_INIT_HIGH =>
+        spi_cs_n_s   <= '1';
+
+        if cfg_init_n_i = '1' and cmd_finished_s then
+          ctrl_fsm_s <= CMD18;
+        else
+          ctrl_fsm_s <= WAIT_INIT_HIGH;
+        end if;
+
+
+      -- Issue CMD18: READ_MULTIPLE_BLOCKS ------------------------------------
+      when CMD18 =>
+        if cmd_finished_s then
+          ctrl_fsm_s <= CMD18_DATA;
+        else
+          ctrl_fsm_s <= CMD18;
+        end if;
+      --
+      -- receive a data block
+      when CMD18_DATA =>
+        if cmd_finished_s then
+          ctrl_fsm_s   <= CMD12;
+        else
+          ctrl_fsm_s   <= CMD18_DATA;
+        end if;
+
+
+       -- Issued CMD12: STOP_TRANSMISSION --------------------------------------
+       when CMD12 =>
+         if cmd_finished_s then
+           ctrl_fsm_s <= INC_IMG_CNT;
+         else
+           ctrl_fsm_s <= CMD12;
+         end if;
+
+
+      -- Increment Image Counter ----------------------------------------------
+      when INC_IMG_CNT =>
+        spi_cs_n_s   <= '1';
+        ctrl_fsm_s   <= WAIT_START;
+        cnt_en_img_s <= true;
+
+
+
+      when others =>
+        null;
+
+    end case;
+
+    -- mmc_compat_s is suppressed if MMC clock compatibility is not required
+    if mmc_compat_clk_div_g > 0 then
+      mmc_compat_s <= mmc_compat_v;
+    else
+      mmc_compat_s <= false;
+    end if;
+
+  end process ctrl_fsm;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Process cmd_fsm
+  --
+  -- Purpose:
+  --   Implements the command FSM.
+  --
+  cmd_fsm: process (spi_clk_rising_q,
+                    spi_data_in_i,
+                    bit_cnt_q,
+                    ctrl_fsm_q,
+                    cmd_fsm_q,
+                    send_cmd12_q)
+
+    variable cnt_zero_v     : boolean;
+    variable spi_data_low_v : boolean;
+    variable no_startbit_v  : boolean;
+
+  begin
+    -- default assignments
+    cmd_finished_s <= false;
+    cmd_fsm_s      <= CMD;
+    res_bc_s       <= NONE;
+
+    cnt_zero_v     := spi_clk_rising_q and bit_cnt_q = 0;
+    spi_data_low_v := spi_clk_rising_q and spi_data_in_i = '0';
+
+    -- these are no real commands thus there will be no startbit
+    case ctrl_fsm_q is
+      when POWER_UP1  | POWER_UP2 |
+           WAIT_START | WAIT_INIT_HIGH | WAIT_INIT_LOW =>
+        no_startbit_v := true;
+      when others =>
+        no_startbit_v := false;
+    end case;
+
+
+    case cmd_fsm_q is
+      -- Send the command -----------------------------------------------------
+      when CMD =>
+        if cnt_zero_v then
+          if ctrl_fsm_q /= CMD18_DATA then
+            -- normal commands including CMD12 require startbit of R1 response
+            cmd_fsm_s <= START;
+          else
+            if not send_cmd12_q then
+              -- CMD18_DATA needs to read CRC
+              cmd_fsm_s <= R1;
+              res_bc_s <= RES_15;
+            else
+              -- CMD18_DATA finished, scan for startbit of response
+              cmd_finished_s <= true;
+              cmd_fsm_s      <= START;
+            end if;
+          end if;
+        else
+          cmd_fsm_s <= CMD;
+        end if;
+
+      -- Wait for startbit of response ----------------------------------------
+      when START =>
+        -- startbit detection or skip of this check
+        if no_startbit_v and spi_clk_rising_q then
+          cmd_fsm_s   <= R1;
+          res_bc_s    <= RES_7;
+        elsif spi_data_low_v then
+          if ctrl_fsm_q /= CMD18_DATA then
+            cmd_fsm_s <= R1;
+          else
+            -- CMD18_DATA startbit detected, read payload
+            cmd_fsm_s <= CMD;
+            res_bc_s  <= RES_MAX;
+          end if;
+        else
+          cmd_fsm_s   <= START;
+          res_bc_s    <= RES_7;
+        end if;
+
+      -- Read R1 response -----------------------------------------------------
+      when R1 =>
+        if cnt_zero_v then
+          res_bc_s  <= RES_7;
+
+          if not (ctrl_fsm_q = CMD18 or ctrl_fsm_q = CMD18_DATA) then
+            cmd_fsm_s        <= PAUSE;
+          else
+            -- CMD18 needs another startbit detection for the data token.
+            -- CMD18_DATA needs a startbit after having received the CRC, either
+            --   * next data token
+            --   * R1 response of CMD12
+            cmd_fsm_s        <= START;
+
+            if ctrl_fsm_q = CMD18 then
+              -- CMD18 response received -> advance to CMD18_DATA
+              cmd_finished_s <= true;
+            end if;
+          end if;
+        else
+          cmd_fsm_s <= R1;
+        end if;
+
+      -- PAUSE state -> required for Nrc, card response to host command -------
+      when PAUSE =>
+        if cnt_zero_v then
+          cmd_fsm_s <= CMD;
+          res_bc_s  <= RES_47;
+          cmd_finished_s <= true;
+        else
+          cmd_fsm_s <= PAUSE;
+        end if;
+
+      when others =>
+        null;
+
+    end case;
+
+  end process cmd_fsm;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Process transmit
+  --
+  -- Purpose:
+  --   Generates the serial data output values based on the current FSM state
+  --
+  --   The local variable cmd_v is 64 bits wide in contrast to an SPI command
+  --   with 48 bits. There are two reasons for this:
+  --   * During "overlaid" sending of CMD12 in FSM state CMD18_DATA, the bit
+  --     counter will start from 3F on its lowest 6 bits. Therefore, it is
+  --     necessary to provide all 64 positions in cmd_v.
+  --   * Reduces logic.
+  --
+  transmit: process (ctrl_fsm_q,
+                     cmd_fsm_q,
+                     bit_cnt_q,
+                     img_cnt_s,
+                     send_cmd12_q,
+                     set_sel_i,
+                     upper_bitcnt_zero_s)
+
+    subtype cmd_r is natural range 47 downto 0;
+    subtype cmd_t is std_logic_vector(cmd_r);
+    subtype ext_cmd_t is std_logic_vector(63 downto 0);
+    --                            STCCCCCCAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAcccccccS
+    constant cmd0_c   : cmd_t := "010000000000000000000000000000000000000010010101";
+    constant cmd1_c   : cmd_t := "0100000100000000000000000000000000000000-------1";
+    constant cmd12_c  : cmd_t := "0100110000000000000000000000000000000000-------1";
+    constant cmd16_c  : cmd_t := "0101000000000000000000000000000000000000-------1";
+    constant cmd18_c  : cmd_t := "0101001000000000000000000000000000000000-------1";
+    constant cmd55_c  : cmd_t := "0111011100000000000000000000000000000000-------1";
+    constant acmd41_c : cmd_t := "0110100100000000000000000000000000000000-------1";
+
+    variable cmd_v      : ext_cmd_t;
+    variable tx_v       : boolean;
+
+  begin
+    -- default assignments
+    spi_dat_s    <= '1';
+    cmd_v        := (others => '1');
+    tx_v         := false;
+
+    if cmd_fsm_q = CMD then
+      case ctrl_fsm_q is
+        when CMD0 =>
+          cmd_v(cmd_r) := cmd0_c;
+          tx_v := true;
+        when CMD1 =>
+          cmd_v(cmd_r) := cmd1_c;
+          tx_v := true;
+        when CMD16 =>
+          cmd_v(cmd_r) := cmd16_c;
+          cmd_v(8 + width_bit_cnt_g-3) := '1';
+          tx_v := true;
+        when CMD18 =>
+          cmd_v(cmd_r) := cmd18_c;
+          -- insert image counter
+          cmd_v(8 + num_bits_per_img_g + width_img_cnt_g
+                downto 8 + num_bits_per_img_g) := img_cnt_s;
+          -- insert set selection
+          cmd_v(8 + num_bits_per_img_g + width_img_cnt_g + width_set_sel_g-1
+                downto 8 + num_bits_per_img_g + width_img_cnt_g) := set_sel_i;
+          tx_v := true;
+        when CMD18_DATA =>
+          cmd_v(cmd_r) := cmd12_c;
+
+          if send_cmd12_q and upper_bitcnt_zero_s then
+            tx_v := true;
+          end if;
+        when CMD55 =>
+          cmd_v(cmd_r) := cmd55_c;
+          tx_v := true;
+        when ACMD41 =>
+          cmd_v(cmd_r) := acmd41_c;
+          tx_v := true;
+
+        when others =>
+          null;
+      end case;
+    end if;
+
+    if tx_v then
+      spi_dat_s <= cmd_v(to_integer(bit_cnt_q(5 downto 0)));
+    end if;
+
+  end process transmit;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Optional Image Counter
+  -----------------------------------------------------------------------------
+  img_cnt: if width_img_cnt_g > 0 generate
+    img_cnt_b : spi_counter
+      generic map (
+        cnt_width_g   => width_img_cnt_g,
+        cnt_max_g     => 2**width_img_cnt_g - 1
+      )
+      port map (
+        clk_i         => clk_i,
+        reset_i       => reset_s,
+        cnt_en_i      => cnt_en_img_s,
+        cnt_o         => img_cnt_s(width_img_cnt_g-1 downto 0),
+        cnt_ovfl_o    => open
+      );
+    img_cnt_s(width_img_cnt_g) <= '0';
+  end generate;
+
+  no_img_cnt: if width_img_cnt_g = 0 generate
+    img_cnt_s <= (others => '0');
+  end generate;
+
+
+  -----------------------------------------------------------------------------
+  -- Optional MMC compatibility counter
+  -----------------------------------------------------------------------------
+  mmc_cnt: if mmc_compat_clk_div_g > 0 generate
+    mmc_cnt_b : spi_counter
+      generic map (
+        cnt_width_g   => width_mmc_clk_div_g,
+        cnt_max_g     => mmc_compat_clk_div_g
+      )
+      port map (
+        clk_i         => clk_i,
+        reset_i       => reset_s,
+        cnt_en_i      => true_s,
+        cnt_o         => open,
+        cnt_ovfl_o    => mmc_cnt_ovfl_s
+      );
+  end generate;
+
+  no_mmc_cnt: if mmc_compat_clk_div_g = 0 generate
+    mmc_cnt_ovfl_s <= true;
+  end generate;
+
+
+  -----------------------------------------------------------------------------
+  -- Output Mapping
+  -----------------------------------------------------------------------------
+  spi_clk_o      <=   spi_clk_q;
+  spi_cs_n_o     <=   spi_cs_n_q;
+  spi_data_out_o <=   spi_dat_q;
+  spi_en_outs_o  <=   '1'
+                    when en_outs_q else
+                      '0';
+  cfg_clk_o      <= cfg_clk_q;
+  cfg_dat_o      <= cfg_dat_q;
+  detached_o     <=   '0'
+                    when en_outs_q else
+                      '1';
+
+end rtl;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: spi_boot.vhd,v $
+-- Revision 1.9  2007/02/25 18:24:12  arniml
+-- fix type handling of resets
+--
+-- Revision 1.8  2006/09/11 23:03:36  arniml
+-- disable outputs with reset
+--
+-- Revision 1.7  2005/04/07 20:44:23  arniml
+-- add new port detached_o
+--
+-- Revision 1.6  2005/03/09 19:48:34  arniml
+-- invert level of set_sel input
+--
+-- Revision 1.5  2005/03/08 22:07:12  arniml
+-- added set selection
+--
+-- Revision 1.4  2005/02/18 06:42:08  arniml
+-- clarify wording for images
+--
+-- Revision 1.3  2005/02/16 18:59:10  arniml
+-- include output enable control for SPI outputs
+--
+-- Revision 1.2  2005/02/13 17:25:51  arniml
+-- major update to fix several problems
+-- configuration/data download of multiple sets works now
+--
+-- Revision 1.1  2005/02/08 20:41:33  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd
new file mode 100644
index 000000000..ac8b544f9
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd
@@ -0,0 +1,54 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: spi_boot_pack-p.vhd,v 1.1 2005/02/08 20:41:33 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package spi_boot_pack is
+
+  function "=" (a : std_logic; b : integer) return boolean;
+
+end spi_boot_pack;
+
+package body spi_boot_pack is
+
+  function "=" (a : std_logic; b : integer) return boolean is
+    variable result_v : boolean;
+  begin
+    result_v := false;
+
+    case a is
+      when '0' =>
+        if b = 0 then
+          result_v := true;
+        end if;
+
+      when '1' =>
+        if b = 1 then
+          result_v := true;
+        end if;
+
+      when others =>
+        null;
+
+    end case;
+
+    return result_v;
+  end;
+
+end spi_boot_pack;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: spi_boot_pack-p.vhd,v $
+-- Revision 1.1  2005/02/08 20:41:33  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd
new file mode 100644
index 000000000..d81e20db6
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd
@@ -0,0 +1,14 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: spi_counter-c.vhd,v 1.1 2005/02/08 20:41:33 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration spi_counter_rtl_c0 of spi_counter is
+
+  for rtl
+  end for;
+
+end spi_counter_rtl_c0;
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter.vhd
new file mode 100644
index 000000000..8ec7357ea
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter.vhd
@@ -0,0 +1,118 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Generic counter module
+--
+-- $Id: spi_counter.vhd,v 1.2 2007/02/25 18:24:12 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity spi_counter is
+
+  generic (
+    cnt_width_g   : integer := 4;
+    cnt_max_g     : integer := 15
+  );
+
+  port (
+    clk_i      : in  std_logic;
+    reset_i    : in  boolean;
+    cnt_en_i   : in  boolean;
+    cnt_o      : out std_logic_vector(cnt_width_g-1 downto 0);
+    cnt_ovfl_o : out boolean
+  );
+
+end spi_counter;
+
+
+library ieee;
+use ieee.numeric_std.all;
+use work.spi_boot_pack.all;
+
+architecture rtl of spi_counter is
+
+  signal cnt_q      : unsigned(cnt_width_g-1 downto 0);
+  signal cnt_ovfl_s : boolean;
+
+begin
+
+  cnt: process (clk_i, reset_i)
+  begin
+    if reset_i then
+      cnt_q <= (others => '0');
+
+    elsif clk_i'event and clk_i = '1' then
+      if cnt_en_i then
+        if not cnt_ovfl_s then
+          cnt_q <= cnt_q + 1;
+        else
+          cnt_q <= (others => '0');
+        end if;
+      end if;
+    end if;
+  end process cnt;
+
+  cnt_ovfl_s <= cnt_q = cnt_max_g;
+
+
+  -----------------------------------------------------------------------------
+  -- Output Mapping
+  -----------------------------------------------------------------------------
+  cnt_ovfl_o <= cnt_ovfl_s;
+  cnt_o      <= std_logic_vector(cnt_q);
+
+end rtl;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: spi_counter.vhd,v $
+-- Revision 1.2  2007/02/25 18:24:12  arniml
+-- fix type handling of resets
+--
+-- Revision 1.1  2005/02/08 20:41:33  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/sim/rtl_sim/Makefile b/fpga/usrp2/opencores/spi_boot/sim/rtl_sim/Makefile
new file mode 100644
index 000000000..46fb3c635
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/sim/rtl_sim/Makefile
@@ -0,0 +1,159 @@
+##############################################################################
+#
+# Makefile for the spi_boot project.
+#
+# The dependencies for all VHDL source files are stored here.
+#
+# Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+#
+# All rights reserved
+#
+##############################################################################
+
+
+PROJECT_DIR = ../..
+RTL_DIR     = $(PROJECT_DIR)/rtl/vhdl
+BENCH_DIR   = $(PROJECT_DIR)/bench/vhdl
+
+
+
+ANALYZE=ghdl -a --std=87 --workdir=work
+ELABORATE=ghdl -e --std=87 --workdir=work
+
+.PHONY: all
+all: work elaborate
+
+work:
+	mkdir work
+
+work/spi_boot_pack-p.o: $(RTL_DIR)/spi_boot_pack-p.vhd
+	$(ANALYZE) $(RTL_DIR)/spi_boot_pack-p.vhd
+
+work/spi_counter.o: $(RTL_DIR)/spi_counter.vhd \
+                    work/spi_boot_pack-p.o
+	$(ANALYZE) $(RTL_DIR)/spi_counter.vhd
+work/spi_counter-c.o: $(RTL_DIR)/spi_counter-c.vhd \
+                      work/spi_counter.o
+	$(ANALYZE) $(RTL_DIR)/spi_counter-c.vhd
+
+work/spi_boot.o: $(RTL_DIR)/spi_boot.vhd \
+                 work/spi_boot_pack-p.o
+	$(ANALYZE) $(RTL_DIR)/spi_boot.vhd
+work/spi_boot-c.o: $(RTL_DIR)/spi_boot-c.vhd \
+                   work/spi_boot.o           \
+                   work/spi_counter-c.o
+	$(ANALYZE) $(RTL_DIR)/spi_boot-c.vhd
+
+work/chip-e.o: $(RTL_DIR)/chip-e.vhd
+	$(ANALYZE) $(RTL_DIR)/chip-e.vhd
+
+work/chip-full-a.o: $(RTL_DIR)/chip-full-a.vhd \
+                    work/chip-e.o
+	$(ANALYZE) $(RTL_DIR)/chip-full-a.vhd
+work/chip-full-c.o: $(RTL_DIR)/chip-full-c.vhd \
+                    work/chip-full-a.o         \
+                    work/spi_boot-c.o
+	$(ANALYZE) $(RTL_DIR)/chip-full-c.vhd
+
+work/chip-mmc-a.o: $(RTL_DIR)/chip-mmc-a.vhd \
+                   work/chip-e.o
+	$(ANALYZE) $(RTL_DIR)/chip-mmc-a.vhd
+work/chip-mmc-c.o: $(RTL_DIR)/chip-mmc-c.vhd \
+                   work/chip-mmc-a.o         \
+                   work/spi_boot-c.o
+	$(ANALYZE) $(RTL_DIR)/chip-mmc-c.vhd
+
+work/chip-sd-a.o: $(RTL_DIR)/chip-sd-a.vhd \
+                  work/chip-e.o
+	$(ANALYZE) $(RTL_DIR)/chip-sd-a.vhd
+work/chip-sd-c.o: $(RTL_DIR)/chip-sd-c.vhd \
+                  work/chip-sd-a.o           \
+                  work/spi_boot-c.o
+	$(ANALYZE) $(RTL_DIR)/chip-sd-c.vhd
+
+work/chip-minimal-a.o: $(RTL_DIR)/chip-minimal-a.vhd \
+                       work/chip-e.o
+	$(ANALYZE) $(RTL_DIR)/chip-minimal-a.vhd
+work/chip-minimal-c.o: $(RTL_DIR)/chip-minimal-c.vhd \
+                       work/chip-minimal-a.o           \
+                       work/spi_boot-c.o
+	$(ANALYZE) $(RTL_DIR)/chip-minimal-c.vhd
+
+work/ram_loader.o: $(RTL_DIR)/sample/ram_loader.vhd
+	$(ANALYZE) $(RTL_DIR)/sample/ram_loader.vhd
+work/ram_loader-c.o: $(RTL_DIR)/sample/ram_loader-c.vhd \
+                     work/ram_loader.o
+	$(ANALYZE) $(RTL_DIR)/sample/ram_loader-c.vhd
+
+work/tb_pack-p.o: $(BENCH_DIR)/tb_pack-p.vhd
+	$(ANALYZE) $(BENCH_DIR)/tb_pack-p.vhd
+
+work/card.o: $(BENCH_DIR)/card.vhd \
+             work/tb_pack-p.o
+	$(ANALYZE) $(BENCH_DIR)/card.vhd
+work/card-c.o: $(BENCH_DIR)/card-c.vhd \
+               work/card.o
+	$(ANALYZE) $(BENCH_DIR)/card-c.vhd
+
+work/tb_elem.o: $(BENCH_DIR)/tb_elem.vhd \
+                work/spi_boot_pack-p.o   \
+                work/tb_pack-p.o
+	$(ANALYZE) $(BENCH_DIR)/tb_elem.vhd
+work/tb_elem-full-c.o: $(BENCH_DIR)/tb_elem-full-c.vhd \
+                       work/tb_elem.o                  \
+                       work/chip-full-c.o              \
+                       work/card-c.o
+	$(ANALYZE) $(BENCH_DIR)/tb_elem-full-c.vhd
+work/tb_elem-mmc-c.o: $(BENCH_DIR)/tb_elem-mmc-c.vhd \
+                      work/tb_elem.o                 \
+                      work/chip-mmc-c.o              \
+                      work/card-c.o
+	$(ANALYZE) $(BENCH_DIR)/tb_elem-mmc-c.vhd
+work/tb_elem-sd-c.o: $(BENCH_DIR)/tb_elem-sd-c.vhd \
+                     work/tb_elem.o                \
+                     work/chip-sd-c.o              \
+                     work/card-c.o
+	$(ANALYZE) $(BENCH_DIR)/tb_elem-sd-c.vhd
+work/tb_elem-minimal-c.o: $(BENCH_DIR)/tb_elem-minimal-c.vhd \
+                          work/tb_elem.o                     \
+                          work/chip-minimal-c.o              \
+                          work/card-c.o
+	$(ANALYZE) $(BENCH_DIR)/tb_elem-minimal-c.vhd
+
+work/tb.o: $(BENCH_DIR)/tb.vhd
+	$(ANALYZE) $(BENCH_DIR)/tb.vhd
+work/tb-c.o: $(BENCH_DIR)/tb-c.vhd    \
+             work/tb.o                \
+             work/tb_elem-full-c.o    \
+             work/tb_elem-mmc-c.o     \
+             work/tb_elem-sd-c.o      \
+             work/tb_elem-minimal-c.o
+	$(ANALYZE) $(BENCH_DIR)/tb-c.vhd
+
+work/tb_rl.o: $(BENCH_DIR)/tb_rl.vhd
+	$(ANALYZE) $(BENCH_DIR)/tb_rl.vhd
+work/tb_rl-c.o: $(BENCH_DIR)/tb_rl-c.vhd \
+                work/tb_rl.o             \
+                work/chip-full-c.o       \
+                work/card-c.o            \
+                work/ram_loader-c.o
+	$(ANALYZE) $(BENCH_DIR)/tb_rl-c.vhd
+
+
+.PHONY: elaborate
+elaborate: tb_behav_c0 tb_rl_behav_c0
+
+tb_behav_c0: work/tb-c.o
+	$(ELABORATE) tb_behav_c0; \
+	strip tb_behav_c0
+
+tb_rl_behav_c0: work/tb_rl-c.o
+	$(ELABORATE) tb_rl_behav_c0; \
+	strip tb_rl_behav_c0
+
+.PHONY: analyze
+analyze: work/tb-c.o work/tb_rl-c.o
+
+.PHONY: clean
+clean:
+	rm -rf work tb_behav_c0 tb_rl_behav_c0 *~
diff --git a/fpga/usrp2/opencores/spi_boot/sw/misc/bit_reverse.c b/fpga/usrp2/opencores/spi_boot/sw/misc/bit_reverse.c
new file mode 100644
index 000000000..9defb106a
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/sw/misc/bit_reverse.c
@@ -0,0 +1,74 @@
+// Altera requires configuration bytes to be sent LSB first but the
+// SD Card reads bytes MSB first
+// This code reverses the bits of the altera bitstream so
+// it will come out correct when read from the SD card
+// $Log: bit_reverse.c,v $
+// Revision 1.1  2006/01/06 14:44:17  mbl
+// initial version
+//
+
+
+
+#include "stdio.h"
+#include "string.h"
+
+FILE*   fileOut;
+FILE*   fileIn;
+
+void    outIOerror(char* pfn);
+void    inIOerror(char* pfn);
+
+int main(int argc, char* arg[])
+{
+	unsigned char input, output;
+	unsigned char in_mask, out_mask;
+	int i;
+
+	fileOut = fopen(arg[2],"wb");
+	if (fileOut == NULL)
+	{
+	    outIOerror(arg[2]);
+	    exit(-1);
+	}
+
+	printf("Opening input file %s\n", arg[1]);
+        fileIn = fopen(arg[1],"rb");
+        if (fileIn == NULL)
+        {
+            inIOerror(arg[1]);
+            exit(-1);
+        }
+
+        while (!feof(fileIn) && fgets((char*)&input, 2 ,fileIn) != NULL)
+        {
+    	    in_mask = 1;
+    	    out_mask = 0x80;
+	    output = 0;
+
+    	    for ( i=0; i < 8; ++i )
+     	    {
+       		if (input & in_mask) 
+       		{
+        	    output |= out_mask;
+       		}
+       		out_mask = out_mask >> 1;
+       		in_mask = in_mask << 1;
+     	    }
+	    fwrite((void*)&output,sizeof(char),1,fileOut);
+	}
+
+	fclose(fileIn);
+	fclose(fileOut);
+	printf("\n%s has been created\n", arg[2]);
+	exit(0);
+}
+
+void outIOerror(char *pfn)
+{
+	printf("I/O Error while writing to file=%s\n",pfn);
+}
+
+void inIOerror(char *pfn)
+{
+	printf("I/O Error while reading file=%s\n",pfn);
+}