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-rwxr-xr-xfpga/usrp2/opencores/aemb/sim/cversim22
1 files changed, 0 insertions, 22 deletions
diff --git a/fpga/usrp2/opencores/aemb/sim/cversim b/fpga/usrp2/opencores/aemb/sim/cversim
deleted file mode 100755
index 0dbb7aea1..000000000
--- a/fpga/usrp2/opencores/aemb/sim/cversim
+++ /dev/null
@@ -1,22 +0,0 @@
-#!/bin/sh
-# $Id: cversim,v 1.5 2007/12/11 00:44:30 sybreon Exp $
-# $Log: cversim,v $
-# Revision 1.5 2007/12/11 00:44:30 sybreon
-# Modified for AEMB2
-#
-# Revision 1.4 2007/11/30 17:08:30 sybreon
-# Moved simulation kernel into code.
-#
-# Revision 1.3 2007/11/05 10:59:31 sybreon
-# Added random seed for simulation.
-#
-# Revision 1.2 2007/04/12 20:21:33 sybreon
-# Moved testbench into /sim/verilog.
-# Simulation cleanups.
-#
-# Revision 1.1 2007/03/09 17:41:55 sybreon
-# initial import
-#
-RANDOM=$(date +%s)
-echo "parameter randseed = $RANDOM;" > random.v
-cver -q -w +define+AEMBX_SIMULATION_KERNEL $@ ../rtl/verilog/*.v