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-rw-r--r--fpga/usrp2/boot_cpld/.gitignore38
-rwxr-xr-xfpga/usrp2/boot_cpld/_impact.cmd34
-rwxr-xr-xfpga/usrp2/boot_cpld/boot_cpld.ipfbin2967 -> 0 bytes
-rwxr-xr-xfpga/usrp2/boot_cpld/boot_cpld.isebin227573 -> 0 bytes
-rwxr-xr-xfpga/usrp2/boot_cpld/boot_cpld.lfp5
-rwxr-xr-xfpga/usrp2/boot_cpld/boot_cpld.ucf34
-rwxr-xr-xfpga/usrp2/boot_cpld/boot_cpld.v95
7 files changed, 0 insertions, 206 deletions
diff --git a/fpga/usrp2/boot_cpld/.gitignore b/fpga/usrp2/boot_cpld/.gitignore
deleted file mode 100644
index 45cf9a86b..000000000
--- a/fpga/usrp2/boot_cpld/.gitignore
+++ /dev/null
@@ -1,38 +0,0 @@
-/*_xdb
-/*.restore
-/*.xrpt
-/*.zip
-/xst
-/_ngo
-/_xmsgs
-/*.log
-/*.stx
-/*.tspec
-/*.xml
-/*.gyd
-/*.ngr
-/*.tim
-/*.err
-/*.lso
-/*.bld
-/*.cmd_log
-/*.ise_ISE_Backup
-/*.ipf_ISE_Backup
-/*.mfd
-/*.vm6
-/*.syr
-/*.xst
-/*.csv
-/*.html
-/*.jed
-/*.pad
-/*.ng*
-/*.pnx
-/*.rpt
-/*.prj
-/*_html
-/*.cel
-/_pace.ucf
-/*.lock
-/*.tfi
-/templates
diff --git a/fpga/usrp2/boot_cpld/_impact.cmd b/fpga/usrp2/boot_cpld/_impact.cmd
deleted file mode 100755
index 4af86cb02..000000000
--- a/fpga/usrp2/boot_cpld/_impact.cmd
+++ /dev/null
@@ -1,34 +0,0 @@
-loadProjectFile -file "C:\cygwin\home\matt\usrp2\fpga\boot_cpld/boot_cpld.ipf"
-setMode -ss
-setMode -sm
-setMode -hw140
-setMode -spi
-setMode -acecf
-setMode -acempm
-setMode -pff
-setMode -bs
-setMode -bs
-setMode -bs
-setMode -bs
-setCable -port auto
-Identify
-identifyMPM
-assignFile -p 1 -file "C:/cygwin/home/matt/usrp2/fpga/boot_cpld/boot_cpld.jed"
-Program -p 1 -e -v -defaultVersion 0
-Program -p 1 -e -v -defaultVersion 0
-Program -p 1 -e -v -defaultVersion 0
-Program -p 1 -e -v -defaultVersion 0
-Program -p 1 -e -v -defaultVersion 0
-Program -p 1 -e -v -defaultVersion 0
-Identify
-identifyMPM
-Identify
-identifyMPM
-Identify
-identifyMPM
-Identify
-identifyMPM
-Identify
-identifyMPM
-setMode -bs
-deleteDevice -position 1
diff --git a/fpga/usrp2/boot_cpld/boot_cpld.ipf b/fpga/usrp2/boot_cpld/boot_cpld.ipf
deleted file mode 100755
index 8acb6821e..000000000
--- a/fpga/usrp2/boot_cpld/boot_cpld.ipf
+++ /dev/null
Binary files differ
diff --git a/fpga/usrp2/boot_cpld/boot_cpld.ise b/fpga/usrp2/boot_cpld/boot_cpld.ise
deleted file mode 100755
index 7252d3768..000000000
--- a/fpga/usrp2/boot_cpld/boot_cpld.ise
+++ /dev/null
Binary files differ
diff --git a/fpga/usrp2/boot_cpld/boot_cpld.lfp b/fpga/usrp2/boot_cpld/boot_cpld.lfp
deleted file mode 100755
index 0f0c8f2e2..000000000
--- a/fpga/usrp2/boot_cpld/boot_cpld.lfp
+++ /dev/null
@@ -1,5 +0,0 @@
-# begin LFP file C:\cygwin\home\matt\u2f\boot_cpld\boot_cpld.lfp
-designfile boot_cpld.v
-parttype xc9572xl-vq44-10
-bus_delimiter 0;
-set_busdelim_onsave 1;
diff --git a/fpga/usrp2/boot_cpld/boot_cpld.ucf b/fpga/usrp2/boot_cpld/boot_cpld.ucf
deleted file mode 100755
index 789bb1d96..000000000
--- a/fpga/usrp2/boot_cpld/boot_cpld.ucf
+++ /dev/null
@@ -1,34 +0,0 @@
-NET "CLK_25MHZ" LOC = "P5" ;
-NET "CLK_25MHZ_EN" LOC = "P6" ;
-NET "LED<0>" LOC = "P12" ;
-NET "LED<1>" LOC = "P8" ;
-NET "LED<2>" LOC = "P7" ;
-NET "DEBUG<0>" LOC = "P1" ;
-NET "DEBUG<1>" LOC = "P2" ;
-NET "DEBUG<2>" LOC = "P3" ;
-NET "DEBUG<3>" LOC = "P29" ;
-NET "DEBUG<4>" LOC = "P30" ;
-NET "DEBUG<5>" LOC = "P31" ;
-NET "DEBUG<6>" LOC = "P32" ;
-NET "DEBUG<7>" LOC = "P33" ;
-NET "DEBUG<8>" LOC = "P34" ;
-NET "POR" LOC = "P42" ;
-NET "SD_nCS" LOC = "P20" ;
-NET "SD_Din" LOC = "P21" ;
-NET "SD_CLK" LOC = "P22" ;
-NET "SD_Dout" LOC = "P23" ;
-NET "SD_DAT1" LOC = "P27" ;
-NET "SD_DAT2" LOC = "P28" ;
-NET "SD_prot" LOC = "P19" ;
-NET "SD_det" LOC = "P36" ;
-NET "CFG_INIT_B" LOC = "P38" ;
-NET "CFG_Din" LOC = "P37" ;
-NET "CFG_CCLK" LOC = "P41" ;
-NET "CFG_DONE" LOC = "P40" ;
-NET "CFG_PROG_B" LOC = "P39" ;
-NET "CPLD_CLK" LOC = "P13" ;
-NET "START" LOC = "P14" ;
-NET "MODE" LOC = "P18" ;
-NET "DONE" LOC = "P16" ;
-NET "detached" LOC = "P43" ;
-NET "CPLD_misc" LOC = "P44" ;
diff --git a/fpga/usrp2/boot_cpld/boot_cpld.v b/fpga/usrp2/boot_cpld/boot_cpld.v
deleted file mode 100755
index 2ffc6daed..000000000
--- a/fpga/usrp2/boot_cpld/boot_cpld.v
+++ /dev/null
@@ -1,95 +0,0 @@
-`timescale 1ns / 1ps
-// ////////////////////////////////////////////////////////////////////////////////
-// Boot CPLD design, only for u2_rev2
-// ////////////////////////////////////////////////////////////////////////////////
-
-module boot_cpld
- (input CLK_25MHZ,
- output CLK_25MHZ_EN,
- output [2:0] LED,
- output [8:0] DEBUG,
- input POR,
-
- // To SD Card
- output SD_nCS,
- output SD_Din,
- output SD_CLK,
- input SD_Dout,
- input SD_DAT1, // Unused
- input SD_DAT2, // Unused
- input SD_prot, // Write Protect
- input SD_det, // Card Detect
-
- // To FPGA Config Interface
- input CFG_INIT_B,
- output CFG_Din, // Also used in Data interface
- output CFG_CCLK,
- input CFG_DONE,
- output CFG_PROG_B,
-
- // To FPGA data interface
- output CPLD_CLK,
- input START,
- input MODE,
- input DONE,
- output detached,
- input CPLD_misc // Unused for now
- );
-
- assign CLK_25MHZ_EN = 1'b1;
-
- assign LED[0] = ~CFG_DONE;
- assign LED[1] = CFG_INIT_B;
- assign LED[2] = ~CFG_PROG_B;
-
- wire en_outs;
- wire [3:0] set_sel = 4'd0;
-
- assign CPLD_CLK = CFG_CCLK;
- assign DEBUG[8:0] = { CLK_25MHZ, SD_nCS, SD_CLK, SD_Din, SD_Dout,
- START, MODE, DONE, CPLD_misc};
-
- // Handle cutover to FPGA control of SD
- wire fpga_takeover = ~CPLD_misc;
- wire SD_CLK_int, SD_nCS_int, SD_Din_int, CFG_Din_int;
-
- assign SD_CLK = fpga_takeover ? START : SD_CLK_int;
- assign SD_nCS = fpga_takeover ? MODE : SD_nCS_int;
- assign SD_Din = fpga_takeover ? DONE : SD_Din_int;
- assign CFG_Din = fpga_takeover ? SD_Dout : CFG_Din_int;
-
- spi_boot #(.width_set_sel_g(4), // How many sets (16)
- .width_bit_cnt_g(6), // Block length (12 is faster, 6 is minimum)
- .width_img_cnt_g(2), // How many images per set
- .num_bits_per_img_g(20), // Image size, 20 = 1MB
- .sd_init_g(1), // SD-specific initialization
- .mmc_compat_clk_div_g(0),// No MMC support
- .width_mmc_clk_div_g(0), // No MMC support
- .reset_level_g(0)) // Active low reset
-
- spi_boot(.clk_i(CLK_25MHZ),
- .reset_i(POR),
-
- // To SD Card
- .spi_clk_o(SD_CLK_int),
- .spi_cs_n_o(SD_nCS_int),
- .spi_data_in_i(SD_Dout),
- .spi_data_out_o(SD_Din_int),
- .spi_en_outs_o(en_outs),
-
- // Data Port
- .start_i(START),
- .mode_i(MODE), // 0->conf mode, 1->data mode
- .detached_o(detached),
- .dat_done_i(DONE),
- .set_sel_i(set_sel),
-
- // To FPGA
- .config_n_o(CFG_PROG_B),
- .cfg_init_n_i(CFG_INIT_B),
- .cfg_done_i(CFG_DONE),
- .cfg_clk_o(CFG_CCLK),
- .cfg_dat_o(CFG_Din_int)
- );
-
-endmodule // boot_cpld
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 08:35:15 +0000