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-rw-r--r--eth/bench/verilog/miim_model.v14
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diff --git a/eth/bench/verilog/miim_model.v b/eth/bench/verilog/miim_model.v
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--- a/eth/bench/verilog/miim_model.v
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-
-// Skeleton PHY interface simulator
-
-module miim_model(input mdc_i,
- inout mdio,
- input phy_resetn_i,
- input phy_clk_i,
- output phy_intn_o,
- output [2:0] speed_o);
-
- assign phy_intn_o = 1; // No interrupts
- assign speed_o = 3'b100; // 1G mode
-
-endmodule // miim_model