diff options
Diffstat (limited to 'coregen/fifo_xlnx_512x36_2clk.xco')
-rw-r--r-- | coregen/fifo_xlnx_512x36_2clk.xco | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/coregen/fifo_xlnx_512x36_2clk.xco b/coregen/fifo_xlnx_512x36_2clk.xco index c67e7e89f..5934ef285 100644 --- a/coregen/fifo_xlnx_512x36_2clk.xco +++ b/coregen/fifo_xlnx_512x36_2clk.xco @@ -1,7 +1,7 @@ ############################################################## # -# Xilinx Core Generator version K.31 -# Date: Mon Jul 28 22:47:43 2008 +# Xilinx Core Generator version K.39 +# Date: Thu Sep 3 17:24:24 2009 # ############################################################## # @@ -14,13 +14,13 @@ # # BEGIN Project Options SET addpads = False -SET asysymbol = True +SET asysymbol = False SET busformat = BusFormatAngleBracketNotRipped SET createndf = False -SET designentry = VHDL +SET designentry = Verilog SET device = xc3s2000 SET devicefamily = spartan3 -SET flowvendor = Foundation_iSE +SET flowvendor = Other SET formalverification = False SET foundationsym = False SET implementationfiletype = Ngc @@ -29,7 +29,7 @@ SET removerpms = False SET simulationfiles = Behavioral SET speedgrade = -5 SET verilogsim = True -SET vhdlsim = True +SET vhdlsim = False # END Project Options # BEGIN Select SELECT Fifo_Generator family Xilinx,_Inc. 4.3 @@ -39,7 +39,7 @@ CSET almost_empty_flag=false CSET almost_full_flag=false CSET component_name=fifo_xlnx_512x36_2clk CSET data_count=false -CSET data_count_width=9 +CSET data_count_width=10 CSET disable_timing_violations=false CSET dout_reset_value=0 CSET empty_threshold_assert_value=4 @@ -61,22 +61,22 @@ CSET programmable_empty_type=No_Programmable_Empty_Threshold CSET programmable_full_type=No_Programmable_Full_Threshold CSET read_clock_frequency=1 CSET read_data_count=true -CSET read_data_count_width=9 +CSET read_data_count_width=10 CSET reset_pin=true CSET reset_type=Asynchronous_Reset CSET underflow_flag=false CSET underflow_sense=Active_High -CSET use_dout_reset=false +CSET use_dout_reset=true CSET use_embedded_registers=false -CSET use_extra_logic=false +CSET use_extra_logic=true CSET valid_flag=false CSET valid_sense=Active_High CSET write_acknowledge_flag=false CSET write_acknowledge_sense=Active_High CSET write_clock_frequency=1 CSET write_data_count=true -CSET write_data_count_width=9 +CSET write_data_count_width=10 # END Parameters GENERATE -# CRC: 43b7cba0 +# CRC: b7f2a9ba |