diff options
Diffstat (limited to 'coregen/fifo_xlnx_512x36_2clk.vho')
| -rw-r--r-- | coregen/fifo_xlnx_512x36_2clk.vho | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/coregen/fifo_xlnx_512x36_2clk.vho b/coregen/fifo_xlnx_512x36_2clk.vho new file mode 100644 index 000000000..70eac27a5 --- /dev/null +++ b/coregen/fifo_xlnx_512x36_2clk.vho @@ -0,0 +1,76 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +component fifo_xlnx_512x36_2clk + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(8 downto 0); + wr_data_count: OUT std_logic_VECTOR(8 downto 0)); +end component; + +-- Synplicity black box declaration +attribute syn_black_box : boolean; +attribute syn_black_box of fifo_xlnx_512x36_2clk: component is true; + +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : fifo_xlnx_512x36_2clk + port map ( + din => din, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + wr_clk => wr_clk, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full, + rd_data_count => rd_data_count, + wr_data_count => wr_data_count); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file fifo_xlnx_512x36_2clk.vhd when simulating +-- the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + |