diff options
| m--------- | fpga-src | 0 | ||||
| -rw-r--r-- | host/lib/usrp/cores/rx_frontend_core_3000.cpp | 18 | ||||
| -rw-r--r-- | host/lib/usrp/x300/x300_fw_common.h | 2 | ||||
| -rw-r--r-- | images/manifest.txt | 4 |
4 files changed, 10 insertions, 14 deletions
diff --git a/fpga-src b/fpga-src -Subproject 3de8954aa6c49aede0ddcf2d21c7844c01f5663 +Subproject f1ba32fe71856b9201696bfc2730daf0152da96 diff --git a/host/lib/usrp/cores/rx_frontend_core_3000.cpp b/host/lib/usrp/cores/rx_frontend_core_3000.cpp index 15c65ad03..214eefb73 100644 --- a/host/lib/usrp/cores/rx_frontend_core_3000.cpp +++ b/host/lib/usrp/cores/rx_frontend_core_3000.cpp @@ -1,13 +1,12 @@ // // Copyright 2011-2012,2014-2016 Ettus Research LLC -// Copyright 2017-2018 Ettus Research, a National Instruments Company +// Copyright 2018 Ettus Research, a National Instruments Company // // SPDX-License-Identifier: GPL-3.0-or-later // #include <uhd/types/dict.hpp> #include <uhd/types/ranges.hpp> -#include <uhd/utils/math.hpp> #include <uhdlib/usrp/cores/rx_frontend_core_3000.hpp> #include <uhdlib/usrp/cores/dsp_core_utils.hpp> #include <boost/math/special_functions/round.hpp> @@ -99,10 +98,11 @@ public: _iface->poke32(REG_RX_FE_MAPPING, mapping_reg_val); UHD_ASSERT_THROW(_adc_rate!=0.0) + double cordic_freq = 0.0, actual_cordic_freq = 0.0; if (fe_conn.get_sampling_mode() == fe_connection_t::HETERODYNE) { //1. Remember the sign of the IF frequency. // It will be discarded in the next step - const int if_freq_sign = boost::math::sign(fe_conn.get_if_freq()); + int if_freq_sign = boost::math::sign(fe_conn.get_if_freq()); //2. Map IF frequency to the range [0, _adc_rate) double if_freq = std::abs(std::fmod(fe_conn.get_if_freq(), _adc_rate)); //3. Map IF frequency to the range [-_adc_rate/2, _adc_rate/2) @@ -112,15 +112,11 @@ public: } //4. Set DSP offset to spin the signal in the opposite // direction as the aliased frequency - const double cordic_freq = if_freq * (-if_freq_sign); - UHD_ASSERT_THROW( - uhd::math::fp_compare::fp_compare_epsilon<double>(4.0) == - std::abs(_adc_rate / cordic_freq) - ); - - _iface->poke32(REG_RX_FE_HET_CORDIC_PHASE, (cordic_freq > 0) ? 0 : 1); + cordic_freq = if_freq * (-if_freq_sign); } - + int32_t freq_word; + get_freq_and_freq_word(cordic_freq, _adc_rate, actual_cordic_freq, freq_word); + _iface->poke32(REG_RX_FE_HET_CORDIC_PHASE, uint32_t(freq_word)); _fe_conn = fe_conn; } diff --git a/host/lib/usrp/x300/x300_fw_common.h b/host/lib/usrp/x300/x300_fw_common.h index 45301640a..e240d8be6 100644 --- a/host/lib/usrp/x300/x300_fw_common.h +++ b/host/lib/usrp/x300/x300_fw_common.h @@ -23,7 +23,7 @@ extern "C" { #define X300_REVISION_MIN 2 #define X300_FW_COMPAT_MAJOR 6 #define X300_FW_COMPAT_MINOR 0 -#define X300_FPGA_COMPAT_MAJOR 0x24 +#define X300_FPGA_COMPAT_MAJOR 0x23 //shared memory sections - in between the stack and the program space #define X300_FW_SHMEM_BASE 0x6000 diff --git a/images/manifest.txt b/images/manifest.txt index d0bb79ce6..9556e6e02 100644 --- a/images/manifest.txt +++ b/images/manifest.txt @@ -1,8 +1,8 @@ # UHD Image Manifest File # Target hash url SHA256 # X300-Series -x3xx_x310_fpga_default fpga-3de8954a x3xx/fpga-3de8954a/x3xx_x310_fpga_default-g3de8954a.zip cd6a1ddfbc5e2deff8d3c5c157d22945eff4004116fc8b5763b36c346b328bbf -x3xx_x300_fpga_default fpga-3de8954a x3xx/fpga-3de8954a/x3xx_x300_fpga_default-g3de8954a.zip e1a542656131b2a1b17db70df69757efc25811831ff43c5ab47cc5988573ddf7 +x3xx_x310_fpga_default fpga-f1ba32fe x3xx/fpga-f1ba32fe/x3xx_x310_fpga_default-gf1ba32fe.zip 7ff752d3ee01ad3aa62dd405f8afbaaf30c5e77d22effe1c9d55f94b03d37326 +x3xx_x300_fpga_default fpga-f1ba32fe x3xx/fpga-f1ba32fe/x3xx_x300_fpga_default-gf1ba32fe.zip ff3e0416f36170bfa83a7d47dc6164e60cfad1277d0f221e3c69a25e6f21323b # Example daughterboard targets (none currently exist) #x3xx_twinrx_cpld_default example_target #dboard_ubx_cpld_default example_target |