diff options
214 files changed, 22007 insertions, 7386 deletions
diff --git a/firmware/README.md b/firmware/README.md index c8ad9df16..b549d993b 100644 --- a/firmware/README.md +++ b/firmware/README.md @@ -18,7 +18,7 @@ __Build Instructions:__ ## fx3/ -__Description:__ This is the firmware for the FX3 USB PHY, and the AD9361 RFIC. +__Description:__ This is the firmware for the FX3 USB PHY. __Devices:__ USRP B200 and USRP B210 @@ -36,7 +36,12 @@ __Devices:__ Octoclock. __Tools:__ avrtools, cmake -__Build Instructions:__ Run `make` from the Octoclock source directory. +__Build Instructions:__ + +1. mkdir `<build directory>` +2. cd `<build directory>` +3. cmake `<source directory>` +4. make ## zpu/ diff --git a/firmware/fx3/.gitignore b/firmware/fx3/.gitignore new file mode 100644 index 000000000..f2c372d44 --- /dev/null +++ b/firmware/fx3/.gitignore @@ -0,0 +1,3 @@ +common +lpp_source +u3p_firmware diff --git a/firmware/fx3/README.md b/firmware/fx3/README.md index e2e8a13d4..7e94c247c 100644 --- a/firmware/fx3/README.md +++ b/firmware/fx3/README.md @@ -9,10 +9,8 @@ show you how to build our firmware source **A brief "Theory of Operations":** The host sends commands to the FX3, our USB3 PHY, which has an on-board ARM -which runs the FX3 firmware code (hex file). That code translates commands into -SPI commands to/from the AD9361. The SPI lines run through the FPGA (bin or bit -file), where they are level-translated, and then head to the AD9361. Note that -the FPGA takes no action on these SPI lines. They are passive pass-throughs. +which runs the FX3 firmware code (hex file). That code is responsible for +managing the transport from the host to the FPGA by configuring IO and DMA. ## Setting up the Cypress SDK @@ -46,7 +44,6 @@ uhd.git/ | --fx3/ | - --ad9361/ # From UHD --b200/ # From UHD --common/ # From Cypress SDK --gpif2_designer/ # From UHD diff --git a/firmware/fx3/ad9361/include/ad9361_dispatch.h b/firmware/fx3/ad9361/include/ad9361_dispatch.h deleted file mode 100644 index e89a4e0b0..000000000 --- a/firmware/fx3/ad9361/include/ad9361_dispatch.h +++ /dev/null @@ -1,16 +0,0 @@ -// -// Copyright 2013-2014 Ettus Research LLC -// - -#ifndef INCLUDED_AD9361_DISPATCH_H -#define INCLUDED_AD9361_DISPATCH_H - -#include <ad9361_transaction.h> - -extern void ad9361_dispatch(const char* request, char* response); - -typedef void (*msgfn)(const char*, ...); - -extern void ad9361_set_msgfn(msgfn pfn); - -#endif /* INCLUDED_AD9361_DISPATCH_H */ diff --git a/firmware/fx3/ad9361/include/ad9361_transaction.h b/firmware/fx3/ad9361/include/ad9361_transaction.h deleted file mode 100644 index 2349a5d3d..000000000 --- a/firmware/fx3/ad9361/include/ad9361_transaction.h +++ /dev/null @@ -1,90 +0,0 @@ -// -// Copyright 2013-2014 Ettus Research LLC -// - -#ifndef INCLUDED_AD9361_TRANSACTION_H -#define INCLUDED_AD9361_TRANSACTION_H - -#include <stdint.h> - -#ifdef __cplusplus -extern "C" { -#endif - -//various constants -#define AD9361_TRANSACTION_VERSION 0x4 -#define AD9361_DISPATCH_PACKET_SIZE 64 - -//action types -#define AD9361_ACTION_ECHO 0 -#define AD9361_ACTION_INIT 1 -#define AD9361_ACTION_SET_RX1_GAIN 2 -#define AD9361_ACTION_SET_TX1_GAIN 3 -#define AD9361_ACTION_SET_RX2_GAIN 4 -#define AD9361_ACTION_SET_TX2_GAIN 5 -#define AD9361_ACTION_SET_RX_FREQ 6 -#define AD9361_ACTION_SET_TX_FREQ 7 -#define AD9361_ACTION_SET_CODEC_LOOP 8 -#define AD9361_ACTION_SET_CLOCK_RATE 9 -#define AD9361_ACTION_SET_ACTIVE_CHAINS 10 - -static inline void ad9361_double_pack(const double input, uint32_t output[2]) -{ - const uint32_t *p = (const uint32_t *)&input; - output[0] = p[0]; - output[1] = p[1]; -} - -static inline double ad9361_double_unpack(const uint32_t input[2]) -{ - double output = 0.0; - uint32_t *p = (uint32_t *)&output; - p[0] = input[0]; - p[1] = input[1]; - return output; -} - -typedef struct -{ - //version is expected to be AD9361_TRANSACTION_VERSION - //check otherwise for compatibility - uint32_t version; - - //sequence number - increment every call for sanity - uint32_t sequence; - - //action tells us what to do, see AD9361_ACTION_* - uint32_t action; - - union - { - //enable mask for chains - uint32_t enable_mask; - - //true to enable codec internal loopback - uint32_t codec_loop; - - //freq holds request LO freq and result from tune - uint32_t freq[2]; - - //gain holds request gain and result from action - uint32_t gain[2]; - - //rate holds request clock rate and result from action - uint32_t rate[2]; - - } value; - - //error message comes back as a reply - - //set to null string for no error \0 - char error_msg[]; - -} ad9361_transaction_t; - -#define AD9361_TRANSACTION_MAX_ERROR_MSG (AD9361_DISPATCH_PACKET_SIZE - (sizeof(ad9361_transaction_t)-4)-1) // -4 for 'error_msg' alignment padding, -1 for terminating \0 - -#ifdef __cplusplus -} -#endif - -#endif /* INCLUDED_AD9361_TRANSACTION_H */ diff --git a/firmware/fx3/ad9361/lib/ad9361_filter_taps.h b/firmware/fx3/ad9361/lib/ad9361_filter_taps.h deleted file mode 100644 index afbe27630..000000000 --- a/firmware/fx3/ad9361/lib/ad9361_filter_taps.h +++ /dev/null @@ -1,47 +0,0 @@ -// -// Copyright 2013-2014 Ettus Research LLC -// - -#ifndef INCLUDED_AD9361_FILTER_TAPS_HPP -#define INCLUDED_AD9361_FILTER_TAPS_HPP - -/* A default 128-tap filter that can be used for generic circumstances. */ -static uint16_t default_128tap_coeffs[] = { - 0x0001,0xfff1,0xffcf,0xffc0,0xffe8,0x0020,0x001a,0xffe3, - 0xffe1,0x001f,0x0028,0xffdf,0xffcc,0x0024,0x0043,0xffdb, - 0xffac,0x0026,0x0068,0xffdb,0xff80,0x0022,0x009a,0xffe2, - 0xff47,0x0017,0x00db,0xfff3,0xfeff,0xffff,0x012b,0x0013, - 0xfea5,0xffd7,0x0190,0x0046,0xfe35,0xff97,0x020e,0x0095, - 0xfda7,0xff36,0x02ae,0x010d,0xfcf0,0xfea1,0x0383,0x01c6, - 0xfbf3,0xfdb6,0x04b7,0x02f8,0xfa6d,0xfc1a,0x06be,0x0541, - 0xf787,0xf898,0x0b60,0x0b6d,0xee88,0xea40,0x2786,0x7209 -}; - - -/* The below pair of filters is optimized for a 10MHz LTE application. */ -/* -static uint16_t lte10mhz_rx_coeffs[] = { - 0xffe2,0x0042,0x0024,0x0095,0x0056,0x004d,0xffcf,0xffb7, - 0xffb1,0x0019,0x0059,0x006a,0x0004,0xff9d,0xff72,0xffd4, - 0x0063,0x00b7,0x0062,0xffac,0xff21,0xff59,0x0032,0x0101, - 0x00f8,0x0008,0xfeea,0xfeac,0xffa3,0x0117,0x01b5,0x00d0, - 0xff05,0xfdea,0xfe9e,0x00ba,0x026f,0x0215,0xffb5,0xfd4a, - 0xfd18,0xffa0,0x02de,0x03dc,0x0155,0xfd2a,0xfb0d,0xfd54, - 0x0287,0x062f,0x048a,0xfe37,0xf862,0xf8c1,0x004d,0x0963, - 0x0b88,0x02a4,0xf3e7,0xebdd,0xf5f8,0x1366,0x3830,0x518b -}; - -static uint16_t lte10mhz_tx_coeffs[] = { - 0xfffb,0x0000,0x0004,0x0017,0x0024,0x0028,0x0013,0xfff3, - 0xffdc,0xffe5,0x000b,0x0030,0x002e,0xfffe,0xffc4,0xffb8, - 0xfff0,0x0045,0x0068,0x002b,0xffb6,0xff72,0xffad,0x0047, - 0x00b8,0x0088,0xffc8,0xff1c,0xff33,0x001a,0x0110,0x0124, - 0x0019,0xfec8,0xfe74,0xff9a,0x0156,0x0208,0x00d3,0xfe9b, - 0xfd68,0xfe96,0x015d,0x033f,0x0236,0xfecd,0xfc00,0xfcb5, - 0x00d7,0x04e5,0x04cc,0xffd5,0xf9fe,0xf8fb,0xfef2,0x078c, - 0x0aae,0x036d,0xf5c0,0xed89,0xf685,0x12af,0x36a4,0x4faa -}; -*/ - - -#endif // INCLUDED_AD9361_FILTER_TAPS_HPP diff --git a/firmware/fx3/ad9361/lib/ad9361_impl.c b/firmware/fx3/ad9361/lib/ad9361_impl.c deleted file mode 100644 index 61512d2c8..000000000 --- a/firmware/fx3/ad9361/lib/ad9361_impl.c +++ /dev/null @@ -1,1918 +0,0 @@ -// -// Copyright 2013-2014 Ettus Research LLC -// - -/* This file implements b200 vendor requests handler - * It handles ad9361 setup and configuration - */ - -#include <stdarg.h> -#include <stdio.h> -#include <math.h> - -#include <ad9361_transaction.h> -#include "ad9361_filter_taps.h" -#include "ad9361_gain_tables.h" -#include "ad9361_synth_lut.h" -#include "ad9361_dispatch.h" - -//////////////////////////////////////////////////////////// - -static void fake_msg(const char* str, ...) -{ -} - -static msgfn _msgfn = fake_msg; - -//extern void msg(const char* str, ...); External object must provide this symbol -#define msg (_msgfn) - -void ad9361_set_msgfn(msgfn pfn) -{ - _msgfn = pfn; -} - -//////////////////////////////////////////////////////////// -#define AD9361_MAX_GAIN 89.75 - -#define DOUBLE_PI 3.14159265359 -#define DOUBLE_LN_2 0.693147181 - -#define RX_TYPE 0 -#define TX_TYPE 1 - -#ifndef AD9361_CLOCKING_MODE -#error define a AD9361_CLOCKING_MODE -#endif - -#ifndef AD9361_RX_BAND_EDGE0 -#error define a AD9361_RX_BAND_EDGE0 -#endif - -#ifndef AD9361_RX_BAND_EDGE1 -#error define a AD9361_RX_BAND_EDGE1 -#endif - -#ifndef AD9361_TX_BAND_EDGE -#error define a AD9361_TX_BAND_EDGE -#endif - -//////////////////////////////////////////////////////////// -// the following macros evaluate to a compile time constant -// macros By Tom Torfs - donated to the public domain - -/* turn a numeric literal into a hex constant -(avoids problems with leading zeroes) -8-bit constants max value 0x11111111, always fits in unsigned long -*/ -#define HEX__(n) 0x##n##LU - -/* 8-bit conversion function */ -#define B8__(x) ((x&0x0000000FLU)?1:0) \ -+((x&0x000000F0LU)?2:0) \ -+((x&0x00000F00LU)?4:0) \ -+((x&0x0000F000LU)?8:0) \ -+((x&0x000F0000LU)?16:0) \ -+((x&0x00F00000LU)?32:0) \ -+((x&0x0F000000LU)?64:0) \ -+((x&0xF0000000LU)?128:0) - -/* *** user macros *** */ - -/* for upto 8-bit binary constants */ -#define B8(d) ((unsigned char)B8__(HEX__(d))) - -//////////////////////////////////////////////////////////// -// shadow registers -static uint8_t reg_vcodivs; -static uint8_t reg_inputsel; -static uint8_t reg_rxfilt; -static uint8_t reg_txfilt; -static uint8_t reg_bbpll; -static uint8_t reg_bbftune_config; -static uint8_t reg_bbftune_mode; - -//////////////////////////////////////////////////////////// -// other private data fields for VRQ handler -static double _rx_freq, _tx_freq, _req_rx_freq, _req_tx_freq; -static double _baseband_bw, _bbpll_freq, _adcclock_freq; -static double _req_clock_rate, _req_coreclk; -static uint16_t _rx_bbf_tunediv; -static uint8_t _curr_gain_table; -static uint32_t _rx1_gain, _rx2_gain, _tx1_gain, _tx2_gain; -static int _tfir_factor; - -double set_gain(int which, int n, const double value); -void set_active_chains(bool tx1, bool tx2, bool rx1, bool rx2); -/*********************************************************************** - * Placeholders, unused, or test functions - **********************************************************************/ -static char *tmp_req_buffer; - -void post_err_msg(const char* error) -{ - msg("[AD9361 error] %s", error); - - if (!tmp_req_buffer) - return; - - ad9361_transaction_t *request = (ad9361_transaction_t *)tmp_req_buffer; - strncpy(request->error_msg, error, (AD9361_TRANSACTION_MAX_ERROR_MSG + 1)); // '+ 1' as length excludes terminating NUL - request->error_msg[AD9361_TRANSACTION_MAX_ERROR_MSG] = '\0'; // If string was too long, NUL will not be copied, so force one just in case -} - -void write_ad9361_reg(uint32_t reg, uint8_t val) -{ - ad9361_transact_spi((reg << 8) | val | (1 << 23)); -} - -uint8_t read_ad9361_reg(uint32_t reg) -{ - return ad9361_transact_spi((reg << 8)) & 0xff; -} - -//shortcuts for double packer/unpacker function -#define double_pack ad9361_double_pack -#define double_unpack ad9361_double_unpack - -/* Make Catalina output its test tone. */ -void output_test_tone(void) { - /* Output a 480 kHz tone at 800 MHz */ - write_ad9361_reg(0x3F4, 0x0B); - write_ad9361_reg(0x3FC, 0xFF); - write_ad9361_reg(0x3FD, 0xFF); - write_ad9361_reg(0x3FE, 0x3F); -} - -/* Turn on/off Catalina's TX port --> RX port loopback. */ -void data_port_loopback(const int on) { - msg("[data_port_loopback] Enabled: %d", on); - write_ad9361_reg(0x3F5, (on ? 0x01 : 0x00)); -} - -/* This is a simple comparison for very large double-precision floating - * point numbers. It is used to prevent re-tunes for frequencies that are - * the same but not 'exactly' because of data precision issues. */ -// TODO: see if we can avoid the need for this function -int freq_is_nearly_equal(double a, double b) { - return AD9361_MAX(a,b) - AD9361_MIN(a,b) < 1; -} - -/*********************************************************************** - * Filter functions - **********************************************************************/ - -/* This function takes in the calculated maximum number of FIR taps, and - * returns a number of taps that makes Catalina happy. */ -int get_num_taps(int max_num_taps) { - - int num_taps = 0; - int num_taps_list[] = {16, 32, 48, 64, 80, 96, 112, 128}; - int i; - for(i = 1; i < 8; i++) { - if(max_num_taps >= num_taps_list[i]) { - continue; - } else { - num_taps = num_taps_list[i - 1]; - break; - } - } if(num_taps == 0) { num_taps = 128; } - - return num_taps; -} - -/* Program either the RX or TX FIR filter. - * - * The process is the same for both filters, but the function must be told - * how many taps are in the filter, and given a vector of the taps - * themselves. Note that the filters are symmetric, so value of 'num_taps' - * should actually be twice the length of the tap vector. */ -void program_fir_filter(int which, int num_taps, \ - uint16_t *coeffs) { - - uint16_t base; - if(which == RX_TYPE) { - base = 0x0f0; - write_ad9361_reg(base+6, 0x02); //filter gain - } else { - base = 0x060; - } - - /* Write the filter configuration. */ - uint8_t reg_numtaps = (((num_taps / 16) - 1) & 0x07) << 5; - - /* Turn on the filter clock. */ - write_ad9361_reg(base+5, reg_numtaps | 0x1a); - ad9361_msleep(1); - - int num_unique_coeffs = (num_taps / 2); - - /* The filters are symmetric, so iterate over the tap vector, - * programming each index, and then iterate backwards, repeating the - * process. */ - int addr; - for(addr=0; addr < num_unique_coeffs; addr++) { - write_ad9361_reg(base+0, addr); - write_ad9361_reg(base+1, (coeffs[addr]) & 0xff); - write_ad9361_reg(base+2, (coeffs[addr] >> 8) & 0xff); - write_ad9361_reg(base+5, 0xfe); - write_ad9361_reg(base+4, 0x00); - write_ad9361_reg(base+4, 0x00); - } - - for(addr=0; addr < num_unique_coeffs; addr++) { - write_ad9361_reg(base+0, addr+num_unique_coeffs); - write_ad9361_reg(base+1, (coeffs[num_unique_coeffs-1-addr]) & 0xff); - write_ad9361_reg(base+2, (coeffs[num_unique_coeffs-1-addr] >> 8) & 0xff); - write_ad9361_reg(base+5, 0xfe); - write_ad9361_reg(base+4, 0x00); - write_ad9361_reg(base+4, 0x00); - } - - /* Disable the filter clock. */ - write_ad9361_reg(base+5, 0xf8); -} - -/* Program the RX FIR Filter. */ -void setup_rx_fir(int total_num_taps) { - int num_taps = total_num_taps / 2; - uint16_t coeffs[num_taps]; - int i; - for(i = 0; i < num_taps; i++) { - coeffs[num_taps - 1 - i] = default_128tap_coeffs[63 - i]; - } - - program_fir_filter(RX_TYPE, total_num_taps, coeffs); -} - -/* Program the TX FIR Filter. */ -void setup_tx_fir(int total_num_taps) { - int num_taps = total_num_taps / 2; - uint16_t coeffs[num_taps]; - int i; - for(i = 0; i < num_taps; i++) { - coeffs[num_taps - 1 - i] = default_128tap_coeffs[63 - i]; - } - - program_fir_filter(TX_TYPE, total_num_taps, coeffs); -} - -/*********************************************************************** - * Calibration functions - ***********************************************************************/ - -/* Calibrate and lock the BBPLL. - * - * This function should be called anytime the BBPLL is tuned. */ -void calibrate_lock_bbpll() { - write_ad9361_reg(0x03F, 0x05); // Start the BBPLL calibration - write_ad9361_reg(0x03F, 0x01); // Clear the 'start' bit - - /* Increase BBPLL KV and phase margin. */ - write_ad9361_reg(0x04c, 0x86); - write_ad9361_reg(0x04d, 0x01); - write_ad9361_reg(0x04d, 0x05); - - /* Wait for BBPLL lock. */ - int count = 0; - while(!(read_ad9361_reg(0x05e) & 0x80)) { - if(count > 1000) { - post_err_msg("BBPLL not locked"); - break; - } - - count++; - ad9361_msleep(2); - } -} - -/* Calibrate the synthesizer charge pumps. - * - * Technically, this calibration only needs to be done once, at device - * initialization. */ -void calibrate_synth_charge_pumps() { - /* If this function ever gets called, and the ENSM isn't already in the - * ALERT state, then something has gone horribly wrong. */ - if((read_ad9361_reg(0x017) & 0x0F) != 5) { - post_err_msg("Catalina not in ALERT during cal"); - } - - /* Calibrate the RX synthesizer charge pump. */ - int count = 0; - write_ad9361_reg(0x23d, 0x04); - while(!(read_ad9361_reg(0x244) & 0x80)) { - if(count > 5) { - post_err_msg("RX charge pump cal failure"); - break; - } - - count++; - ad9361_msleep(1); - } - write_ad9361_reg(0x23d, 0x00); - - /* Calibrate the TX synthesizer charge pump. */ - count = 0; - write_ad9361_reg(0x27d, 0x04); - while(!(read_ad9361_reg(0x284) & 0x80)) { - if(count > 5) { - post_err_msg("TX charge pump cal failure"); - break; - } - - count++; - ad9361_msleep(1); - } - write_ad9361_reg(0x27d, 0x00); -} - -/* Calibrate the analog BB RX filter. - * - * Note that the filter calibration depends heavily on the baseband - * bandwidth, so this must be re-done after any change to the RX sample - * rate. */ -double calibrate_baseband_rx_analog_filter() { - /* For filter tuning, baseband BW is half the complex BW, and must be - * between 28e6 and 0.2e6. */ - double bbbw = _baseband_bw / 2.0; - if(bbbw > 28e6) { - bbbw = 28e6; - } else if (bbbw < 0.20e6) { - bbbw = 0.20e6; - } - - double rxtune_clk = ((1.4 * bbbw * 2 * - DOUBLE_PI) / DOUBLE_LN_2); - - _rx_bbf_tunediv = AD9361_MIN(511, AD9361_CEIL_INT(_bbpll_freq / rxtune_clk)); - - reg_bbftune_config = (reg_bbftune_config & 0xFE) \ - | ((_rx_bbf_tunediv >> 8) & 0x0001); - - double bbbw_mhz = bbbw / 1e6; - - double temp = ((bbbw_mhz - AD9361_FLOOR_INT(bbbw_mhz)) * 1000) / 7.8125; - uint8_t bbbw_khz = (uint8_t) AD9361_MIN(127, (AD9361_FLOOR_INT(temp + 0.5))); - - /* Set corner frequencies and dividers. */ - write_ad9361_reg(0x1fb, (uint8_t)(bbbw_mhz)); - write_ad9361_reg(0x1fc, bbbw_khz); - write_ad9361_reg(0x1f8, (_rx_bbf_tunediv & 0x00FF)); - write_ad9361_reg(0x1f9, reg_bbftune_config); - - /* RX Mix Voltage settings - only change with apps engineer help. */ - write_ad9361_reg(0x1d5, 0x3f); - write_ad9361_reg(0x1c0, 0x03); - - /* Enable RX1 & RX2 filter tuners. */ - write_ad9361_reg(0x1e2, 0x02); - write_ad9361_reg(0x1e3, 0x02); - - /* Run the calibration! */ - int count = 0; - write_ad9361_reg(0x016, 0x80); - while(read_ad9361_reg(0x016) & 0x80) { - if(count > 100) { - post_err_msg("RX baseband filter cal FAILURE"); - break; - } - - count++; - ad9361_msleep(1); - } - - /* Disable RX1 & RX2 filter tuners. */ - write_ad9361_reg(0x1e2, 0x03); - write_ad9361_reg(0x1e3, 0x03); - - return bbbw; -} - -/* Calibrate the analog BB TX filter. - * - * Note that the filter calibration depends heavily on the baseband - * bandwidth, so this must be re-done after any change to the TX sample - * rate. */ -double calibrate_baseband_tx_analog_filter() { - /* For filter tuning, baseband BW is half the complex BW, and must be - * between 28e6 and 0.2e6. */ - double bbbw = _baseband_bw / 2.0; - if(bbbw > 20e6) { - bbbw = 20e6; - } else if (bbbw < 0.625e6) { - bbbw = 0.625e6; - } - - double txtune_clk = ((1.6 * bbbw * 2 * - DOUBLE_PI) / DOUBLE_LN_2); - - uint16_t txbbfdiv = AD9361_MIN(511, (AD9361_CEIL_INT(_bbpll_freq / txtune_clk))); - - reg_bbftune_mode = (reg_bbftune_mode & 0xFE) \ - | ((txbbfdiv >> 8) & 0x0001); - - /* Program the divider values. */ - write_ad9361_reg(0x0d6, (txbbfdiv & 0x00FF)); - write_ad9361_reg(0x0d7, reg_bbftune_mode); - - /* Enable the filter tuner. */ - write_ad9361_reg(0x0ca, 0x22); - - /* Calibrate! */ - int count = 0; - write_ad9361_reg(0x016, 0x40); - while(read_ad9361_reg(0x016) & 0x40) { - if(count > 100) { - post_err_msg("TX baseband filter cal FAILURE"); - break; - } - - count++; - ad9361_msleep(1); - } - - /* Disable the filter tuner. */ - write_ad9361_reg(0x0ca, 0x26); - - return bbbw; -} - -/* Calibrate the secondary TX filter. - * - * This filter also depends on the TX sample rate, so if a rate change is - * made, the previous calibration will no longer be valid. */ -void calibrate_secondary_tx_filter() { - /* For filter tuning, baseband BW is half the complex BW, and must be - * between 20e6 and 0.53e6. */ - double bbbw = _baseband_bw / 2.0; - if(bbbw > 20e6) { - bbbw = 20e6; - } else if (bbbw < 0.53e6) { - bbbw = 0.53e6; - } - - double bbbw_mhz = bbbw / 1e6; - - /* Start with a resistor value of 100 Ohms. */ - int res = 100; - - /* Calculate target corner frequency. */ - double corner_freq = 5 * bbbw_mhz * 2 * DOUBLE_PI; - - /* Iterate through RC values to determine correct combination. */ - int cap = 0; - int i; - for(i = 0; i <= 3; i++) { - cap = (AD9361_FLOOR_INT(0.5 + (( 1 / ((corner_freq * res) * 1e6)) * 1e12))) - 12; - - if(cap <= 63) { - break; - } - - res = res * 2; - } - if(cap > 63) { - cap = 63; - } - - uint8_t reg0d0, reg0d1, reg0d2; - - /* Translate baseband bandwidths to register settings. */ - if((bbbw_mhz * 2) <= 9) { - reg0d0 = 0x59; - } else if(((bbbw_mhz * 2) > 9) && ((bbbw_mhz * 2) <= 24)) { - reg0d0 = 0x56; - } else if((bbbw_mhz * 2) > 24) { - reg0d0 = 0x57; - } else { - post_err_msg("Cal2ndTxFil: INVALID_CODE_PATH bad bbbw_mhz"); - reg0d0 = 0x00; - } - - /* Translate resistor values to register settings. */ - if(res == 100) { - reg0d1 = 0x0c; - } else if(res == 200) { - reg0d1 = 0x04; - } else if(res == 400) { - reg0d1 = 0x03; - } else if(res == 800) { - reg0d1 = 0x01; - } else { - reg0d1 = 0x0c; - } - - reg0d2 = cap; - - /* Program the above-calculated values. Sweet. */ - write_ad9361_reg(0x0d2, reg0d2); - write_ad9361_reg(0x0d1, reg0d1); - write_ad9361_reg(0x0d0, reg0d0); -} - -/* Calibrate the RX TIAs. - * - * Note that the values in the TIA register, after calibration, vary with - * the RX gain settings. */ -void calibrate_rx_TIAs() { - - uint8_t reg1eb = read_ad9361_reg(0x1eb) & 0x3F; - uint8_t reg1ec = read_ad9361_reg(0x1ec) & 0x7F; - uint8_t reg1e6 = read_ad9361_reg(0x1e6) & 0x07; - uint8_t reg1db = 0x00; - uint8_t reg1dc = 0x00; - uint8_t reg1dd = 0x00; - uint8_t reg1de = 0x00; - uint8_t reg1df = 0x00; - - /* For calibration, baseband BW is half the complex BW, and must be - * between 28e6 and 0.2e6. */ - double bbbw = _baseband_bw / 2.0; - if(bbbw > 20e6) { - bbbw = 20e6; - } else if (bbbw < 0.20e6) { - bbbw = 0.20e6; - } - double ceil_bbbw_mhz = AD9361_CEIL_INT(bbbw / 1e6); - - /* Do some crazy resistor and capacitor math. */ - int Cbbf = (reg1eb * 160) + (reg1ec * 10) + 140; - int R2346 = 18300 * (reg1e6 & 0x07); - double CTIA_fF = (Cbbf * R2346 * 0.56) / 3500; - - /* Translate baseband BW to register settings. */ - if(ceil_bbbw_mhz <= 3) { - reg1db = 0xe0; - } else if((ceil_bbbw_mhz > 3) && (ceil_bbbw_mhz <= 10)) { - reg1db = 0x60; - } else if(ceil_bbbw_mhz > 10) { - reg1db = 0x20; - } else { - post_err_msg("CalRxTias: INVALID_CODE_PATH bad bbbw_mhz"); - } - - if(CTIA_fF > 2920) { - reg1dc = 0x40; - reg1de = 0x40; - - uint8_t temp = (uint8_t) AD9361_MIN(127, (AD9361_FLOOR_INT(0.5 + ((CTIA_fF - 400.0) / 320.0)))); - reg1dd = temp; - reg1df = temp; - } else { - uint8_t temp = (uint8_t) AD9361_FLOOR_INT(0.5 + ((CTIA_fF - 400.0) / 40.0)) + 0x40; - reg1dc = temp; - reg1de = temp; - reg1dd = 0; - reg1df = 0; - } - - /* w00t. Settings calculated. Program them and roll out. */ - write_ad9361_reg(0x1db, reg1db); - write_ad9361_reg(0x1dd, reg1dd); - write_ad9361_reg(0x1df, reg1df); - write_ad9361_reg(0x1dc, reg1dc); - write_ad9361_reg(0x1de, reg1de); -} - -/* Setup the Catalina ADC. - * - * There are 40 registers that control the ADC's operation, most of the - * values of which must be derived mathematically, dependent on the current - * setting of the BBPLL. Note that the order of calculation is critical, as - * some of the 40 registers depend on the values in others. */ -void setup_adc() { - double bbbw_mhz = (((_bbpll_freq / 1e6) / _rx_bbf_tunediv) * DOUBLE_LN_2) \ - / (1.4 * 2 * DOUBLE_PI); - - /* For calibration, baseband BW is half the complex BW, and must be - * between 28e6 and 0.2e6. */ - if(bbbw_mhz > 28) { - bbbw_mhz = 28; - } else if (bbbw_mhz < 0.20) { - bbbw_mhz = 0.20; - } - - uint8_t rxbbf_c3_msb = read_ad9361_reg(0x1eb) & 0x3F; - uint8_t rxbbf_c3_lsb = read_ad9361_reg(0x1ec) & 0x7F; - uint8_t rxbbf_r2346 = read_ad9361_reg(0x1e6) & 0x07; - - double fsadc = _adcclock_freq / 1e6; - - /* Sort out the RC time constant for our baseband bandwidth... */ - double rc_timeconst = 0.0; - if(bbbw_mhz < 18) { - rc_timeconst = (1 / ((1.4 * 2 * DOUBLE_PI) \ - * (18300 * rxbbf_r2346) - * ((160e-15 * rxbbf_c3_msb) - + (10e-15 * rxbbf_c3_lsb) + 140e-15) - * (bbbw_mhz * 1e6))); - } else { - rc_timeconst = (1 / ((1.4 * 2 * DOUBLE_PI) \ - * (18300 * rxbbf_r2346) - * ((160e-15 * rxbbf_c3_msb) - + (10e-15 * rxbbf_c3_lsb) + 140e-15) - * (bbbw_mhz * 1e6) * (1 + (0.01 * (bbbw_mhz - 18))))); - } - - double scale_res = ad9361_sqrt(1 / rc_timeconst); - double scale_cap = ad9361_sqrt(1 / rc_timeconst); - - double scale_snr = (_adcclock_freq < 80e6) ? 1.0 : 1.584893192; - double maxsnr = 640 / 160; - - /* Calculate the values for all 40 settings registers. - * - * DO NOT TOUCH THIS UNLESS YOU KNOW EXACTLY WHAT YOU ARE DOING. kthx.*/ - uint8_t data[40]; - data[0] = 0; data[1] = 0; data[2] = 0; data[3] = 0x24; - data[4] = 0x24; data[5] = 0; data[6] = 0; - data[7] = (uint8_t) AD9361_MIN(124, (AD9361_FLOOR_INT(-0.5 - + (80.0 * scale_snr * scale_res - * AD9361_MIN(1.0, ad9361_sqrt(maxsnr * fsadc / 640.0)))))); - double data007 = data[7]; - data[8] = (uint8_t) AD9361_MIN(255, (AD9361_FLOOR_INT(0.5 - + ((20.0 * (640.0 / fsadc) * ((data007 / 80.0)) - / (scale_res * scale_cap)))))); - data[10] = (uint8_t) AD9361_MIN(127, (AD9361_FLOOR_INT(-0.5 + (77.0 * scale_res - * AD9361_MIN(1.0, ad9361_sqrt(maxsnr * fsadc / 640.0)))))); - double data010 = data[10]; - data[9] = (uint8_t) AD9361_MIN(127, (AD9361_FLOOR_INT(0.8 * data010))); - data[11] = (uint8_t) AD9361_MIN(255, (AD9361_FLOOR_INT(0.5 - + (20.0 * (640.0 / fsadc) * ((data010 / 77.0) - / (scale_res * scale_cap)))))); - data[12] = (uint8_t) AD9361_MIN(127, (AD9361_FLOOR_INT(-0.5 - + (80.0 * scale_res * AD9361_MIN(1.0, - ad9361_sqrt(maxsnr * fsadc / 640.0)))))); - double data012 = data[12]; - data[13] = (uint8_t) AD9361_MIN(255, (AD9361_FLOOR_INT(-1.5 - + (20.0 * (640.0 / fsadc) * ((data012 / 80.0) - / (scale_res * scale_cap)))))); - data[14] = 21 * (uint8_t)(AD9361_FLOOR_INT(0.1 * 640.0 / fsadc)); - data[15] = (uint8_t) AD9361_MIN(127, (1.025 * data007)); - double data015 = data[15]; - data[16] = (uint8_t) AD9361_MIN(127, (AD9361_FLOOR_INT((data015 - * (0.98 + (0.02 * AD9361_MAX(1.0, - (640.0 / fsadc) / maxsnr))))))); - data[17] = data[15]; - data[18] = (uint8_t) AD9361_MIN(127, (0.975 * (data010))); - double data018 = data[18]; - data[19] = (uint8_t) AD9361_MIN(127, (AD9361_FLOOR_INT((data018 - * (0.98 + (0.02 * AD9361_MAX(1.0, - (640.0 / fsadc) / maxsnr))))))); - data[20] = data[18]; - data[21] = (uint8_t) AD9361_MIN(127, (0.975 * data012)); - double data021 = data[21]; - data[22] = (uint8_t) AD9361_MIN(127, (AD9361_FLOOR_INT((data021 - * (0.98 + (0.02 * AD9361_MAX(1.0, - (640.0 / fsadc) / maxsnr))))))); - data[23] = data[21]; - data[24] = 0x2e; - data[25] = (uint8_t)(AD9361_FLOOR_INT(128.0 + AD9361_MIN(63.0, - 63.0 * (fsadc / 640.0)))); - data[26] = (uint8_t)(AD9361_FLOOR_INT(AD9361_MIN(63.0, 63.0 * (fsadc / 640.0) - * (0.92 + (0.08 * (640.0 / fsadc)))))); - data[27] = (uint8_t)(AD9361_FLOOR_INT(AD9361_MIN(63.0, - 32.0 * ad9361_sqrt(fsadc / 640.0)))); - data[28] = (uint8_t)(AD9361_FLOOR_INT(128.0 + AD9361_MIN(63.0, - 63.0 * (fsadc / 640.0)))); - data[29] = (uint8_t)(AD9361_FLOOR_INT(AD9361_MIN(63.0, - 63.0 * (fsadc / 640.0) - * (0.92 + (0.08 * (640.0 / fsadc)))))); - data[30] = (uint8_t)(AD9361_FLOOR_INT(AD9361_MIN(63.0, - 32.0 * ad9361_sqrt(fsadc / 640.0)))); - data[31] = (uint8_t)(AD9361_FLOOR_INT(128.0 + AD9361_MIN(63.0, - 63.0 * (fsadc / 640.0)))); - data[32] = (uint8_t)(AD9361_FLOOR_INT(AD9361_MIN(63.0, - 63.0 * (fsadc / 640.0) * (0.92 - + (0.08 * (640.0 / fsadc)))))); - data[33] = (uint8_t)(AD9361_FLOOR_INT(AD9361_MIN(63.0, - 63.0 * ad9361_sqrt(fsadc / 640.0)))); - data[34] = (uint8_t) AD9361_MIN(127, (AD9361_FLOOR_INT(64.0 - * ad9361_sqrt(fsadc / 640.0)))); - data[35] = 0x40; - data[36] = 0x40; - data[37] = 0x2c; - data[38] = 0x00; - data[39] = 0x00; - - /* Program the registers! */ - int i; - for(i=0; i<40; i++) { - write_ad9361_reg(0x200+i, data[i]); - } - -} - -/* Calibrate the baseband DC offset. - * - * Note that this function is called from within the TX quadrature - * calibration function! */ -void calibrate_baseband_dc_offset() { - write_ad9361_reg(0x193, 0x3f); // Calibration settings - write_ad9361_reg(0x190, 0x0f); // Set tracking coefficient - //write_ad9361_reg(0x190, /*0x0f*//*0xDF*/0x80*1 | 0x40*1 | (16+8/*+4*/)); // Set tracking coefficient: don't *4 counter, do decim /4, increased gain shift - write_ad9361_reg(0x194, 0x01); // More calibration settings - - /* Start that calibration, baby. */ - int count = 0; - write_ad9361_reg(0x016, 0x01); - while(read_ad9361_reg(0x016) & 0x01) { - if(count > 100) { - post_err_msg("Baseband DC Offset Calibration Failure"); - break; - } - - count++; - ad9361_msleep(5); - } -} - -/* Calibrate the RF DC offset. - * - * Note that this function is called from within the TX quadrature - * calibration function. */ -void calibrate_rf_dc_offset() { - /* Some settings are frequency-dependent. */ - if(_rx_freq < 4e9) { - write_ad9361_reg(0x186, 0x32); // RF DC Offset count - write_ad9361_reg(0x187, 0x24); - write_ad9361_reg(0x188, 0x05); - } else { - write_ad9361_reg(0x186, 0x28); // RF DC Offset count - write_ad9361_reg(0x187, 0x34); - write_ad9361_reg(0x188, 0x06); - } - - write_ad9361_reg(0x185, 0x20); // RF DC Offset wait count - write_ad9361_reg(0x18b, 0x83); - write_ad9361_reg(0x189, 0x30); - - /* Run the calibration! */ - int count = 0; - write_ad9361_reg(0x016, 0x02); - while(read_ad9361_reg(0x016) & 0x02) { - if(count > 100) { - post_err_msg("RF DC Offset Calibration Failure"); - break; - } - - count++; - ad9361_msleep(50); - } -} - -/* Start the RX quadrature calibration. - * - * Note that we are using Catalina's 'tracking' feature for RX quadrature - * calibration, so once it starts it continues to free-run during operation. - * It should be re-run for large frequency changes. */ -void calibrate_rx_quadrature(void) { - /* Configure RX Quadrature calibration settings. */ - write_ad9361_reg(0x168, 0x03); // Set tone level for cal - write_ad9361_reg(0x16e, 0x25); // RX Gain index to use for cal - write_ad9361_reg(0x16a, 0x75); // Set Kexp phase - write_ad9361_reg(0x16b, 0x15); // Set Kexp amplitude - write_ad9361_reg(0x169, 0xcf); // Continuous tracking mode - write_ad9361_reg(0x18b, 0xad); -} - -/* TX quadtrature calibration routine. - * - * The TX quadrature needs to be done twice, once for each TX chain, with - * only one register change in between. Thus, this function enacts the - * calibrations, and it is called from calibrate_tx_quadrature. */ -void tx_quadrature_cal_routine(void) { - - /* This is a weird process, but here is how it works: - * 1) Read the calibrated NCO frequency bits out of 0A3. - * 2) Write the two bits to the RX NCO freq part of 0A0. - * 3) Re-read 0A3 to get bits [5:0] because maybe they changed? - * 4) Update only the TX NCO freq bits in 0A3. - * 5) Profit (I hope). */ - uint8_t reg0a3 = read_ad9361_reg(0x0a3); - uint8_t nco_freq = (reg0a3 & 0xC0); - write_ad9361_reg(0x0a0, 0x15 | (nco_freq >> 1)); - reg0a3 = read_ad9361_reg(0x0a3); - write_ad9361_reg(0x0a3, (reg0a3 & 0x3F) | nco_freq); - - /* It is possible to reach a configuration that won't operate correctly, - * where the two test tones used for quadrature calibration are outside - * of the RX BBF, and therefore don't make it to the ADC. We will check - * for that scenario here. */ - double max_cal_freq = (((_baseband_bw * _tfir_factor) * ((nco_freq >> 6) + 1)) / 32) * 2; - double bbbw = _baseband_bw / 2.0; // bbbw represents the one-sided BW - if(bbbw > 28e6) { - bbbw = 28e6; - } else if (bbbw < 0.20e6) { - bbbw = 0.20e6; - } - if (max_cal_freq > bbbw ) - post_err_msg("max_cal_freq > bbbw"); - - write_ad9361_reg(0x0a1, 0x7B); // Set tracking coefficient - write_ad9361_reg(0x0a9, 0xff); // Cal count - write_ad9361_reg(0x0a2, 0x7f); // Cal Kexp - write_ad9361_reg(0x0a5, 0x01); // Cal magnitude threshold VVVV - write_ad9361_reg(0x0a6, 0x01); - - /* The gain table index used for calibration must be adjusted for the - * mid-table to get a TIA index = 1 and LPF index = 0. */ - if((_rx_freq >= 1300e6) && (_rx_freq < 4000e6)) { - write_ad9361_reg(0x0aa, 0x22); // Cal gain table index - } else { - write_ad9361_reg(0x0aa, 0x25); // Cal gain table index - } - - write_ad9361_reg(0x0a4, 0xf0); // Cal setting conut - write_ad9361_reg(0x0ae, 0x00); // Cal LPF gain index (split mode) - - /* First, calibrate the baseband DC offset. */ - calibrate_baseband_dc_offset(); - - /* Second, calibrate the RF DC offset. */ - calibrate_rf_dc_offset(); - - /* Now, calibrate the TX quadrature! */ - int count = 0; - write_ad9361_reg(0x016, 0x10); - while(read_ad9361_reg(0x016) & 0x10) { - if(count > 100) { - post_err_msg("TX Quadrature Calibration Failure"); - break; - } - - count++; - ad9361_msleep(10); - } -} - -/* Run the TX quadrature calibration. - * - * Note that from within this function we are also triggering the baseband - * and RF DC calibrations. */ -void calibrate_tx_quadrature(void) { - /* Make sure we are, in fact, in the ALERT state. If not, something is - * terribly wrong in the driver execution flow. */ - if((read_ad9361_reg(0x017) & 0x0F) != 5) { - post_err_msg("TX Quad Cal started, but not in ALERT"); - } - - /* Turn off free-running and continuous calibrations. Note that this - * will get turned back on at the end of the RX calibration routine. */ - write_ad9361_reg(0x169, 0xc0); - - /* This calibration must be done in a certain order, and for both TX_A - * and TX_B, separately. Store the original setting so that we can - * restore it later. */ - uint8_t orig_reg_inputsel = reg_inputsel; - - /*********************************************************************** - * TX1/2-A Calibration - **********************************************************************/ - reg_inputsel = reg_inputsel & 0xBF; - write_ad9361_reg(0x004, reg_inputsel); - - tx_quadrature_cal_routine(); - - /*********************************************************************** - * TX1/2-B Calibration - **********************************************************************/ - reg_inputsel = reg_inputsel | 0x40; - write_ad9361_reg(0x004, reg_inputsel); - - tx_quadrature_cal_routine(); - - /*********************************************************************** - * fin - **********************************************************************/ - reg_inputsel = orig_reg_inputsel; - write_ad9361_reg(0x004, orig_reg_inputsel); -} - - -/*********************************************************************** - * Other Misc Setup Functions - ***********************************************************************/ - -/* Program the mixer gain table. - * - * Note that this table is fixed for all frequency settings. */ -void program_mixer_gm_subtable() { - uint8_t gain[] = {0x78, 0x74, 0x70, 0x6C, 0x68, 0x64, 0x60, 0x5C, 0x58, - 0x54, 0x50, 0x4C, 0x48, 0x30, 0x18, 0x00}; - uint8_t gm[] = {0x00, 0x0D, 0x15, 0x1B, 0x21, 0x25, 0x29, 0x2C, 0x2F, - 0x31, 0x33, 0x34, 0x35, 0x3A, 0x3D, 0x3E}; - - /* Start the clock. */ - write_ad9361_reg(0x13f, 0x02); - - /* Program the GM Sub-table. */ - int i; - for(i = 15; i >= 0; i--) { - write_ad9361_reg(0x138, i); - write_ad9361_reg(0x139, gain[(15 - i)]); - write_ad9361_reg(0x13A, 0x00); - write_ad9361_reg(0x13B, gm[(15 - i)]); - write_ad9361_reg(0x13F, 0x06); - write_ad9361_reg(0x13C, 0x00); - write_ad9361_reg(0x13C, 0x00); - } - - /* Clear write bit and stop clock. */ - write_ad9361_reg(0x13f, 0x02); - write_ad9361_reg(0x13C, 0x00); - write_ad9361_reg(0x13C, 0x00); - write_ad9361_reg(0x13f, 0x00); -} - -/* Program the gain table. - * - * There are three different gain tables for different frequency ranges! */ -void program_gain_table() { - - /* Figure out which gain table we should be using for our current - * frequency band. */ - uint8_t (*gain_table)[5] = NULL; - uint8_t new_gain_table; - if(_rx_freq < 1300e6) { - gain_table = gain_table_sub_1300mhz; - new_gain_table = 1; - } else if(_rx_freq < 4e9) { - gain_table = gain_table_1300mhz_to_4000mhz; - new_gain_table = 2; - } else if(_rx_freq <= 6e9) { - gain_table = gain_table_4000mhz_to_6000mhz; - new_gain_table = 3; - } else { - post_err_msg("Wrong _rx_freq value"); - new_gain_table = 1; - } - - /* Only re-program the gain table if there has been a band change. */ - if(_curr_gain_table == new_gain_table) { - return; - } else { - _curr_gain_table = new_gain_table; - } - - /* Okay, we have to program a new gain table. Sucks, brah. Start the - * gain table clock. */ - write_ad9361_reg(0x137, 0x1A); - - /* IT'S PROGRAMMING TIME. */ - uint8_t index = 0; - for(; index < 77; index++) { - write_ad9361_reg(0x130, index); - write_ad9361_reg(0x131, gain_table[index][1]); - write_ad9361_reg(0x132, gain_table[index][2]); - write_ad9361_reg(0x133, gain_table[index][3]); - write_ad9361_reg(0x137, 0x1E); - write_ad9361_reg(0x134, 0x00); - write_ad9361_reg(0x134, 0x00); - } - - /* Everything above the 77th index is zero. */ - for(; index < 91; index++) { - write_ad9361_reg(0x130, index); - write_ad9361_reg(0x131, 0x00); - write_ad9361_reg(0x132, 0x00); - write_ad9361_reg(0x133, 0x00); - write_ad9361_reg(0x137, 0x1E); - write_ad9361_reg(0x134, 0x00); - write_ad9361_reg(0x134, 0x00); - } - - /* Clear the write bit and stop the gain clock. */ - write_ad9361_reg(0x137, 0x1A); - write_ad9361_reg(0x134, 0x00); - write_ad9361_reg(0x134, 0x00); - write_ad9361_reg(0x137, 0x00); -} - -/* Setup gain control registers. - * - * This really only needs to be done once, at initialization. */ -void setup_gain_control() { - write_ad9361_reg(0x0FA, 0xE0); // Gain Control Mode Select - write_ad9361_reg(0x0FB, 0x08); // Table, Digital Gain, Man Gain Ctrl - write_ad9361_reg(0x0FC, 0x23); // Incr Step Size, ADC Overrange Size - write_ad9361_reg(0x0FD, 0x4C); // Max Full/LMT Gain Table Index - write_ad9361_reg(0x0FE, 0x44); // Decr Step Size, Peak Overload Time - write_ad9361_reg(0x100, 0x6F); // Max Digital Gain - write_ad9361_reg(0x104, 0x2F); // ADC Small Overload Threshold - write_ad9361_reg(0x105, 0x3A); // ADC Large Overload Threshold - write_ad9361_reg(0x107, 0x31); // Large LMT Overload Threshold - write_ad9361_reg(0x108, 0x39); // Small LMT Overload Threshold - write_ad9361_reg(0x109, 0x23); // Rx1 Full/LMT Gain Index - write_ad9361_reg(0x10A, 0x58); // Rx1 LPF Gain Index - write_ad9361_reg(0x10B, 0x00); // Rx1 Digital Gain Index - write_ad9361_reg(0x10C, 0x23); // Rx2 Full/LMT Gain Index - write_ad9361_reg(0x10D, 0x18); // Rx2 LPF Gain Index - write_ad9361_reg(0x10E, 0x00); // Rx2 Digital Gain Index - write_ad9361_reg(0x114, 0x30); // Low Power Threshold - write_ad9361_reg(0x11A, 0x27); // Initial LMT Gain Limit - write_ad9361_reg(0x081, 0x00); // Tx Symbol Gain Control -} - -/* Setup the RX or TX synthesizers. - * - * This setup depends on a fixed look-up table, which is stored in an - * included header file. The table is indexed based on the passed VCO rate. - */ -void setup_synth(int which, double vcorate) { - /* The vcorates in the vco_index array represent lower boundaries for - * rates. Once we find a match, we use that index to look-up the rest of - * the register values in the LUT. */ - int vcoindex = 0; - int i; - for(i = 0; i < 53; i++) { - vcoindex = i; - if(vcorate > vco_index[i]) { - break; - } - } - - if (vcoindex > 53) - post_err_msg("vcoindex > 53"); - - /* Parse the values out of the LUT based on our calculated index... */ - uint8_t vco_output_level = synth_cal_lut[vcoindex][0]; - uint8_t vco_varactor = synth_cal_lut[vcoindex][1]; - uint8_t vco_bias_ref = synth_cal_lut[vcoindex][2]; - uint8_t vco_bias_tcf = synth_cal_lut[vcoindex][3]; - uint8_t vco_cal_offset = synth_cal_lut[vcoindex][4]; - uint8_t vco_varactor_ref = synth_cal_lut[vcoindex][5]; - uint8_t charge_pump_curr = synth_cal_lut[vcoindex][6]; - uint8_t loop_filter_c2 = synth_cal_lut[vcoindex][7]; - uint8_t loop_filter_c1 = synth_cal_lut[vcoindex][8]; - uint8_t loop_filter_r1 = synth_cal_lut[vcoindex][9]; - uint8_t loop_filter_c3 = synth_cal_lut[vcoindex][10]; - uint8_t loop_filter_r3 = synth_cal_lut[vcoindex][11]; - - /* ... annnd program! */ - if(which == RX_TYPE) { - write_ad9361_reg(0x23a, 0x40 | vco_output_level); - write_ad9361_reg(0x239, 0xC0 | vco_varactor); - write_ad9361_reg(0x242, vco_bias_ref | (vco_bias_tcf << 3)); - write_ad9361_reg(0x238, (vco_cal_offset << 3)); - write_ad9361_reg(0x245, 0x00); - write_ad9361_reg(0x251, vco_varactor_ref); - write_ad9361_reg(0x250, 0x70); - write_ad9361_reg(0x23b, 0x80 | charge_pump_curr); - write_ad9361_reg(0x23e, loop_filter_c1 | (loop_filter_c2 << 4)); - write_ad9361_reg(0x23f, loop_filter_c3 | (loop_filter_r1 << 4)); - write_ad9361_reg(0x240, loop_filter_r3); - } else if(which == TX_TYPE) { - write_ad9361_reg(0x27a, 0x40 | vco_output_level); - write_ad9361_reg(0x279, 0xC0 | vco_varactor); - write_ad9361_reg(0x282, vco_bias_ref | (vco_bias_tcf << 3)); - write_ad9361_reg(0x278, (vco_cal_offset << 3)); - write_ad9361_reg(0x285, 0x00); - write_ad9361_reg(0x291, vco_varactor_ref); - write_ad9361_reg(0x290, 0x70); - write_ad9361_reg(0x27b, 0x80 | charge_pump_curr); - write_ad9361_reg(0x27e, loop_filter_c1 | (loop_filter_c2 << 4)); - write_ad9361_reg(0x27f, loop_filter_c3 | (loop_filter_r1 << 4)); - write_ad9361_reg(0x280, loop_filter_r3); - } else { - post_err_msg("[setup_synth] INVALID_CODE_PATH"); - } -} - - -/* Tune the baseband VCO. - * - * This clock signal is what gets fed to the ADCs and DACs. This function is - * not exported outside of this file, and is invoked based on the rate - * fed to the public set_clock_rate function. */ -double tune_bbvco(const double rate) { - msg("[tune_bbvco] rate=%.10f", rate); - - /* Let's not re-tune to the same frequency over and over... */ - if(freq_is_nearly_equal(rate, _req_coreclk)) { - return _adcclock_freq; - } - - _req_coreclk = rate; - - const double fref = 40e6; - const int modulus = 2088960; - const double vcomax = 1430e6; - const double vcomin = 672e6; - double vcorate; - int vcodiv; - - /* Iterate over VCO dividers until appropriate divider is found. */ - int i = 1; - for(; i <= 6; i++) { - vcodiv = 1 << i; - vcorate = rate * vcodiv; - - if(vcorate >= vcomin && vcorate <= vcomax) break; - } - if(i == 7) - post_err_msg("[tune_bbvco] wrong vcorate"); - - msg("[tune_bbvco] vcodiv=%d vcorate=%.10f", vcodiv, vcorate); - - /* Fo = Fref * (Nint + Nfrac / mod) */ - int nint = vcorate / fref; - msg("[tune_bbvco] (nint)=%.10f", (vcorate / fref)); - int nfrac = lround(((vcorate / fref) - (double)nint) * (double)modulus); - msg("[tune_bbvco] (nfrac)=%.10f", (((vcorate / fref) - (double)nint) * (double)modulus)); - msg("[tune_bbvco] nint=%d nfrac=%d", nint, nfrac); - double actual_vcorate = fref * ((double)nint + ((double)nfrac / (double)modulus)); - - /* Scale CP current according to VCO rate */ - const double icp_baseline = 150e-6; - const double freq_baseline = 1280e6; - double icp = icp_baseline * (actual_vcorate / freq_baseline); - int icp_reg = (icp / 25e-6) - 1; - - write_ad9361_reg(0x045, 0x00); // REFCLK / 1 to BBPLL - write_ad9361_reg(0x046, icp_reg & 0x3F); // CP current - write_ad9361_reg(0x048, 0xe8); // BBPLL loop filters - write_ad9361_reg(0x049, 0x5b); // BBPLL loop filters - write_ad9361_reg(0x04a, 0x35); // BBPLL loop filters - - write_ad9361_reg(0x04b, 0xe0); - write_ad9361_reg(0x04e, 0x10); // Max accuracy - - write_ad9361_reg(0x043, nfrac & 0xFF); // Nfrac[7:0] - write_ad9361_reg(0x042, (nfrac >> 8) & 0xFF); // Nfrac[15:8] - write_ad9361_reg(0x041, (nfrac >> 16) & 0xFF); // Nfrac[23:16] - write_ad9361_reg(0x044, nint); // Nint - - calibrate_lock_bbpll(); - - reg_bbpll = (reg_bbpll & 0xF8) | i; - - _bbpll_freq = actual_vcorate; - _adcclock_freq = (actual_vcorate / vcodiv); - - return _adcclock_freq; -} - -/* This function re-programs all of the gains in the system. - * - * Because the gain values match to different gain indices based on the - * current operating band, this function can be called to update all gain - * settings to the appropriate index after a re-tune. */ -void program_gains() { - set_gain(RX_TYPE,1, _rx1_gain); - set_gain(RX_TYPE,2, _rx2_gain); - set_gain(TX_TYPE,1, _tx1_gain); - set_gain(TX_TYPE,2, _tx2_gain); -} - -/* This is the internal tune function, not available for a host call. - * - * Calculate the VCO settings for the requested frquency, and then either - * tune the RX or TX VCO. */ -double tune_helper(int which, const double value) { - - /* The RFPLL runs from 6 GHz - 12 GHz */ - const double fref = 80e6; - const int modulus = 8388593; - const double vcomax = 12e9; - const double vcomin = 6e9; - double vcorate; - int vcodiv; - - /* Iterate over VCO dividers until appropriate divider is found. */ - int i; - for(i = 0; i <= 6; i++) { - vcodiv = 2 << i; - vcorate = value * vcodiv; - if(vcorate >= vcomin && vcorate <= vcomax) break; - } - if(i == 7) - post_err_msg("RFVCO can't find valid VCO rate!"); - - int nint = vcorate / fref; - int nfrac = ((vcorate / fref) - nint) * modulus; - - double actual_vcorate = fref * (nint + (double)(nfrac)/modulus); - double actual_lo = actual_vcorate / vcodiv; - - // UHD_VAR(actual_lo); // TODO: - - if(which == RX_TYPE) { - - _req_rx_freq = value; - - /* Set band-specific settings. */ - if(value < AD9361_RX_BAND_EDGE0) { - reg_inputsel = (reg_inputsel & 0xC0) | 0x30; - } else if((value >= AD9361_RX_BAND_EDGE0) && (value < AD9361_RX_BAND_EDGE1)) { - reg_inputsel = (reg_inputsel & 0xC0) | 0x0C; - } else if((value >= AD9361_RX_BAND_EDGE1) && (value <= 6e9)) { - reg_inputsel = (reg_inputsel & 0xC0) | 0x03; - } else { - post_err_msg("[tune_helper] INVALID_CODE_PATH"); - } - - write_ad9361_reg(0x004, reg_inputsel); - - /* Store vcodiv setting. */ - reg_vcodivs = (reg_vcodivs & 0xF0) | (i & 0x0F); - - /* Setup the synthesizer. */ - setup_synth(RX_TYPE, actual_vcorate); - - /* Tune!!!! */ - write_ad9361_reg(0x233, nfrac & 0xFF); - write_ad9361_reg(0x234, (nfrac >> 8) & 0xFF); - write_ad9361_reg(0x235, (nfrac >> 16) & 0xFF); - write_ad9361_reg(0x232, (nint >> 8) & 0xFF); - write_ad9361_reg(0x231, nint & 0xFF); - write_ad9361_reg(0x005, reg_vcodivs); - - /* Lock the PLL! */ - ad9361_msleep(2); - if((read_ad9361_reg(0x247) & 0x02) == 0) { - post_err_msg("RX PLL NOT LOCKED"); - } - - _rx_freq = actual_lo; - - return actual_lo; - - } else { - - _req_tx_freq = value; - - /* Set band-specific settings. */ - if(value < AD9361_TX_BAND_EDGE) { - reg_inputsel = reg_inputsel | 0x40; - } else if((value >= AD9361_TX_BAND_EDGE) && (value <= 6e9)) { - reg_inputsel = reg_inputsel & 0xBF; - } else { - post_err_msg("[tune_helper] INVALID_CODE_PATH"); - } - - write_ad9361_reg(0x004, reg_inputsel); - - /* Store vcodiv setting. */ - reg_vcodivs = (reg_vcodivs & 0x0F) | ((i & 0x0F) << 4); - - /* Setup the synthesizer. */ - setup_synth(TX_TYPE, actual_vcorate); - - /* Tune it, homey. */ - write_ad9361_reg(0x273, nfrac & 0xFF); - write_ad9361_reg(0x274, (nfrac >> 8) & 0xFF); - write_ad9361_reg(0x275, (nfrac >> 16) & 0xFF); - write_ad9361_reg(0x272, (nint >> 8) & 0xFF); - write_ad9361_reg(0x271, nint & 0xFF); - write_ad9361_reg(0x005, reg_vcodivs); - - /* Lock the PLL! */ - ad9361_msleep(2); - if((read_ad9361_reg(0x287) & 0x02) == 0) { - post_err_msg("TX PLL NOT LOCKED"); - } - - _tx_freq = actual_lo; - - return actual_lo; - } -} - -/* Configure the various clock / sample rates in the RX and TX chains. - * - * Functionally, this function configures Catalina's RX and TX rates. For - * a requested TX & RX rate, it sets the interpolation & decimation filters, - * and tunes the VCO that feeds the ADCs and DACs. - */ -double setup_rates(const double rate) { - - /* If we make it into this function, then we are tuning to a new rate. - * Store the new rate. */ - _req_clock_rate = rate; - - /* Set the decimation and interpolation values in the RX and TX chains. - * This also switches filters in / out. Note that all transmitters and - * receivers have to be turned on for the calibration portion of - * bring-up, and then they will be switched out to reflect the actual - * user-requested antenna selections. */ - int divfactor = 0; - _tfir_factor = 0; - if(rate < 0.33e6) { - // RX1 + RX2 enabled, 3, 2, 2, 4 - reg_rxfilt = B8( 11101111 ) ; - - // TX1 + TX2 enabled, 3, 2, 2, 4 - reg_txfilt = B8( 11101111 ) ; - - divfactor = 48; - _tfir_factor = 2; - } else if(rate < 0.66e6) { - // RX1 + RX2 enabled, 2, 2, 2, 4 - reg_rxfilt = B8( 11011111 ) ; - - // TX1 + TX2 enabled, 2, 2, 2, 4 - reg_txfilt = B8( 11011111 ) ; - - divfactor = 32; - _tfir_factor = 2; - } else if(rate <= 20e6) { - // RX1 + RX2 enabled, 2, 2, 2, 2 - reg_rxfilt = B8( 11011110 ) ; - - // TX1 + TX2 enabled, 2, 2, 2, 2 - reg_txfilt = B8( 11011110 ) ; - - divfactor = 16; - _tfir_factor = 2; - } else if((rate > 20e6) && (rate < 23e6)) { - // RX1 + RX2 enabled, 3, 2, 2, 2 - reg_rxfilt = B8( 11101110 ) ; - - // TX1 + TX2 enabled, 3, 1, 2, 2 - reg_txfilt = B8( 11100110 ) ; - - divfactor = 24; - _tfir_factor = 2; - } else if((rate >= 23e6) && (rate < 41e6)) { - // RX1 + RX2 enabled, 2, 2, 2, 2 - reg_rxfilt = B8( 11011110 ) ; - - // TX1 + TX2 enabled, 1, 2, 2, 2 - reg_txfilt = B8( 11001110 ) ; - - divfactor = 16; - _tfir_factor = 2; - } else if((rate >= 41e6) && (rate <= 56e6)) { - // RX1 + RX2 enabled, 3, 1, 2, 2 - reg_rxfilt = B8( 11100110 ) ; - - // TX1 + TX2 enabled, 3, 1, 1, 2 - reg_txfilt = B8( 11100010 ) ; - - divfactor = 12; - _tfir_factor = 2; - } else if((rate > 56e6) && (rate <= 61.44e6)) { - // RX1 + RX2 enabled, 3, 1, 1, 2 - reg_rxfilt = B8( 11100010 ) ; - - // TX1 + TX2 enabled, 3, 1, 1, 1 - reg_txfilt = B8( 11100001 ) ; - - divfactor = 6; - _tfir_factor = 1; - } else { - // should never get in here - post_err_msg("[setup_rates] INVALID_CODE_PATH"); - } - - msg("[setup_rates] divfactor=%d", divfactor); - - /* Tune the BBPLL to get the ADC and DAC clocks. */ - const double adcclk = tune_bbvco(rate * divfactor); - double dacclk = adcclk; - - /* The DAC clock must be <= 336e6, and is either the ADC clock or 1/2 the - * ADC clock.*/ - if(adcclk > 336e6) { - /* Make the DAC clock = ADC/2, and bypass the TXFIR. */ - reg_bbpll = reg_bbpll | 0x08; - dacclk = adcclk / 2.0; - } else { - reg_bbpll = reg_bbpll & 0xF7; - } - - /* Set the dividers / interpolators in Catalina. */ - write_ad9361_reg(0x002, reg_txfilt); - write_ad9361_reg(0x003, reg_rxfilt); - write_ad9361_reg(0x004, reg_inputsel); - write_ad9361_reg(0x00A, reg_bbpll); - - msg("[setup_rates] adcclk=%f", adcclk); - _baseband_bw = (adcclk / divfactor); - - /* Setup the RX and TX FIR filters. Scale the number of taps based on - * the clock speed. */ - const int max_tx_taps = 16 * AD9361_MIN((int)((dacclk / rate) + 0.5), \ - AD9361_MIN(4 * (1 << _tfir_factor), 8)); - const int max_rx_taps = AD9361_MIN((16 * (int)(adcclk / rate)), 128); - - const int num_tx_taps = get_num_taps(max_tx_taps); - const int num_rx_taps = get_num_taps(max_rx_taps); - - setup_tx_fir(num_tx_taps); - setup_rx_fir(num_rx_taps); - - return _baseband_bw; -} - -/*********************************************************************** - * Publicly exported functions to host calls - **********************************************************************/ -void init_ad9361(void) { - - /* Initialize shadow registers. */ - reg_vcodivs = 0x00; - reg_inputsel = 0x30; - reg_rxfilt = 0x00; - reg_txfilt = 0x00; - reg_bbpll = 0x02; - reg_bbftune_config = 0x1e; - reg_bbftune_mode = 0x1e; - - /* Initialize private VRQ fields. */ - _rx_freq = 0.0; - _tx_freq = 0.0; - _req_rx_freq = 0.0; - _req_tx_freq = 0.0; - _baseband_bw = 0.0; - _req_clock_rate = 0.0; - _req_coreclk = 0.0; - _bbpll_freq = 0.0; - _adcclock_freq = 0.0; - _rx_bbf_tunediv = 0; - _curr_gain_table = 0; - _rx1_gain = 0; - _rx2_gain = 0; - _tx1_gain = 0; - _tx2_gain = 0; - - /* Reset the device. */ - write_ad9361_reg(0x000,0x01); - write_ad9361_reg(0x000,0x00); - ad9361_msleep(20); - - /* There is not a WAT big enough for this. */ - write_ad9361_reg(0x3df, 0x01); - - write_ad9361_reg(0x2a6, 0x0e); // Enable master bias - write_ad9361_reg(0x2a8, 0x0e); // Set bandgap trim - - /* Set RFPLL ref clock scale to REFCLK * 2 */ - write_ad9361_reg(0x2ab, 0x07); - write_ad9361_reg(0x2ac, 0xff); - - /* Enable clocks. */ - if (AD9361_CLOCKING_MODE == 0) - { - write_ad9361_reg(0x009, 0x17); - } - if (AD9361_CLOCKING_MODE == 1) - { - write_ad9361_reg(0x009, 0x07); - write_ad9361_reg(0x292, 0x08); - write_ad9361_reg(0x293, 0x80); - write_ad9361_reg(0x294, 0x00); - write_ad9361_reg(0x295, 0x14); - } - ad9361_msleep(20); - - /* Tune the BBPLL, write TX and RX FIRS. */ - setup_rates(50e6); - - /* Setup data ports (FDD dual port DDR CMOS): - * FDD dual port DDR CMOS no swap. - * Force TX on one port, RX on the other. */ - write_ad9361_reg(0x010, 0xc8); - write_ad9361_reg(0x011, 0x00); - write_ad9361_reg(0x012, 0x02); - - /* Data delay for TX and RX data clocks */ - write_ad9361_reg(0x006, 0x0F); - write_ad9361_reg(0x007, 0x0F); - - /* Setup AuxDAC */ - write_ad9361_reg(0x018, 0x00); // AuxDAC1 Word[9:2] - write_ad9361_reg(0x019, 0x00); // AuxDAC2 Word[9:2] - write_ad9361_reg(0x01A, 0x00); // AuxDAC1 Config and Word[1:0] - write_ad9361_reg(0x01B, 0x00); // AuxDAC2 Config and Word[1:0] - write_ad9361_reg(0x023, 0xFF); // AuxDAC Manaul/Auto Control - write_ad9361_reg(0x026, 0x00); // AuxDAC Manual Select Bit/GPO Manual Select - write_ad9361_reg(0x030, 0x00); // AuxDAC1 Rx Delay - write_ad9361_reg(0x031, 0x00); // AuxDAC1 Tx Delay - write_ad9361_reg(0x032, 0x00); // AuxDAC2 Rx Delay - write_ad9361_reg(0x033, 0x00); // AuxDAC2 Tx Delay - - /* Setup AuxADC */ - write_ad9361_reg(0x00B, 0x00); // Temp Sensor Setup (Offset) - write_ad9361_reg(0x00C, 0x00); // Temp Sensor Setup (Temp Window) - write_ad9361_reg(0x00D, 0x03); // Temp Sensor Setup (Periodic Measure) - write_ad9361_reg(0x00F, 0x04); // Temp Sensor Setup (Decimation) - write_ad9361_reg(0x01C, 0x10); // AuxADC Setup (Clock Div) - write_ad9361_reg(0x01D, 0x01); // AuxADC Setup (Decimation/Enable) - - /* Setup control outputs. */ - write_ad9361_reg(0x035, 0x07); - write_ad9361_reg(0x036, 0xFF); - - /* Setup GPO */ - write_ad9361_reg(0x03a, 0x27); //set delay register - write_ad9361_reg(0x020, 0x00); // GPO Auto Enable Setup in RX and TX - write_ad9361_reg(0x027, 0x03); // GPO Manual and GPO auto value in ALERT - write_ad9361_reg(0x028, 0x00); // GPO_0 RX Delay - write_ad9361_reg(0x029, 0x00); // GPO_1 RX Delay - write_ad9361_reg(0x02A, 0x00); // GPO_2 RX Delay - write_ad9361_reg(0x02B, 0x00); // GPO_3 RX Delay - write_ad9361_reg(0x02C, 0x00); // GPO_0 TX Delay - write_ad9361_reg(0x02D, 0x00); // GPO_1 TX Delay - write_ad9361_reg(0x02E, 0x00); // GPO_2 TX Delay - write_ad9361_reg(0x02F, 0x00); // GPO_3 TX Delay - - write_ad9361_reg(0x261, 0x00); // RX LO power - write_ad9361_reg(0x2a1, 0x00); // TX LO power - write_ad9361_reg(0x248, 0x0b); // en RX VCO LDO - write_ad9361_reg(0x288, 0x0b); // en TX VCO LDO - write_ad9361_reg(0x246, 0x02); // pd RX cal Tcf - write_ad9361_reg(0x286, 0x02); // pd TX cal Tcf - write_ad9361_reg(0x249, 0x8e); // rx vco cal length - write_ad9361_reg(0x289, 0x8e); // rx vco cal length - write_ad9361_reg(0x23b, 0x80); // set RX MSB?, FIXME 0x89 magic cp - write_ad9361_reg(0x27b, 0x80); // "" TX //FIXME 0x88 see above - write_ad9361_reg(0x243, 0x0d); // set rx prescaler bias - write_ad9361_reg(0x283, 0x0d); // "" TX - - write_ad9361_reg(0x23d, 0x00); // Clear half VCO cal clock setting - write_ad9361_reg(0x27d, 0x00); // Clear half VCO cal clock setting - - /* The order of the following process is EXTREMELY important. If the - * below functions are modified at all, device initialization and - * calibration might be broken in the process! */ - - write_ad9361_reg(0x015, 0x04); // dual synth mode, synth en ctrl en - write_ad9361_reg(0x014, 0x05); // use SPI for TXNRX ctrl, to ALERT, TX on - write_ad9361_reg(0x013, 0x01); // enable ENSM - ad9361_msleep(1); - - calibrate_synth_charge_pumps(); - - tune_helper(RX_TYPE, 800e6); - tune_helper(TX_TYPE, 850e6); - - program_mixer_gm_subtable(); - program_gain_table(); - setup_gain_control(); - - calibrate_baseband_rx_analog_filter(); - calibrate_baseband_tx_analog_filter(); - calibrate_rx_TIAs(); - calibrate_secondary_tx_filter(); - - setup_adc(); - - calibrate_tx_quadrature(); - calibrate_rx_quadrature(); - - write_ad9361_reg(0x012, 0x02); // cals done, set PPORT config - write_ad9361_reg(0x013, 0x01); // Set ENSM FDD bit - write_ad9361_reg(0x015, 0x04); // dual synth mode, synth en ctrl en - - /* Default TX attentuation to 10dB on both TX1 and TX2 */ - write_ad9361_reg(0x073, 0x00); - write_ad9361_reg(0x074, 0x00); - write_ad9361_reg(0x075, 0x00); - write_ad9361_reg(0x076, 0x00); - - /* Setup RSSI Measurements */ - write_ad9361_reg(0x150, 0x0E); // RSSI Measurement Duration 0, 1 - write_ad9361_reg(0x151, 0x00); // RSSI Measurement Duration 2, 3 - write_ad9361_reg(0x152, 0xFF); // RSSI Weighted Multiplier 0 - write_ad9361_reg(0x153, 0x00); // RSSI Weighted Multiplier 1 - write_ad9361_reg(0x154, 0x00); // RSSI Weighted Multiplier 2 - write_ad9361_reg(0x155, 0x00); // RSSI Weighted Multiplier 3 - write_ad9361_reg(0x156, 0x00); // RSSI Delay - write_ad9361_reg(0x157, 0x00); // RSSI Wait - write_ad9361_reg(0x158, 0x0D); // RSSI Mode Select - write_ad9361_reg(0x15C, 0x67); // Power Measurement Duration - - /* Turn on the default RX & TX chains. */ - set_active_chains(true, false, false, false); - - /* Set TXers & RXers on (only works in FDD mode) */ - write_ad9361_reg(0x014, 0x21); -} - - -/* This function sets the RX / TX rate between Catalina and the FPGA, and - * thus determines the interpolation / decimation required in the FPGA to - * achieve the user's requested rate. - * - * This is the only clock setting function that is exposed to the outside. */ -double set_clock_rate(const double req_rate) { - if(req_rate > 61.44e6) { - post_err_msg("Requested master clock rate outside range"); - } - - msg("[set_clock_rate] req_rate=%.10f", req_rate); - - /* UHD has a habit of requesting the same rate like four times when it - * starts up. This prevents that, and any bugs in user code that request - * the same rate over and over. */ - if(freq_is_nearly_equal(req_rate, _req_clock_rate)) { - return _baseband_bw; - } - - /* We must be in the SLEEP / WAIT state to do this. If we aren't already - * there, transition the ENSM to State 0. */ - uint8_t current_state = read_ad9361_reg(0x017) & 0x0F; - switch(current_state) { - case 0x05: - /* We are in the ALERT state. */ - write_ad9361_reg(0x014, 0x21); - ad9361_msleep(5); - write_ad9361_reg(0x014, 0x00); - break; - - case 0x0A: - /* We are in the FDD state. */ - write_ad9361_reg(0x014, 0x00); - break; - - default: - post_err_msg("[set_clock_rate:1] AD9361 in unknown state"); - break; - }; - - /* Store the current chain / antenna selections so that we can restore - * them at the end of this routine; all chains will be enabled from - * within setup_rates for calibration purposes. */ - uint8_t orig_tx_chains = reg_txfilt & 0xC0; - uint8_t orig_rx_chains = reg_rxfilt & 0xC0; - - /* Call into the clock configuration / settings function. This is where - * all the hard work gets done. */ - double rate = setup_rates(req_rate); - - msg("[set_clock_rate] rate=%.10f", rate); - - /* Transition to the ALERT state and calibrate everything. */ - write_ad9361_reg(0x015, 0x04); //dual synth mode, synth en ctrl en - write_ad9361_reg(0x014, 0x05); //use SPI for TXNRX ctrl, to ALERT, TX on - write_ad9361_reg(0x013, 0x01); //enable ENSM - ad9361_msleep(1); - - calibrate_synth_charge_pumps(); - - tune_helper(RX_TYPE, _rx_freq); - tune_helper(TX_TYPE, _tx_freq); - - program_mixer_gm_subtable(); - program_gain_table(); - setup_gain_control(); - program_gains(); - - calibrate_baseband_rx_analog_filter(); - calibrate_baseband_tx_analog_filter(); - calibrate_rx_TIAs(); - calibrate_secondary_tx_filter(); - - setup_adc(); - - calibrate_tx_quadrature(); - calibrate_rx_quadrature(); - - write_ad9361_reg(0x012, 0x02); // cals done, set PPORT config - write_ad9361_reg(0x013, 0x01); // Set ENSM FDD bit - write_ad9361_reg(0x015, 0x04); // dual synth mode, synth en ctrl en - - /* End the function in the same state as the entry state. */ - switch(current_state) { - case 0x05: - /* We are already in ALERT. */ - break; - - case 0x0A: - /* Transition back to FDD, and restore the original antenna - * / chain selections. */ - reg_txfilt = (reg_txfilt & 0x3F) | orig_tx_chains; - reg_rxfilt = (reg_rxfilt & 0x3F) | orig_rx_chains; - - write_ad9361_reg(0x002, reg_txfilt); - write_ad9361_reg(0x003, reg_rxfilt); - write_ad9361_reg(0x014, 0x21); - break; - - default: - post_err_msg("[set_clock_rate:2] AD9361 in unknown state"); - break; - }; - - return rate; -} - - -/* Set which of the four TX / RX chains provided by Catalina are active. - * - * Catalina provides two sets of chains, Side A and Side B. Each side - * provides one TX antenna, and one RX antenna. The B200 maintains the USRP - * standard of providing one antenna connection that is both TX & RX, and - * one that is RX-only - for each chain. Thus, the possible antenna and - * chain selections are: - * - * B200 Antenna Catalina Side Catalina Chain - * ------------------------------------------------------------------- - * TX / RX1 Side A TX1 (when switched to TX) - * TX / RX1 Side A RX1 (when switched to RX) - * RX1 Side A RX1 - * - * TX / RX2 Side B TX2 (when switched to TX) - * TX / RX2 Side B RX2 (when switched to RX) - * RX2 Side B RX2 - */ -void set_active_chains(bool tx1, bool tx2, bool rx1, bool rx2) { - /* Clear out the current active chain settings. */ - reg_txfilt = reg_txfilt & 0x3F; - reg_rxfilt = reg_rxfilt & 0x3F; - - /* Turn on the different chains based on the passed parameters. */ - if(tx1) { reg_txfilt = reg_txfilt | 0x40; } - if(tx2) { reg_txfilt = reg_txfilt | 0x80; } - if(rx1) { reg_rxfilt = reg_rxfilt | 0x40; } - if(rx2) { reg_rxfilt = reg_rxfilt | 0x80; } - - /* Turn on / off the chains. */ - write_ad9361_reg(0x002, reg_txfilt); - write_ad9361_reg(0x003, reg_rxfilt); -} - -/* Tune the RX or TX frequency. - * - * This is the publicly-accessible tune function. It makes sure the tune - * isn't a redundant request, and if not, passes it on to the class's - * internal tune function. - * - * After tuning, it runs any appropriate calibrations. */ -double tune(int which, const double value) { - - if(which == RX_TYPE) { - if(freq_is_nearly_equal(value, _req_rx_freq)) { - return _rx_freq; - } - - } else if(which == TX_TYPE) { - if(freq_is_nearly_equal(value, _req_tx_freq)) { - return _tx_freq; - } - - } else { - post_err_msg("[tune] INVALID_CODE_PATH"); - } - - /* If we aren't already in the ALERT state, we will need to return to - * the FDD state after tuning. */ - int not_in_alert = 0; - if((read_ad9361_reg(0x017) & 0x0F) != 5) { - /* Force the device into the ALERT state. */ - not_in_alert = 1; - write_ad9361_reg(0x014, 0x01); - } - - /* Tune the RF VCO! */ - double tune_freq = tune_helper(which, value); - - /* Run any necessary calibrations / setups */ - if(which == RX_TYPE) { - program_gain_table(); - } - - /* Update the gain settings. */ - program_gains(); - - /* Run the calibration algorithms. */ - calibrate_tx_quadrature(); - calibrate_rx_quadrature(); - - /* If we were in the FDD state, return it now. */ - if(not_in_alert) { - write_ad9361_reg(0x014, 0x21); - } - - return tune_freq; -} - -/* Set the gain of RX1, RX2, TX1, or TX2. - * - * Note that the 'value' passed to this function is the actual gain value, - * _not_ the gain index. This is the opposite of the eval software's GUI! - * Also note that the RX chains are done in terms of gain, and the TX chains - * are done in terms of attenuation. */ -double set_gain(int which, int n, const double value) { - - if(which == RX_TYPE) { - /* Indexing the gain tables requires an offset from the requested - * amount of total gain in dB: - * < 1300MHz: dB + 5 - * >= 1300MHz and < 4000MHz: dB + 3 - * >= 4000MHz and <= 6000MHz: dB + 14 - */ - int gain_offset = 0; - if(_rx_freq < 1300e6) { - gain_offset = 5; - } else if(_rx_freq < 4000e6) { - gain_offset = 3; - } else { - gain_offset = 14; - } - - int gain_index = value + gain_offset; - - /* Clip the gain values to the proper min/max gain values. */ - if(gain_index > 76) gain_index = 76; - if(gain_index < 0) gain_index = 0; - - if(n == 1) { - _rx1_gain = value; - write_ad9361_reg(0x109, gain_index); - } else { - _rx2_gain = value; - write_ad9361_reg(0x10c, gain_index); - } - - return gain_index - gain_offset; - } else { - /* Setting the below bits causes a change in the TX attenuation word - * to immediately take effect. */ - write_ad9361_reg(0x077, 0x40); - write_ad9361_reg(0x07c, 0x40); - - /* Each gain step is -0.25dB. Calculate the attenuation necessary - * for the requested gain, convert it into gain steps, then write - * the attenuation word. Max gain (so zero attenuation) is 89.75. */ - double atten = AD9361_MAX_GAIN - value; - int attenreg = atten * 4; - if(n == 1) { - _tx1_gain = value; - write_ad9361_reg(0x073, attenreg & 0xFF); - write_ad9361_reg(0x074, (attenreg >> 8) & 0x01); - } else { - _tx2_gain = value; - write_ad9361_reg(0x075, attenreg & 0xFF); - write_ad9361_reg(0x076, (attenreg >> 8) & 0x01); - } - return AD9361_MAX_GAIN - ((double)(attenreg)/ 4); - } -} - -/* This function is responsible to dispatch the vendor request call - * to the proper handler - */ -void ad9361_dispatch(const char* vrb, char* vrb_out) { - memcpy(vrb_out, vrb, AD9361_DISPATCH_PACKET_SIZE); // Copy request to response memory - tmp_req_buffer = vrb_out; // Set this to enable 'post_err_msg' - - ////////////////////////////////////////////// - - double ret_val = 0.0; - int mask = 0; - - const ad9361_transaction_t *request = (const ad9361_transaction_t *)vrb; - ad9361_transaction_t *response = (ad9361_transaction_t *)vrb_out; - response->error_msg[0] = '\0'; // Ensure error is cleared - - //msg("[ad9361_dispatch] action=%d", request->action); - - switch (request->action) { - case AD9361_ACTION_ECHO: - break; // nothing to do - case AD9361_ACTION_INIT: - init_ad9361(); - break; - case AD9361_ACTION_SET_RX1_GAIN: - ret_val = set_gain(RX_TYPE,1,double_unpack(request->value.gain)); - double_pack(ret_val, response->value.gain); - break; - case AD9361_ACTION_SET_TX1_GAIN: - ret_val = set_gain(TX_TYPE,1,double_unpack(request->value.gain)); - double_pack(ret_val, response->value.gain); - break; - case AD9361_ACTION_SET_RX2_GAIN: - ret_val = set_gain(RX_TYPE,2,double_unpack(request->value.gain)); - double_pack(ret_val, response->value.gain); - break; - case AD9361_ACTION_SET_TX2_GAIN: - ret_val = set_gain(TX_TYPE,2,double_unpack(request->value.gain)); - double_pack(ret_val, response->value.gain); - break; - case AD9361_ACTION_SET_RX_FREQ: - ret_val = tune(RX_TYPE, double_unpack(request->value.freq)); - double_pack(ret_val, response->value.freq); - break; - case AD9361_ACTION_SET_TX_FREQ: - ret_val = tune(TX_TYPE, double_unpack(request->value.freq)); - double_pack(ret_val, response->value.freq); - break; - case AD9361_ACTION_SET_CODEC_LOOP: - data_port_loopback(request->value.codec_loop != 0); - break; - case AD9361_ACTION_SET_CLOCK_RATE: - ret_val = set_clock_rate(double_unpack(request->value.rate)); - double_pack(ret_val, response->value.rate); - break; - case AD9361_ACTION_SET_ACTIVE_CHAINS: - mask = request->value.enable_mask; - set_active_chains(mask & 1, mask & 2, mask & 4, mask & 8); - break; - default: - post_err_msg("[ad9361_dispatch] NOT IMPLEMENTED"); - break; - } -} diff --git a/firmware/fx3/b200/b200_ad9361.c b/firmware/fx3/b200/b200_ad9361.c deleted file mode 100644 index ebb0dda70..000000000 --- a/firmware/fx3/b200/b200_ad9361.c +++ /dev/null @@ -1,57 +0,0 @@ -// -// Copyright 2013-2014 Ettus Research LLC -// - -#include "cyu3error.h" -#include "cyu3i2c.h" -#include "cyu3spi.h" -#include "cyu3os.h" -#include "cyu3pib.h" -#include "cyu3system.h" -#include "cyu3usb.h" -#include "cyu3utils.h" -#include "pib_regs.h" -#include "b200_vrq.h" -#include <stdint.h> - -#define true CyTrue -#define false CyFalse - -typedef CyBool_t bool; - -/* Fast sqrt() - precision can be improved by increasing - * the number of iterations - */ -float ad9361_sqrt(const float number) -{ - uint32_t i; - float x2, y; - - x2 = number * 0.5F; - y = number; - i = *(uint32_t *) &y; - i = 0x5f3759df - ( i >> 1 ); - y = *(float *) &i; - y = y * (1.5F - (x2 * y * y)); - - return number * y; -} - -void ad9361_msleep(const unsigned millis) -{ - CyU3PThreadSleep(millis); -} - -#define AD9361_MIN(a, b) CY_U3P_MIN(a, b) -#define AD9361_MAX(a, b) CY_U3P_MAX(a, b) - -#define AD9361_CEIL_INT(a) ((int)(a+1)) -#define AD9361_FLOOR_INT(a) ((int)(a)) - -#define AD9361_CLOCKING_MODE 0 - -#define AD9361_RX_BAND_EDGE0 2.2e9 -#define AD9361_RX_BAND_EDGE1 4e9 -#define AD9361_TX_BAND_EDGE 2.5e9 - -#include "../ad9361/lib/ad9361_impl.c" diff --git a/firmware/fx3/b200/b200_main.c b/firmware/fx3/b200/b200_main.c index 38af9ed4e..077ee251b 100644 --- a/firmware/fx3/b200/b200_main.c +++ b/firmware/fx3/b200/b200_main.c @@ -12,7 +12,6 @@ #include "b200_main.h" #include "b200_gpifconfig.h" -#include "b200_vrq.h" #include "b200_i2c.h" #include "cyu3dma.h" @@ -28,9 +27,6 @@ #include "cyfxversion.h" #include "pib_regs.h" -#include <ad9361_transaction.h> -#include <ad9361_dispatch.h> - #define STATIC_SAVER static // Save stack space for variables in a non-re-entrant function (e.g. USB setup callback) /* @@ -40,7 +36,6 @@ //#define HAS_HEAP // This requires memory to be set aside for the heap (e.g. required for printing floating-point numbers). You can apply the accompanying patch ('fx3_mem_map.patch') to fx3.ld & cyfxtx.c to create one. //#define ENABLE_MSG // This will cause the compiled code to exceed the default text memory area (SYS_MEM). You can apply the accompanying patch ('fx3_mem_map.patch') to fx3.ld & cyfxtx.c to resize the memory map so it will fit. -//#define ENABLE_AD9361_LOGGING // When enabling this, you *must* enable the heap with HAS_HEAP (and apply the accompanying memory map patch 'fx3_mem_map.patch') otherwise the FW will crash when printing a floating-point number (as there is no heap for _sbrk by default) //#define ENABLE_MANUAL_DMA_XFER //#define ENABLE_MANUAL_DMA_XFER_FROM_HOST //#define ENABLE_MANUAL_DMA_XFER_TO_HOST @@ -69,13 +64,6 @@ #ifdef ENABLE_MSG #pragma message "msg enabled" - -#ifdef ENABLE_AD9361_LOGGING -#pragma message " AD9361 logging enabled" -#else -#pragma message " AD9361 logging disabled" -#endif // ENABLE_AD9361_LOGGING - #else #pragma message "msg disabled" #endif // ENABLE_MSG @@ -156,21 +144,15 @@ static CyU3PThread thread_fpga_config; #ifdef ENABLE_RE_ENUM_THREAD static CyU3PThread thread_re_enum; #endif // ENABLE_RE_ENUM_THREAD -static CyU3PThread thread_ad9361; static CyBool_t g_app_running = CyFalse; static uint8_t g_fx3_state = STATE_UNDEFINED; -//#define AD9361_DISPATCH_PACKET_SIZE 64 // Must fit into smallest VREQ #define USB2_VREQ_BUF_SIZE 64 #define USB3_VREQ_BUF_SIZE 512 #define MIN_VREQ_BUF_SIZE USB2_VREQ_BUF_SIZE #define MAX_VREQ_BUF_SIZE USB3_VREQ_BUF_SIZE -#if AD9361_DISPATCH_PACKET_SIZE > MIN_VREQ_BUF_SIZE -#error "AD9361_DISPATCH_PACKET_SIZE must be less than MIN_VREQ_BUF_SIZE" -#endif - static uint16_t g_vendor_req_buff_size = MIN_VREQ_BUF_SIZE; static uint8_t g_vendor_req_buffer[MAX_VREQ_BUF_SIZE] __attribute__ ((aligned (32))); static uint16_t g_vendor_req_read_count = 0; @@ -180,8 +162,6 @@ static uint8_t fw_hash[4] __attribute__ ((aligned (32))); static uint8_t compat_num[2]; static uint32_t g_fpga_programming_write_count = 0; -static char g_ad9361_response[AD9361_DISPATCH_PACKET_SIZE]; - #define COUNTER_MAGIC 0x10024001 #define LOG_BUFFER_SIZE /*MAX_VREQ_BUF_SIZE*/1024 // [Max vreq @ USB3 (64 @ USB2)] Can be larger static char log_buffer[LOG_BUFFER_SIZE]; @@ -685,214 +665,6 @@ void gpio_interrupt_callback(uint8_t gpio_id) { } -// The following two functions are intended to replace write_spi_to_ad9361 -// and read_spi_from_ad9361 after the code porting is complete -/*! Perform a register write to the ad9361 chip. - * A pointer to the register address followed by data will be provided as - * parameter - */ -static void write_ad9361_reg(uint16_t reg, uint8_t val) { - - CyBool_t gpio_value; - uint8_t write_buff[3]; - MAKE_AD9361_WRITE(write_buff, reg, val) - - // Number of bytes we are writing. - uint8_t num_bytes = 3; //register address = 2 bytes, data = 1 byte - - CyU3PGpioSetValue(GPIO_FX3_CE, 0); - - // Clock the data out to AD9361 over SPI. - int8_t bit_count, byte_count; - for(byte_count = 0; byte_count < num_bytes; byte_count++) { - - uint8_t miso = 0x00; - uint8_t data = write_buff[byte_count]; - - for(bit_count = 7; bit_count >= 0; bit_count--) { - CyU3PGpioSetValue(GPIO_FX3_SCLK, 1); - CyU3PGpioSetValue(GPIO_FX3_MOSI, ((data >> bit_count) & 0x01)); - CyU3PGpioSetValue(GPIO_FX3_SCLK, 0); - - CyU3PGpioGetValue(GPIO_FX3_MISO, &gpio_value); - if(gpio_value) { - miso |= (1 << bit_count); - } - } - // FIXME: Determine what to do with miso value; - } - - CyU3PGpioSetValue(GPIO_FX3_MOSI, 0); - CyU3PGpioSetValue(GPIO_FX3_CE, 1); -} - -/*! Perform a register read from to the ad9361 chip. - * A pointer to register address will be provided as parameter - * The function returns the value read from the register - */ -static uint8_t read_ad9361_reg(uint16_t reg) { - - CyBool_t gpio_value; - uint8_t write_buff[2]; - MAKE_AD9361_READ(write_buff, reg) - - // Each 9361 register read returns 1 byte - - CyU3PGpioSetValue(GPIO_FX3_CE, 0); - - // Write the two register address bytes. - int8_t bit_count, byte_count; - for(byte_count = 0; byte_count < 2; byte_count++) { - - uint8_t miso = 0x00; - uint8_t data = write_buff[byte_count]; - - for(bit_count = 7; bit_count >= 0; bit_count--) { - CyU3PGpioSetValue(GPIO_FX3_SCLK, 1); - CyU3PGpioSetValue(GPIO_FX3_MOSI, ((data >> bit_count) & 0x01)); - CyU3PGpioSetValue(GPIO_FX3_SCLK, 0); - - CyU3PGpioGetValue(GPIO_FX3_MISO, &gpio_value); - if(gpio_value) { - miso |= (1 << bit_count); - } - } - // FIXME: Determine what to do with miso value; - } - - CyU3PGpioSetValue(GPIO_FX3_MOSI, 0); - - // Read the response data from the chip. - uint8_t data = 0x00; - - for(bit_count = 7; bit_count >= 0; bit_count--) { - CyU3PGpioSetValue(GPIO_FX3_SCLK, 1); - - CyU3PGpioGetValue(GPIO_FX3_MISO, &gpio_value); - if(gpio_value) { - data |= (1 << bit_count); - } - - CyU3PGpioSetValue(GPIO_FX3_SCLK, 0); - } - CyU3PGpioSetValue(GPIO_FX3_CE, 1); - return data; -} - -/*! Perform a register write to the ad9361 chip. - * - * This function will take data received over EP0, as a vendor request, and - * perform a SPI write to ad9361. This requires that the FPGA be passing these - * SPI lines through to the ad9361 chip. */ -void write_spi_to_ad9361(void) { - - CyBool_t gpio_value; - - /* Pull out the number of bytes we are writing. */ - uint8_t num_bytes = ((g_vendor_req_buffer[0] & 0x70) >> 4) + 1; - - CyU3PGpioSetValue(GPIO_FX3_CE, 0); - - /* Clock the data out to AD9361 over SPI. */ - int8_t bit_count, byte_count; - for(byte_count = 0; byte_count < (num_bytes + 2); byte_count++) { - - uint8_t miso = 0x00; - uint8_t data = g_vendor_req_buffer[byte_count]; - - for(bit_count = 7; bit_count >= 0; bit_count--) { - CyU3PGpioSetValue(GPIO_FX3_SCLK, 1); - CyU3PGpioSetValue(GPIO_FX3_MOSI, ((data >> bit_count) & 0x01)); - CyU3PGpioSetValue(GPIO_FX3_SCLK, 0); - - CyU3PGpioGetValue(GPIO_FX3_MISO, &gpio_value); - if(gpio_value) { - miso |= (1 << bit_count); - } - } - - g_vendor_req_buffer[byte_count] = miso; - } - - CyU3PGpioSetValue(GPIO_FX3_MOSI, 0); - CyU3PGpioSetValue(GPIO_FX3_CE, 1); -} - - -/*! Perform a register read from the ad9361 chip. - * - * This function will write a command to the ad9361 chip, performing a register - * read, and store the returned data in the vendor request buffer. This data can - * then be retrieved with another vendor request from the host. - * - * This requires that the FPGA be passing these SPI lines through to the - * ad9361 chip. */ -void read_spi_from_ad9361(void) { - - CyBool_t gpio_value; - - /* Pull out the number of bytes we are reading. */ - uint8_t num_bytes = ((g_vendor_req_buffer[0] & 0x70) >> 4) + 1; - - CyU3PGpioSetValue(GPIO_FX3_CE, 0); - - /* Write the two instruction bytes. */ - int8_t bit_count, byte_count; - for(byte_count = 0; byte_count < 2; byte_count++) { - - uint8_t miso = 0x00; - uint8_t data = g_vendor_req_buffer[byte_count]; - - for(bit_count = 7; bit_count >= 0; bit_count--) { - CyU3PGpioSetValue(GPIO_FX3_SCLK, 1); - CyU3PGpioSetValue(GPIO_FX3_MOSI, ((data >> bit_count) & 0x01)); - CyU3PGpioSetValue(GPIO_FX3_SCLK, 0); - - CyU3PGpioGetValue(GPIO_FX3_MISO, &gpio_value); - if(gpio_value) { - miso |= (1 << bit_count); - } - } - - g_vendor_req_buffer[byte_count] = miso; - } - - CyU3PGpioSetValue(GPIO_FX3_MOSI, 0); - - /* Read the response data from the chip. */ - for(byte_count = 0; byte_count < num_bytes; byte_count++) { - - uint8_t data = 0x00; - - for(bit_count = 7; bit_count >= 0; bit_count--) { - CyU3PGpioSetValue(GPIO_FX3_SCLK, 1); - - CyU3PGpioGetValue(GPIO_FX3_MISO, &gpio_value); - if(gpio_value) { - data |= (1 << bit_count); - } - - CyU3PGpioSetValue(GPIO_FX3_SCLK, 0); - } - - g_vendor_req_buffer[byte_count + 2] = data; - } - - CyU3PGpioSetValue(GPIO_FX3_CE, 1); -} - - -uint32_t ad9361_transact_spi(const uint32_t bits) { - // FIXME: Could make this more sane - if ((bits >> 23) & 0x1) - { - write_ad9361_reg(bits >> 8, bits & 0xff); - return 0; - } - return read_ad9361_reg(bits >> 8); -} - - /*! Stops the application, and destroys transport data structures. * * This function is essentially a destructor for all transport configurations. @@ -1891,22 +1663,6 @@ CyBool_t usb_setup_callback(uint32_t data0, uint32_t data1) { break; } - case B200_VREQ_SPI_WRITE_AD9361: { - CyU3PUsbGetEP0Data(g_vendor_req_buff_size, g_vendor_req_buffer, \ - &read_count); - - write_spi_to_ad9361(); // FIXME: Should have g_vendor_req_buffer & read_count passed in as args - break; - } - - case B200_VREQ_SPI_READ_AD9361: { - CyU3PUsbGetEP0Data(g_vendor_req_buff_size, g_vendor_req_buffer, \ - &read_count); - - read_spi_from_ad9361(); // FIXME: Should have g_vendor_req_buffer & read_count passed in as args - break; - } - case B200_VREQ_LOOP_CODE: { CyU3PUsbSendEP0Data(g_vendor_req_buff_size, g_vendor_req_buffer); break; @@ -2152,55 +1908,6 @@ CyBool_t usb_setup_callback(uint32_t data0, uint32_t data1) { break; } - case B200_VREQ_AD9361_CTRL_READ: { - CyU3PUsbSendEP0Data(g_vendor_req_buff_size, g_vendor_req_buffer); - /* - * This is where vrb gets sent back to the host - */ - break; - } - - case B200_VREQ_AD9361_CTRL_WRITE: { - CyU3PUsbGetEP0Data(g_vendor_req_buff_size, g_vendor_req_buffer, &read_count); - CyU3PEventSet(&g_event_usb_config, EVENT_AD9361_XACT_INIT, CYU3P_EVENT_OR); - - uint32_t event_flag; - CyU3PEventGet(&g_event_usb_config, EVENT_AD9361_XACT_DONE, CYU3P_EVENT_AND_CLEAR, &event_flag, CYU3P_WAIT_FOREVER); - - memcpy(g_vendor_req_buffer, g_ad9361_response, AD9361_DISPATCH_PACKET_SIZE); - break; - } - - case B200_VREQ_AD9361_LOOPBACK: { - CyU3PUsbGetEP0Data(g_vendor_req_buff_size, g_vendor_req_buffer, &read_count); - - if (read_count > 0) { - ad9361_transaction_t xact; - memset(&xact, 0x00, sizeof(xact)); - - xact.version = AD9361_TRANSACTION_VERSION; - xact.action = AD9361_ACTION_SET_CODEC_LOOP; - xact.sequence = 0; - xact.value.codec_loop = g_vendor_req_buffer[0]; - - memcpy(g_vendor_req_buffer, &xact, sizeof(xact)); - - CyU3PEventSet(&g_event_usb_config, EVENT_AD9361_XACT_INIT, CYU3P_EVENT_OR); - - uint32_t event_flag; - CyU3PEventGet(&g_event_usb_config, EVENT_AD9361_XACT_DONE, CYU3P_EVENT_AND_CLEAR, &event_flag, CYU3P_WAIT_FOREVER); - - memcpy(g_vendor_req_buffer, g_ad9361_response, AD9361_DISPATCH_PACKET_SIZE); - - if (xact.value.codec_loop) - msg("Codec loopback ON"); - else - msg("Codec loopback OFF"); - } - - break; - } - default: msg("! Unknown VREQ %02X", (uint32_t)bRequest); handled = CyFalse; @@ -2684,23 +2391,6 @@ void thread_main_app_entry(uint32_t input) { } } - -void thread_ad9361_entry(uint32_t input) { - uint32_t event_flag; - - //msg("thread_ad9361_entry"); - - while (1) { - if (CyU3PEventGet(&g_event_usb_config, \ - EVENT_AD9361_XACT_INIT, CYU3P_EVENT_AND_CLEAR, \ - &event_flag, CYU3P_WAIT_FOREVER) == CY_U3P_SUCCESS) { - ad9361_dispatch((const char*)g_vendor_req_buffer, g_ad9361_response); - - CyU3PEventSet(&g_event_usb_config, EVENT_AD9361_XACT_DONE, CYU3P_EVENT_OR); - } - } -} - static uint16_t g_poll_last_phy_error_count = 0, g_poll_last_link_error_count = 0; static uint32_t g_poll_last_phy_error_status = 0; @@ -2966,7 +2656,7 @@ void thread_fpga_sb_poll_entry(uint32_t input) { * If thread creation fails, lock the system and force a power reset. */ void CyFxApplicationDefine(void) { - void *app_thread_ptr, *fpga_thread_ptr, *ad9361_thread_ptr; + void *app_thread_ptr, *fpga_thread_ptr; #ifdef ENABLE_RE_ENUM_THREAD void *re_enum_thread_ptr; #endif // ENABLE_RE_ENUM_THREAD @@ -2975,9 +2665,6 @@ void CyFxApplicationDefine(void) { #endif // ENABLE_FPGA_SB g_counters.magic = COUNTER_MAGIC; -#ifdef ENABLE_AD9361_LOGGING - ad9361_set_msgfn(msg); -#endif // ENABLE_AD9361_LOGGING memset(&g_config, 0xFF, sizeof(g_config)); // Initialise to -1 CyU3PMutexCreate(&g_log_lock, CYU3P_NO_INHERIT); @@ -3032,7 +2719,6 @@ void CyFxApplicationDefine(void) { #ifdef ENABLE_RE_ENUM_THREAD re_enum_thread_ptr = CyU3PMemAlloc(APP_THREAD_STACK_SIZE); #endif // ENABLE_RE_ENUM_THREAD - ad9361_thread_ptr = CyU3PMemAlloc(APP_THREAD_STACK_SIZE); #ifdef ENABLE_FPGA_SB fpga_sb_poll_thread_ptr = CyU3PMemAlloc(APP_THREAD_STACK_SIZE); #endif // ENABLE_FPGA_SB @@ -3077,18 +2763,6 @@ void CyFxApplicationDefine(void) { CYU3P_NO_TIME_SLICE, CYU3P_AUTO_START); #endif // ENABLE_RE_ENUM_THREAD - /* Create thread to handle AD9361 transactions */ - if (ad9361_thread_ptr != NULL) - CyU3PThreadCreate(&thread_ad9361, - "500:B200 AD9361", - thread_ad9361_entry, - 0, - ad9361_thread_ptr, - APP_THREAD_STACK_SIZE, - THREAD_PRIORITY, - THREAD_PRIORITY, - CYU3P_NO_TIME_SLICE, - CYU3P_AUTO_START); #ifdef ENABLE_FPGA_SB /* Create thread to handling Settings Bus logging/transactions */ if (fpga_sb_poll_thread_ptr != NULL) diff --git a/firmware/fx3/b200/b200_main.h b/firmware/fx3/b200/b200_main.h index 7971c1625..1fdb74801 100644 --- a/firmware/fx3/b200/b200_main.h +++ b/firmware/fx3/b200/b200_main.h @@ -10,7 +10,7 @@ #include "cyu3types.h" #include "cyu3usbconst.h" -#define FX3_COMPAT_MAJOR (uint8_t)(4) +#define FX3_COMPAT_MAJOR (uint8_t)(6) #define FX3_COMPAT_MINOR (uint8_t)(0) /* GPIO Pins */ @@ -67,16 +67,11 @@ #define B200_VREQ_WRITE_SB (uint8_t)(0x29) #define B200_VREQ_SET_SB_BAUD_DIV (uint8_t)(0x30) #define B200_VREQ_FLUSH_DATA_EPS (uint8_t)(0x31) -#define B200_VREQ_SPI_WRITE_AD9361 (uint8_t)(0x32) -#define B200_VREQ_SPI_READ_AD9361 (uint8_t)(0x42) #define B200_VREQ_FPGA_CONFIG (uint8_t)(0x55) #define B200_VREQ_TOGGLE_FPGA_RESET (uint8_t)(0x62) #define B200_VREQ_TOGGLE_GPIF_RESET (uint8_t)(0x72) #define B200_VREQ_GET_USB_SPEED (uint8_t)(0x80) #define B200_VREQ_GET_STATUS (uint8_t)(0x83) -#define B200_VREQ_AD9361_CTRL_WRITE (uint8_t)(0x90) -#define B200_VREQ_AD9361_CTRL_READ (uint8_t)(0x91) -#define B200_VREQ_AD9361_LOOPBACK (uint8_t)(0x92) #define B200_VREQ_RESET_DEVICE (uint8_t)(0x99) #define B200_VREQ_EEPROM_WRITE (uint8_t)(0xBA) #define B200_VREQ_EEPROM_READ (uint8_t)(0xBB) @@ -86,8 +81,6 @@ #define EVENT_GPIO_INITB_RISE (1 << 3) #define EVENT_FPGA_CONFIG (1 << 4) #define EVENT_RE_ENUM (1 << 5) -#define EVENT_AD9361_XACT_INIT (1 << 6) -#define EVENT_AD9361_XACT_DONE (1 << 7) /* FX3 States */ diff --git a/firmware/fx3/b200/b200_vrq.h b/firmware/fx3/b200/b200_vrq.h deleted file mode 100644 index d1f79f0ad..000000000 --- a/firmware/fx3/b200/b200_vrq.h +++ /dev/null @@ -1,21 +0,0 @@ -// -// Copyright 2013-2014 Ettus Research LLC -// - -/* This file defines b200 vendor requests handlers, version 1 - */ -#ifndef B200_VRQ_H -#define B200_VRQ_H - -uint32_t ad9361_transact_spi(const uint32_t bits); - -// note: for a write instruction bit 7 from byte 0 is set to 1 -#define MAKE_AD9361_WRITE(dest, reg, val) {dest[0] = 0x80 | ((reg >> 8) & 0x3F); \ - dest[1] = reg & 0xFF; \ - dest[2] = val;} -#define MAKE_AD9361_READ(dest, reg) {dest[0] = (reg >> 8) & 0x3F; \ - dest[1] = reg & 0xFF;} - -#endif //B200_VRQ_H - - diff --git a/firmware/fx3/b200/makefile b/firmware/fx3/b200/makefile index d693db076..22eb1bbcc 100644 --- a/firmware/fx3/b200/makefile +++ b/firmware/fx3/b200/makefile @@ -19,13 +19,9 @@ MODULE = b200_main SOURCE += $(MODULE).c SOURCE += b200_usb_descriptors.c -SOURCE += b200_ad9361.c SOURCE += b200_i2c.c -INCLUDES = b200_main.h b200_vrq.h b200_gpifconfig.h b200_i2c.h -INCLUDES += ../ad9361/include/ad9361_transaction.h - -INCFLAGS = -I ../ad9361/include +INCLUDES = b200_main.h b200_gpifconfig.h b200_i2c.h LDLIBS += \ "$$ARMGCC_INSTALL_PATH"/arm-none-eabi/lib/libm.a diff --git a/firmware/octoclock/.gitignore b/firmware/octoclock/.gitignore new file mode 100644 index 000000000..d6e09dedb --- /dev/null +++ b/firmware/octoclock/.gitignore @@ -0,0 +1,4 @@ +build +*.o +*.elf +*.hex diff --git a/firmware/octoclock/CMakeLists.txt b/firmware/octoclock/CMakeLists.txt new file mode 100644 index 000000000..80df0e9eb --- /dev/null +++ b/firmware/octoclock/CMakeLists.txt @@ -0,0 +1,45 @@ +# +# Copyright 2014 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +cmake_minimum_required(VERSION 2.6) +set(CMAKE_SYSTEM_NAME Generic) + +find_program(AVR_CC avr-gcc REQUIRED) +find_program(AVR_OBJCOPY avr-objcopy REQUIRED) +find_program(AVRDUDE avrdude REQUIRED) +set(CMAKE_C_COMPILER ${AVR_CC}) + +project(OCTOCLOCK C) +set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -mmcu=atmega128 -std=gnu99") + +if(NOT DEFINED PROGRAMMER) + SET(PROGRAMMER "avrisp2") +endif(NOT DEFINED PROGRAMMER) + +if(OCTOCLOCK_DEBUG) + message(STATUS "Debug enabled. Interrupts will be disabled.") + add_definitions(-DDEBUG) +endif(OCTOCLOCK_DEBUG) + +include_directories( + ${CMAKE_SOURCE_DIR}/include + ${CMAKE_SOURCE_DIR}/../../host/lib/usrp_clock +) + +add_subdirectory(bootloader) +add_subdirectory(lib) +add_subdirectory(octoclock_r4) diff --git a/firmware/octoclock/Makefile b/firmware/octoclock/Makefile deleted file mode 100644 index acf26f617..000000000 --- a/firmware/octoclock/Makefile +++ /dev/null @@ -1,68 +0,0 @@ -# -# Copyright 2009 Ettus Research LLC -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see <http://www.gnu.org/licenses/>. -# - -################################################## -# Compiler -################################################## -CC = avr-gcc -OBJCOPY = avr-objcopy -STRIP = avr-strip -OBJDUMP = avr-objdump -SREC = srec_cat -#CFLAGS = -O2 -std=gnu99 -fshort-enums -pedantic-errors -Wall -Werror \ -# -Wstrict-prototypes -Wmissing-prototypes -Wcast-align -Wshadow -CFLAGS = -std=gnu99 -O2 - -#-D IO_DEBUG - -################################################## -# Files -################################################## -SRCS = OctoClock.c -TARGET = octoclock_fw - -################################################## -# Device -################################################## -MMCU = atmega128 -PROGRAMMER = avrisp2 -PORT = usb -AVRDUDE = avrdude -p $(MMCU) -c $(PROGRAMMER) -P $(PORT) - -################################################## -# Global Targets -################################################## -all: $(TARGET).hex - -clean: - $(RM) *.o *.elf *.hex - -install: all - $(AVRDUDE) -U efuse:w:0xFF:m -U hfuse:w:0x89:m -U lfuse:w:0xFF:m -U flash:w:$(TARGET).hex:i - -################################################## -# Dependency Targets -################################################## - -$(TARGET).hex: $(TARGET).elf - $(OBJCOPY) -O ihex $< $@ - -$(TARGET).elf: $(SRCS:.c=.o) - $(CC) -mmcu=$(MMCU) $^ -o $@ - -%.o: %.c Makefile - $(CC) -mmcu=$(MMCU) -c $< -o $@ $(CFLAGS) diff --git a/firmware/octoclock/OctoClock.c b/firmware/octoclock/OctoClock.c deleted file mode 100644 index f73c30885..000000000 --- a/firmware/octoclock/OctoClock.c +++ /dev/null @@ -1,589 +0,0 @@ -/* - * Copyright 2013 Ettus Research LLC - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -/* - * Welcome to the firmware code for the USRP Octoclock accessory product! - * - * Notes regarding this firmware: - * NOT in M103 compatibility mode - * no WDT - * CKOPT full rail-to-rail - * xtal osc - * 16K CK (16K clock cycles) - * additional delay 65ms for Crystal Oscillator - * slowly rising power - * - * These settings are very conservative. If a lower power oscillator is - * required, change CKOPT to '1' (UNPROGRAMMED). - * - * M103C = [ ] - * WDTON = [ ] - * OCDEN = [ ] - * JTAGEN = [X] - * SPIEN = [X] - * EESAVE = [ ] - * BOOTSZ = 4096W_F000 - * BOOTRST = [ ] - * CKOPT = [X] - * BODLEVEL = 2V7 - * BODEN = [ ] - * SUT_CKSEL = EXTHIFXTALRES_16KCK_64MS - * - * EXTENDED = 0xFF (valid) - * HIGH = 0x89 (valid) - * LOW = 0xFF (valid) - * - */ - -#include <stdint.h> -#include <stdbool.h> -#include <avr/io.h> -#include <avr/interrupt.h> - -#ifdef On -#undef On -#endif - -#ifdef Off -#undef Off -#endif - -#define Off (0) -#define On (!Off) - -#ifdef FALSE -#undef FALSE -#endif - -#ifdef TRUE -#undef TRUE -#endif - -#define FALSE (0) -#define TRUE (!FALSE) - - -// Important for the Serial Port, not used at the moment -#define FOSC (7372800) -#define BAUD (115200) - -#define MYUBRR FOSC/16/BAUD-1 - -#define wait() for(uint16_t u=14000; u; u--) asm("nop"); - -#define CLK (PA0) // Shift by 0 bits -#define CE_ (PA1) // Is really the "Chip Disable" signal, as Hi disables SPI -#define MOSI (PA2) -#define MISO (PA3) -#define PD_ (PA4) -#define SYNC_ (PA5) - -// Top is 0, Mid is 1, and Bottom is 2 -enum LEDs {Top, Middle, Bottom}; - -enum TI_Input_10_MHz {Primary_GPS, Secondary_Ext}; - -enum Levels {Lo, Hi}; - -void led(enum LEDs which, int turn_it_on) { - - // selects the proper bit - uint8_t LED = 0x20 << which; - - if(turn_it_on) - PORTC |= LED; - else - PORTC &= ~LED; -} - -/******************************************************************************* -* SPI routines -*******************************************************************************/ - -/* All macros evaluate to compile-time constants */ - - -/* turn a numeric literal into a hex constant - * (avoids problems with leading zeros) - * 8-bit constants max value 0x11111111, always fits in unsigned long - */ -#define HEX__(n) 0x##n##LU - -/* 8-bit conversion function */ -#define B8__(x) ((x&0x0000000FLU)?1:0) \ - +((x&0x000000F0LU)?2:0) \ - +((x&0x00000F00LU)?4:0) \ - +((x&0x0000F000LU)?8:0) \ - +((x&0x000F0000LU)?16:0) \ - +((x&0x00F00000LU)?32:0) \ - +((x&0x0F000000LU)?64:0) \ - +((x&0xF0000000LU)?128:0) - -/* for up to 8-bit binary constants */ -#define Bits_8(d) ((unsigned char)B8__(HEX__(d))) - -/* for up to 16-bit binary constants, MSB first */ -#define Bits_16(dmsb,dlsb) (((unsigned short)Bits_8(dmsb)<<8) \ - + Bits_8(dlsb)) - -/* for up to 32-bit binary constants, MSB first */ -#define Bits_32(dmsb,db2,db3,dlsb) (((unsigned long)Bits_8(dmsb)<<24) \ - + ((unsigned long)Bits_8(db2)<<16) \ - + ((unsigned long)Bits_8(db3)<<8) \ - + Bits_8(dlsb)) - -/* Sample usage: - * Bits_8(01010101) = 85 - * Bits_16(10101010,01010101) = 43605 - * Bits_32(10000000,11111111,10101010,01010101) = 2164238933 - */ - -enum CDCE18005 { - Reg0, Reg1, Reg2, Reg3, Reg4, Reg5, Reg6, Reg7, - Reg8_Status_Control, - Read_Command=0xE, - RAM_EEPROM_Unlock=0x1F, - RAM_EEPROM_Lock=0x3f -} TI_CDCE18005; - -// Table of 32-bit constants to be written to the TI chip's registers. These are -// from the "Special Settings" on Page 35 of the datasheet. -// For the GPS's 10 MHz output -uint32_t table_Pri_Ref[] = { - Bits_32(1,01010100,0,0), // Reg 0 - Bits_32(1,01010100,0,0), // Outputs LVCMOS Positive&Negative Active - Non-inverted - Bits_32(1,01010100,0,0), - Bits_32(1,01010100,0,0), - Bits_32(1,01010100,0,0), // All have output divide ratio to be 1; Aux Output is OFF - Bits_32(0,0,1001,11010100), // Reg 5 LVCMOS in; p31 of TI datasheet - Bits_32(1,0,0010000,0), // Reg 6 // SCAS863A – NOVEMBER 2008 – REVISED JUNE 2011 - Bits_32(1,01000000,0,0), // Reg 7 - Bits_32(0,0,1,10000000) // Reg8 Status/Control -}; - -// For the External 10 MHz input LVDS with external termination, -// Effectively DC coupled -uint32_t table_Sec_Ref[] = { - Bits_32(0001,01010100,0,100000), // Reg 0 -- use Secondary Reference for all channels - Bits_32(0001,01010100,0,100000), // Outputs LVCMOS Positive&Negative Active - Non-inverted - Bits_32(0001,01010100,0,100000), - Bits_32(0001,01010100,0,100000), - Bits_32(0001,01010100,0,100000), - Bits_32(0,0,1,10011011), // Reg 5, Failsafe OFF b5.11 = 0 - Bits_32(1,0,10000,0), // Reg 6; try again - Bits_32(1,01000000,0,0), - Bits_32(0,0,1,10000000) // Reg8 Status/Control -}; - -// Table 19 conflicts with Tables 5 thru 9 - in how LVCMOS outputs are defined -// extra error in Table 9, for bits 24 and 25 -int table_size = sizeof (table_Pri_Ref) / sizeof(uint32_t); - -void set_bit(uint8_t bit_number, enum Levels bit_value) { - - if(bit_value == Hi) - PORTA |= 1<<bit_number; - else - PORTA &= ~ (1<<bit_number); -} - -bool get_bit(uint8_t bit_number) { - asm("nop"); - - uint8_t portA = PINA; - return (portA & 1<< bit_number) > 0 ? TRUE : FALSE; -} - -// Send 32 bits to TI chip, LSB first. -// Don't worry about reading any bits back at this time -void send_SPI(uint32_t bits) { - - // Basically, when the clock is low, one can set MOSI to anything, as it's - // ignored. - set_bit(CE_, Lo); // Start SPI transaction with TI chip - - // Send each bit, LSB first, add a bit of delay before the clock, and then - // toggle the clock line. - for (uint8_t i=0; i<32; i++) { - set_bit(MOSI, ((bits & (1UL<<i)) ? Hi : Lo) ); - asm("nop"); - set_bit(CLK, Hi); - set_bit(CLK, Lo); - } - - // OK, transaction is over - set_bit(CE_, Hi); -} - -void reset_TI_CDCE18005() { - // First, reset the chip. Or, if you will, pull /SYNC low then high - set_bit(CE_, Hi); - set_bit(PD_, Lo); - wait(); - - // Out of Power Down state - set_bit(PD_, Hi); - wait(); - - set_bit(SYNC_, Lo); - wait(); - set_bit(SYNC_, Hi); - - wait(); -} - -void setup_TI_CDCE18005(enum TI_Input_10_MHz which_input) { - // Send the table of data to init the clock distribution chip. Uses SPI. - uint32_t temp; - - if(which_input == Primary_GPS) { - for(uint8_t i=0; i<table_size; i++){ - temp = table_Pri_Ref[i]<<4; - temp |= i; - send_SPI(temp); // Make sure the register's address is in the LSBs - } - } else { - // is Secondary_Ext -- External 10 MHz input from SMA connector - for(uint8_t i=0; i<table_size; i++){ - temp = table_Sec_Ref[i]<<4; - temp |= i; - // Make sure the register's address is in the LSBs - send_SPI(temp); - } - } -} - -uint32_t receive_SPI() { - uint32_t bits = 0; - - set_bit(CE_, Hi); // Make sure we're inactive - set_bit(CLK, Lo); // and clk line is inactive, too - set_bit(MOSI,Lo); // Make our bit output zero, for good measure - set_bit(CE_, Lo); // Start SPI transaction with TI chip; MOSI is don't care - - // For each bit we are receiving, prep, clock in the bit LSB first - for (uint8_t i=0; i<32; i++){ - bits >>= 1; - set_bit(CLK, Hi); - if( get_bit(MISO) ) bits |= 0x80000000; - set_bit(CLK, Lo); - } - - // OK, transaction is over - set_bit(CE_, Hi); - - // Ditch the lower 4 bits, which only contain the address - return (uint32_t)(bits >> 4); -} - -uint32_t get_TI_CDCE18005(enum CDCE18005 which_register){ - uint32_t get_reg_value = 0; - get_reg_value = (0xf0 & which_register << 4) | Read_Command; - - // This tells the TI chip to send us the reg. value requested - send_SPI(get_reg_value); - return receive_SPI(); -} - -bool check_TI_CDCE18005(enum TI_Input_10_MHz which_input, - enum CDCE18005 which_register) { - - if(which_input == Primary_GPS){ - uint32_t read_value = get_TI_CDCE18005(which_register); - return read_value == table_Pri_Ref[which_register]; - } else { - uint32_t read_value = get_TI_CDCE18005(which_register); - return read_value == table_Sec_Ref[which_register]; - } -} - -void Setup_Atmel_IO_Ports() { -/* - * PORT A - * - * pin# Sig Our Functional Name - * - * p51 PA0 CLK_CDCE to U205 pin 24 -- L-->H edge latches MOSI and MISO in CDCE18005 - * p50 PA1 CE_CDCE Low = Chip Enabled for SPI comm to U205 pin 25 - * p49 PA2 MOSI_CDCE Goes to CDCE18005 - U205 pin 23 - * p48 PA3 MISO_CDCE Input Comes from U205 pin 22 - * p47 PA4 PD_CDCE Low = Chip is in Power-Down state; is Hi for normal operation U205 pin 12 - * p46 PA5 SYNC_CDCE Low = Chip is sync'd with interal dividers; Hi for normal operation U205 pin 14 - * p45 PA6 PPS_SEL Low --> PPS_EXT selected; Hi -> PPS_GPS selected; to U203 pin 1 - * p44 PA7 gps_lock Input Comes from M9107 - U206 pin 3 - * - */ - -// /pd_cdcd, /sync_code, /ce need to be 1 (disabled) to start -// all bits are outputs, except PA7 (gps_lock) and PA3 (MISO_CDCE) are inputs -PORTA = Bits_8(00110010); -DDRA = 1<<DDA6 | 1<<DDA5 | 1<<DDA4 | 1<<DDA2 | 1<<DDA1 | 1<<DDA0; - -/* - * Port B - * - * pin# Sig Our Functional Name - * - * p10 PB0 Ethernet /SEN - * p11 PB1 Ethernet SCLK - * p12 PB2 Ethernet MOSI - * p13 PB3 Ethernet MISO - * p14 PB4 Not connected, set as output with value 0 - * p15 PB5 Ethernet /RESET -- Set to HI for normal use, weak input - * p16 PB6 Ethernet /WOL --- Wake on LAN -- set, weak input - * p17 PB7 Not connected, set as output with value 0 - * - */ - -PORTB = Bits_8(01100001); // Initial Value is all zeros -DDRB = 1<<DDB2 | 1<<DDB4 | 1<<DDB7; // MOSI is an output; the Not Connected pins are also outputs - -/* - * Port C - * - * pin# Sig Our Functional Name - * - * p34 PC0 Not connected, set as output with value 0 - * p35 PC1 Reference Select Switch INPUT - * p36 PC2 Not connected, set as output with value 0 - * p37 PC3 Not connected, set as output with value 0 - * p38 PC4 Not connected, set as output with value 0 - * p40 PC5 "Top LED" of D103 3-stack of green LEDs - * p41 PC6 "Middle LED" - * p43 PC7 "Bottom LED" - * - */ - -PORTC = 0; // Initial Value is all zeros -DDRC = ~( 1<<DDC1 ); // All bits are outputs, except PC1. including the 5 Not Connected bits - -/* - * Port D - * - * pin# Sig Our Functional Name - * - * p25 PD0 Ethernet /INT input - * p26 PD1 GPS NMEA bit, output - * p27 PD2 GPS Serial Out (RXD; INT1) INPUT - * p28 PD3 GPS Serial In (TXD) OUTPUT - * p29 PD4 GPS Present, INPUT hi = Present - * p30 PD5 Not connected, set as output with value 0 - * p31 PD6 Not connected, set as output with value 0 - * p32 PD7 Not connected, set as output with value 0 - * - */ - -PORTD = 0; // Initial Value is all zeros -DDRD = 1<<DDD3; - -/* - * Port E - * - * pin# Sig Dir Our Functional Name - * - * p2 PE0 In avr_rxd (Also MOSI [PDI] when used for SPI programming of the chip) - * p3 PE1 Out avr_txd (Also MISO [PDO] when used for SPI programming of the chip) - * p4 PE2 In avr_cts - * p5 PE3 Out avr_rts - * p6 PE4 In PPS_GPS - * p7 PE5 In PPS_EXT_n - * p8 PE6 In Not Connected - * p9 PE7 In Not Connected - * - */ - -PORTE = 0; -DDRE = 1<<DDE1; // make outputs, set to zero. PE1 is usart0 TXD - -/* - * Port F - * - * Split into 2 nibbles; goes to Amp/Filter board to select ENABLE and two bits - * to select band one bit per nibble is not connected. - * - * pin Sig Dir Our Functional Name - * - * p61 PF0 Out J117 pin 3 (J117 pins 1 and 2 are GND) - * p60 PF1 Out J117 pin 4 - * p59 PF2 Out J117 pin 5 - * p58 PF3 Out J117 pin 6 - * p57 PF4 Out J118 pin 3 (J118 pins 1 and 2 are GND) - * p56 PF5 Out J118 pin 4 - * p55 PF6 Out J118 pin 5 - * p54 PF7 Out J118 pin 6 - * - */ - -PORTF = 0; // Initial Value is all zeros; be sure ENABLE bits are active high!!!! -DDRF = 0xff; // All bits are outputs - -led(Middle,On); -setup_TI_CDCE18005(Primary_GPS); // 10 MHz from Internal Source - -led(Top,On); -PORTA |= (1<<PA6); // PPS from Internal source -} - -// NOT PRESENT unless proven so... -bool Global_GPS_Present = (bool)FALSE; -bool Global_Ext_Ref_Is_Present = (bool)FALSE; - -void LEDs_Off(){ - led(Top,Off); - led(Middle,Off); - led(Bottom,Off); -} - -void Force_Internal(){ - led(Top,On); - led(Middle,Off); - led(Bottom,On); - - setup_TI_CDCE18005(Primary_GPS); - - // Set PPS to Primary (1) n.b.: "1" in general means "Internal" for all - // such signals - PORTA |= (1<<PA6); -} - -void Force_External(){ - led(Top, Off); - led(Middle, On); - led(Bottom, On); - - setup_TI_CDCE18005(Secondary_Ext); - - // Set PPS to External - PORTA &= ~(1<<PA6); -} - -void Prefer_Internal(){ - - if(Global_GPS_Present) - Force_Internal(); - else if(Global_Ext_Ref_Is_Present) - Force_External(); - else - LEDs_Off(); -} - -void Prefer_External(){ - // if external is NOT OK, then force Internal - if(Global_Ext_Ref_Is_Present) - Force_External(); - else if(Global_GPS_Present) - Force_Internal(); - else - LEDs_Off(); -} - -bool Check_What_Is_Present(){ - - // See if +5 scaled to 3.3 from GPSDO is there - Global_GPS_Present = (PIND & (1<<DDD4)) != 0; - - volatile uint8_t portE = PINE; - volatile uint8_t prev, now; - - // Get PREVIOUS state of the input - prev = ( portE & (1 << DDE7) ? 1 : 0); - - for(uint16_t c=1; c; c++){ - portE = PINE; - now = ( portE & (1 << DDE7) ? 1 : 0); - - if(prev != now){ - Global_Ext_Ref_Is_Present = (bool)TRUE; - - return (bool)TRUE; - } - } - - // Else, if it didn't wiggle in that time, then it didn't wiggle - // So ext. is NOT present - Global_Ext_Ref_Is_Present = (bool)FALSE; - return (bool)FALSE; -} - - -bool get_Switch_State(){ - uint8_t portC = PINC; - - // UP is prefer internal, - // DOWN is prefer external - return (bool)(portC & (1<<DDC1) ? Off : On); -} - -/******************************************************************************* -* Main Routine -*******************************************************************************/ - -int main(void){ - - bool Old_Switch_State, Current_Switch_State, Old_Global_Ext_Ref_Is_Present = FALSE; - - // Global Interrupt Disable --- enable with SEI if desired later - asm("cli"); - - Setup_Atmel_IO_Ports(); - - /* - * DO THIS FOREVER: - * - * get_switch_state - * - * if SWITCH_CHANGED: - * - * if PREFER_INTERNAL: - * if INTERNAL_PRESENT do_internal - * else if EXTERNAL_PRESENT do_external - * else LEDs OFF - * - * if PREFER_EXTERNAL: - * if EXTERNAL_PRESENT do_external - * else if INTERNAL_PRESENT do_internal - * else LEDs OFF - * - */ - - Old_Switch_State = ! get_Switch_State(); - - // Because down below, we use this to get state swap So we arbitrarily set - // the PREVIOUS state to be the "other" state so that, below, we trigger - // what happens when the switch changes This first "change" is therefore - // artificial to keep the logic, below, cleaner - while(TRUE) { - // Set "Global_Ext_Ref_Is_Present" and "Global_GPS_Present" - Check_What_Is_Present(); - - // Off means "Prefer External" -- DOWN - // On means "Prefer Internal" -- UP - Current_Switch_State = get_Switch_State(); - - if( (Current_Switch_State != Old_Switch_State) || - (Global_Ext_Ref_Is_Present != Old_Global_Ext_Ref_Is_Present) ) { - - Old_Switch_State = Current_Switch_State; - Old_Global_Ext_Ref_Is_Present = Global_Ext_Ref_Is_Present; - - if(Current_Switch_State == On) - Prefer_Internal(); - else - Prefer_External(); - } - } -} diff --git a/firmware/octoclock/bootloader/CMakeLists.txt b/firmware/octoclock/bootloader/CMakeLists.txt new file mode 100644 index 000000000..04bcfc492 --- /dev/null +++ b/firmware/octoclock/bootloader/CMakeLists.txt @@ -0,0 +1,56 @@ +# +# Copyright 2014 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +set(bootloader_sources + ../lib/init.c + ../lib/enc28j60.c + ../lib/network.c + ../lib/arp_cache.c + main.c +) + +add_executable(octoclock_bootloader.elf ${bootloader_sources}) + +# +# The __AVR_LIBC_DEPRECATED_ENABLE__ flag is necessary because of a bug in some versions of avr-libc +# where including <avr/boot.h> when using an atmega128 will cause a compiler error. +# +# Details: http://savannah.nongnu.org/bugs/?36410 +# +set_target_properties(octoclock_bootloader.elf PROPERTIES + COMPILE_FLAGS "${CMAKE_C_FLAGS} -Os -D__AVR_LIBC_DEPRECATED_ENABLE__ -D__BOOTLOADER__ -Wall" + LINK_FLAGS "-Os -Wl,--relax,--section-start=.text=0x1E000,-Map=octoclock_bootloader.map,--cref" +) + + +add_custom_command( + OUTPUT ${CMAKE_BINARY_DIR}/octoclock_bootloader.hex + DEPENDS octoclock_bootloader.elf + COMMENT "Generating octoclock_bootloader.hex" + COMMAND ${AVR_OBJCOPY} -O ihex ${CMAKE_CURRENT_BINARY_DIR}/octoclock_bootloader.elf ${CMAKE_BINARY_DIR}/octoclock_bootloader.hex +) +add_custom_target( + octoclock_bootloader_hex ALL + DEPENDS ${CMAKE_BINARY_DIR}/octoclock_bootloader.hex +) + +add_custom_target( + upload_bootloader + ${AVRDUDE} -p atmega128 -c ${PROGRAMMER} -P usb -U efuse:w:0xFF:m -U hfuse:w:0x80:m -U lfuse:w:0xFF:m -U flash:w:octoclock_bootloader.hex:i + WORKING_DIRECTORY ${CMAKE_BINARY_DIR} + DEPENDS octoclock_bootloader_hex + COMMENT "Uploading OctoClock bootloader to device with ${PROGRAMMER}" +) diff --git a/firmware/octoclock/bootloader/main.c b/firmware/octoclock/bootloader/main.c new file mode 100644 index 000000000..5e2e6f17e --- /dev/null +++ b/firmware/octoclock/bootloader/main.c @@ -0,0 +1,235 @@ +/* + * Copyright 2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <stdbool.h> +#include <stdint.h> +#include <string.h> + +#include <avr/boot.h> +#include <avr/eeprom.h> +#include <avr/io.h> +#include <avr/pgmspace.h> + +#include <octoclock.h> +#include <debug.h> +#include <network.h> + +#include <util/delay.h> + +#include <net/enc28j60.h> + +#include "octoclock/common.h" + +/* + * The number for 5 seconds is close enough to 65535 that the + * timer may have overflowed before the main loop queries it. + */ +#define TIME_PASSED (TCNT1 > (TIMER1_ONE_SECOND*5) || (TIFR & _BV(TOV1))) + +//States +static bool received_cmd = false; +static bool done_burning = false; + +typedef struct { + uint16_t fw_len; + uint16_t fw_crc; +} crc_info_t; + +static crc_info_t crc_info; + +static void boot_program_page(uint8_t *buf, uint16_t page){ + uint16_t i; + + eeprom_busy_wait(); + + boot_page_erase(page); + boot_spm_busy_wait(); // Wait until the memory is erased. + + for(i = 0; i < SPM_PAGESIZE; i += 2){ + // Set up little-endian word. + uint16_t w = *buf++; + w += ((*buf++) << 8); + + boot_page_fill(page + i, w); + } + + boot_page_write(page); // Store buffer in flash page. + boot_spm_busy_wait(); // Wait until the memory is written. + + // Reenable RWW-section again. We need this if we want to jump back + // to the application after bootloading. + boot_rww_enable(); +} + +static void read_firmware(uint16_t addr, octoclock_packet_t *pkt_out){ + for(size_t i = 0; i < SPM_PAGESIZE; i++){ + pkt_out->data[i] = pgm_read_byte(addr+i); + } +} + +void handle_udp_query_packet( + struct socket_address src, struct socket_address dst, + unsigned char *payload, int payload_len +){ + const octoclock_packet_t *pkt_in = (octoclock_packet_t*)payload; + + //Respond to query packets + if(pkt_in->code == OCTOCLOCK_QUERY_CMD){ + octoclock_packet_t pkt_out; + pkt_out.proto_ver = OCTOCLOCK_BOOTLOADER_PROTO_VER; + pkt_out.sequence = pkt_in->sequence; + pkt_out.code = OCTOCLOCK_QUERY_ACK; + pkt_out.len = 0; + send_udp_pkt(OCTOCLOCK_UDP_CTRL_PORT, src, (void*)&pkt_out, sizeof(octoclock_packet_t)); + } +} + +static void calculate_crc(uint16_t *crc, uint16_t len){ + *crc = 0xFFFF; + + for(size_t i = 0; i < len; i++){ + *crc ^= pgm_read_byte(i); + for(uint8_t j = 0; j < 8; ++j){ + if(*crc & 1) *crc = (*crc >> 1) ^ 0xA001; + else *crc = (*crc >> 1); + } + } +} + +static bool valid_app(){ + crc_info_t crc_eeprom_info; + eeprom_read_block(&crc_eeprom_info, (void*)OCTOCLOCK_EEPROM_APP_LEN, 4); + + calculate_crc(&(crc_info.fw_crc), crc_eeprom_info.fw_len); + return (crc_info.fw_crc == crc_eeprom_info.fw_crc); +} + +void handle_udp_fw_packet( + struct socket_address src, struct socket_address dst, + unsigned char *payload, int payload_len +){ + octoclock_packet_t *pkt_in = (octoclock_packet_t*)payload; + octoclock_packet_t pkt_out; + pkt_out.proto_ver = OCTOCLOCK_BOOTLOADER_PROTO_VER; + pkt_out.sequence = pkt_in->sequence; + pkt_out.len = 0; + + switch(pkt_in->code){ + case PREPARE_FW_BURN_CMD: + received_cmd = true; + done_burning = false; + crc_info.fw_len = pkt_in->len; + pkt_out.code = FW_BURN_READY_ACK; + break; + + case FILE_TRANSFER_CMD: + boot_program_page(pkt_in->data, pkt_in->addr); + pkt_out.code = FILE_TRANSFER_ACK; + break; + + case READ_FW_CMD: + pkt_out.code = READ_FW_ACK; + read_firmware(pkt_in->addr, &pkt_out); + break; + + case FINALIZE_BURNING_CMD: + //With stuff verified, burn CRC info into EEPROM + done_burning = true; + calculate_crc(&(crc_info.fw_crc), crc_info.fw_len); + eeprom_write_block(&crc_info, (void*)OCTOCLOCK_EEPROM_APP_LEN, 4); + pkt_out.code = FINALIZE_BURNING_ACK; + break; + + default: + break; + } + send_udp_pkt(OCTOCLOCK_UDP_FW_PORT, src, (void*)&pkt_out, sizeof(octoclock_packet_t)); +} + +void handle_udp_eeprom_packet( + struct socket_address src, struct socket_address dst, + unsigned char *payload, int payload_len +){ + octoclock_packet_t *pkt_in = (octoclock_packet_t*)payload; + octoclock_packet_t pkt_out; + pkt_out.proto_ver = OCTOCLOCK_BOOTLOADER_PROTO_VER; + pkt_out.sequence = pkt_in->sequence; + pkt_out.len = 0; + + if(pkt_in->proto_ver == OCTOCLOCK_FW_COMPAT_NUM){ + switch(pkt_in->code){ + case CLEAR_EEPROM_CMD: + received_cmd = true; + uint8_t blank_eeprom[103]; + memset(blank_eeprom, 0xFF, 103); + eeprom_write_block(blank_eeprom, 0, 103); + pkt_out.code = CLEAR_EEPROM_ACK; + send_udp_pkt(OCTOCLOCK_UDP_EEPROM_PORT, src, (void*)&pkt_out, sizeof(octoclock_packet_t)); + break; + + default: + break; + } + } +} + +int main(void){ + + asm("cli"); + + //Initialization + setup_atmel_io_ports(); + network_init(); + init_udp_listeners(); + register_udp_listener(OCTOCLOCK_UDP_CTRL_PORT, handle_udp_query_packet); + register_udp_listener(OCTOCLOCK_UDP_FW_PORT, handle_udp_fw_packet); + register_udp_listener(OCTOCLOCK_UDP_EEPROM_PORT, handle_udp_eeprom_packet); + + //Turn LED's on to show we're in the bootloader + PORTC |= 0x20; + PORTC |= (0x20<<1); + PORTC |= (0x20<<2); + + TIMER1_INIT(); + bool app_checked = false; + + while(true){ + if(done_burning){ + if(valid_app()) break; + else done_burning = false; //Burning somehow failed and wasn't caught + } + if(!app_checked && !received_cmd && TIME_PASSED){ + app_checked = true; + if(valid_app()) break; + } + + network_check(); + } + + //Turn LED's off before moving to application + PORTC &= ~0x20; + PORTC &= ~(0x20<<1); + PORTC &= ~(0x20<<2); + + /* + * Whether the bootloader reaches here through five seconds of inactivity + * or after a firmware burn just finished, it can be assumed that the application + * is valid. + */ + asm("jmp 0000"); + return 0; //Will never get here, but AVR-GCC needs it +} diff --git a/firmware/octoclock/include/arch/cc.h b/firmware/octoclock/include/arch/cc.h new file mode 100644 index 000000000..d8d53ecf8 --- /dev/null +++ b/firmware/octoclock/include/arch/cc.h @@ -0,0 +1,65 @@ +#ifndef INCLUDED_ARCH_CC_H +#define INCLUDED_ARCH_CC_H + +#define BYTE_ORDER BIG_ENDIAN + + +#if 1 +#include <stdint.h> + +typedef uint8_t u8_t; +typedef int8_t s8_t; +typedef uint16_t u16_t; +typedef int16_t s16_t; +typedef uint32_t u32_t; +typedef int32_t s32_t; + +#else + +typedef unsigned char u8_t; +typedef signed char s8_t; +typedef unsigned short u16_t; +typedef signed short s16_t; +typedef unsigned long u32_t; +typedef signed long s32_t; +#endif + +typedef u32_t mem_ptr_t; + +#if 1 /* minimal printf */ +#define U16_F "u" +#define S16_F "d" +#define X16_F "x" +#define U32_F "u" +#define S32_F "d" +#define X32_F "x" + +#else + +#define U16_F "hu" +#define S16_F "hd" +#define X16_F "hx" +#define U32_F "lu" +#define S32_F "ld" +#define X32_F "lx" +#endif + +#if 1 // gcc: don't pack +#define PACK_STRUCT_FIELD(x) x +#define PACK_STRUCT_STRUCT +#define PACK_STRUCT_BEGIN +#define PACK_STRUCT_END +#else // gcc: do pack +#define PACK_STRUCT_FIELD(x) x +#define PACK_STRUCT_STRUCT __attribute__((packed)) +#define PACK_STRUCT_BEGIN +#define PACK_STRUCT_END +#endif + +//#define LWIP_PLATFORM_ASSERT(msg) ((void)0) +void abort(void); +#define LWIP_PLATFORM_ASSERT(msg) abort() + + +#endif /* INCLUDED_ARCH_CC_H */ + diff --git a/firmware/octoclock/include/arch/perf.h b/firmware/octoclock/include/arch/perf.h new file mode 100644 index 000000000..f0906d03f --- /dev/null +++ b/firmware/octoclock/include/arch/perf.h @@ -0,0 +1,2 @@ +#define PERF_START ((void) 0) +#define PERF_STOP(msg) ((void) 0) diff --git a/firmware/octoclock/include/avrlibdefs.h b/firmware/octoclock/include/avrlibdefs.h new file mode 100644 index 000000000..7f0cc0adc --- /dev/null +++ b/firmware/octoclock/include/avrlibdefs.h @@ -0,0 +1,72 @@ +/*! \file avrlibdefs.h \brief AVRlib global defines and macros. */ +//***************************************************************************** +// +// File Name : 'avrlibdefs.h' +// Title : AVRlib global defines and macros include file +// Author : Pascal Stang +// Created : 7/12/2001 +// Revised : 9/30/2002 +// Version : 1.1 +// Target MCU : Atmel AVR series +// Editor Tabs : 4 +// +// Description : This include file is designed to contain items useful to all +// code files and projects, regardless of specific implementation. +// +// This code is distributed under the GNU Public License +// which can be found at http://www.gnu.org/licenses/gpl.txt +// +//***************************************************************************** + + +#ifndef AVRLIBDEFS_H +#define AVRLIBDEFS_H + +// Code compatibility to new AVR-libc +// outb(), inb(), inw(), outw(), BV(), sbi(), cbi(), sei(), cli() +#ifndef outb + #define outb(addr, data) addr = (data) +#endif +#ifndef inb + #define inb(addr) (addr) +#endif +#ifndef outw + #define outw(addr, data) addr = (data) +#endif +#ifndef inw + #define inw(addr) (addr) +#endif +#ifndef BV + #define BV(bit) (1<<(bit)) +#endif +#ifndef cbi + #define cbi(reg,bit) reg &= ~(BV(bit)) +#endif +#ifndef sbi + #define sbi(reg,bit) reg |= (BV(bit)) +#endif +#ifndef cli + #define cli() __asm__ __volatile__ ("cli" ::) +#endif +#ifndef sei + #define sei() __asm__ __volatile__ ("sei" ::) +#endif + +// use this for packed structures +// (this is seldom necessary on an 8-bit architecture like AVR, +// but can assist in code portability to AVR) +#define GNUC_PACKED __attribute__((packed)) + +// port address helpers +#define DDR(x) ((x)-1) // address of data direction register of port x +#define PIN(x) ((x)-2) // address of input register of port x + +// MIN/MAX/ABS macros +#define MIN(a,b) ((a<b)?(a):(b)) +#define MAX(a,b) ((a>b)?(a):(b)) +#define ABS(x) ((x>0)?(x):(-x)) + +// constants +#define PI 3.14159265359 + +#endif diff --git a/firmware/octoclock/include/avrlibtypes.h b/firmware/octoclock/include/avrlibtypes.h new file mode 100644 index 000000000..4351c8ea8 --- /dev/null +++ b/firmware/octoclock/include/avrlibtypes.h @@ -0,0 +1,73 @@ +/*! \file avrlibtypes.h \brief AVRlib global types and typedefines. */ +//***************************************************************************** +// +// File Name : 'avrlibtypes.h' +// Title : AVRlib global types and typedefines include file +// Author : Pascal Stang +// Created : 7/12/2001 +// Revised : 9/30/2002 +// Version : 1.0 +// Target MCU : Atmel AVR series +// Editor Tabs : 4 +// +// Description : Type-defines required and used by AVRlib. Most types are also +// generally useful. +// +// This code is distributed under the GNU Public License +// which can be found at http://www.gnu.org/licenses/gpl.txt +// +//***************************************************************************** + + +#ifndef AVRLIBTYPES_H +#define AVRLIBTYPES_H + +#ifndef WIN32 + // true/false defines + #define FALSE 0 + #define TRUE -1 +#endif + +// datatype definitions macros +typedef unsigned char u08; +typedef signed char s08; +typedef unsigned short u16; +typedef signed short s16; +typedef unsigned long u32; +typedef signed long s32; +typedef unsigned long long u64; +typedef signed long long s64; + +// maximum value that can be held +// by unsigned data types (8,16,32bits) +#define MAX_U08 255 +#define MAX_U16 65535 +#define MAX_U32 4294967295 + +// maximum values that can be held +// by signed data types (8,16,32bits) +#define MIN_S08 -128 +#define MAX_S08 127 +#define MIN_S16 -32768 +#define MAX_S16 32767 +#define MIN_S32 -2147483648 +#define MAX_S32 2147483647 + +#ifndef WIN32 + // more type redefinitions + typedef unsigned char BOOL; + typedef unsigned char BYTE; + typedef unsigned int WORD; + typedef unsigned long DWORD; + + typedef unsigned char UCHAR; + typedef unsigned int UINT; + typedef unsigned short USHORT; + typedef unsigned long ULONG; + + typedef char CHAR; + typedef int INT; + typedef long LONG; +#endif + +#endif diff --git a/firmware/octoclock/include/clkdist.h b/firmware/octoclock/include/clkdist.h new file mode 100644 index 000000000..633df9ddf --- /dev/null +++ b/firmware/octoclock/include/clkdist.h @@ -0,0 +1,51 @@ +/* + * Copyright 2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _CLKDIST_H_ +#define _CLKDIST_H_ + +#include <stdbool.h> + +#include <octoclock.h> + +typedef enum { + Reg0, Reg1, Reg2, Reg3, Reg4, Reg5, Reg6, Reg7, + Reg8_Status_Control, + Read_Command=0xE, + RAM_EEPROM_Unlock=0x1F, + RAM_EEPROM_Lock=0x3f +} CDCE18005; + +typedef enum { + Primary_GPS, + Secondary_Ext +} TI_Input_10_MHz; + +typedef enum { + Lo, + Hi +} Levels; + +void setup_TI_CDCE18005(TI_Input_10_MHz which_input); + +void reset_TI_CDCE18005(void); + +uint32_t get_TI_CDCE18005(CDCE18005 which_register); + +bool check_TI_CDCE18005(TI_Input_10_MHz which_input, CDCE18005 which_register); + +#endif /* _CLKDIST_H_ */ diff --git a/firmware/octoclock/include/compiler.h b/firmware/octoclock/include/compiler.h new file mode 100644 index 000000000..542c83568 --- /dev/null +++ b/firmware/octoclock/include/compiler.h @@ -0,0 +1,24 @@ +/* -*- c++ -*- */ +/* + * Copyright 2009, 2010, 2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef INCLUDED_COMPILER_H +#define INCLUDED_COMPILER_H + +#define _AL2 __attribute__((aligned (2))) +#define _AL4 __attribute__((aligned (4))) + +#endif /* INCLUDED_COMPILER_H */ diff --git a/firmware/octoclock/include/debug.h b/firmware/octoclock/include/debug.h new file mode 100644 index 000000000..ee0618bc6 --- /dev/null +++ b/firmware/octoclock/include/debug.h @@ -0,0 +1,94 @@ +/* + * Copyright 2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _DEBUG_H_ +#define _DEBUG_H_ + +//Only expose these macros to the firmware, and only if specified +#if defined(DEBUG) && !defined(__BOOTLOADER__) + +#include <avr/pgmspace.h> +#include <stdbool.h> +#include <stdint.h> + +#include <serial.h> + +#define DEBUG_INIT() serial_init(&PORTF, 0) +#define DEBUG_LOG(msg) serial_tx_P(PSTR(msg), &PORTF, 0, true) +#define DEBUG_LOG_NNL(msg) serial_tx_P(PSTR(msg), &PORTF, 0, false) +#define DEBUG_LOG_BYTE(byte) serial_tx_byte(byte, &PORTF, 0, true) +#define DEBUG_LOG_BYTE_NNL(byte) serial_tx_byte(byte, &PORTF, 0, false) +#define DEBUG_LOG_HEX(byte) serial_tx_hex(byte, &PORTF, 0, true) +#define DEBUG_LOG_HEX_NNL(byte) serial_tx_hex(byte, &PORTF, 0, false) + +#define DEBUG_LOG_CHAR_ARR_NNL(arr,len) for(uint8_t i = 0; i < len; i++){ \ + DEBUG_LOG_BYTE_NNL(arr[i]); \ + DEBUG_LOG_NNL(" "); \ + } +#define DEBUG_LOG_CHAR_ARR(arr,len) DEBUG_LOG_CHAR_ARR_NNL(arr,len); \ + DEBUG_LOG(" ") + +#define DEBUG_LOG_MAC(mac_addr) DEBUG_LOG_HEX_NNL(mac_addr[0]); \ + DEBUG_LOG_NNL(":"); \ + DEBUG_LOG_HEX_NNL(mac_addr[1]); \ + DEBUG_LOG_NNL(":"); \ + DEBUG_LOG_HEX_NNL(mac_addr[2]); \ + DEBUG_LOG_NNL(":"); \ + DEBUG_LOG_HEX_NNL(mac_addr[3]); \ + DEBUG_LOG_NNL(":"); \ + DEBUG_LOG_HEX_NNL(mac_addr[4]); \ + DEBUG_LOG_NNL(":"); \ + DEBUG_LOG_HEX(mac_addr[5]); + +#define DEBUG_LOG_IP(ip_addr) DEBUG_LOG_BYTE_NNL(ip4_addr1(&ip_addr)); \ + DEBUG_LOG_NNL("."); \ + DEBUG_LOG_BYTE_NNL(ip4_addr2(&ip_addr)); \ + DEBUG_LOG_NNL("."); \ + DEBUG_LOG_BYTE_NNL(ip4_addr3(&ip_addr)); \ + DEBUG_LOG_NNL("."); \ + DEBUG_LOG_BYTE(ip4_addr4(&ip_addr)); + +#define DEBUG_LOG_SHORT(num) DEBUG_LOG_HEX_NNL(((uint8_t*)&num)[1]); \ + DEBUG_LOG_HEX(((uint8_t*)&num)[0]); + +#define DEBUG_LOG_INT(num) DEBUG_LOG_HEX_NNL(((uint8_t*)&num)[3]); \ + DEBUG_LOG_HEX(((uint8_t*)&num)[2]); \ + DEBUG_LOG_HEX(((uint8_t*)&num)[1]); \ + DEBUG_LOG_HEX(((uint8_t*)&num)[0]); + +#else + +#define DEBUG_INIT() +#define DEBUG_LOG(msg) +#define DEBUG_LOG_NNL(msg) +#define DEBUG_LOG_CHAR(byte) +#define DEBUG_LOG_CHAR_NNL(byte) +#define DEBUG_LOG_BYTE(byte) +#define DEBUG_LOG_BYTE_NNL(byte) +#define DEBUG_LOG_HEX(byte) +#define DEBUG_LOG_HEX_NNL(byte) +#define DEBUG_LOG_CHAR_ARR(arr,len) +#define DEBUG_LOG_CHAR_ARR_NNL(arr,len) + +#define DEBUG_LOG_MAC(mac_addr) +#define DEBUG_LOG_IP(ip_addr) +#define DEBUG_LOG_SHORT(num) +#define DEBUG_LOG_INT(num) + +#endif + +#endif /* _DEBUG_H_ */ diff --git a/firmware/octoclock/include/gpsdo.h b/firmware/octoclock/include/gpsdo.h new file mode 100644 index 000000000..fc7d87324 --- /dev/null +++ b/firmware/octoclock/include/gpsdo.h @@ -0,0 +1,32 @@ +/* + * Copyright 2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _GPSDO_H_ +#define _GPSDO_H_ + +#include <stdint.h> + +#define POOLSIZE 256 + +char gpsdo_buf[POOLSIZE]; +gpsdo_cache_state_t gpsdo_state; + +void send_gpsdo_cmd(char* buf, uint8_t size); + +void process_gpsdo_output(void); + +#endif /* _GPSDO_H_ */ diff --git a/firmware/octoclock/include/lwip/COPYING b/firmware/octoclock/include/lwip/COPYING new file mode 100644 index 000000000..e23898b5e --- /dev/null +++ b/firmware/octoclock/include/lwip/COPYING @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2001, 2002 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ + + diff --git a/firmware/octoclock/include/lwip/api.h b/firmware/octoclock/include/lwip/api.h new file mode 100644 index 000000000..f6b1f7434 --- /dev/null +++ b/firmware/octoclock/include/lwip/api.h @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __LWIP_API_H__ +#define __LWIP_API_H__ + +#include "lwip/opt.h" + +#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */ + +#include <stddef.h> /* for size_t */ + +#include "lwip/netbuf.h" +#include "lwip/sys.h" +#include "lwip/ip_addr.h" +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Throughout this file, IP addresses and port numbers are expected to be in + * the same byte order as in the corresponding pcb. + */ + +/* Flags for netconn_write */ +#define NETCONN_NOFLAG 0x00 +#define NETCONN_NOCOPY 0x00 /* Only for source code compatibility */ +#define NETCONN_COPY 0x01 +#define NETCONN_MORE 0x02 + +/* Helpers to process several netconn_types by the same code */ +#define NETCONNTYPE_GROUP(t) (t&0xF0) +#define NETCONNTYPE_DATAGRAM(t) (t&0xE0) + +enum netconn_type { + NETCONN_INVALID = 0, + /* NETCONN_TCP Group */ + NETCONN_TCP = 0x10, + /* NETCONN_UDP Group */ + NETCONN_UDP = 0x20, + NETCONN_UDPLITE = 0x21, + NETCONN_UDPNOCHKSUM= 0x22, + /* NETCONN_RAW Group */ + NETCONN_RAW = 0x40 +}; + +enum netconn_state { + NETCONN_NONE, + NETCONN_WRITE, + NETCONN_LISTEN, + NETCONN_CONNECT, + NETCONN_CLOSE +}; + +enum netconn_evt { + NETCONN_EVT_RCVPLUS, + NETCONN_EVT_RCVMINUS, + NETCONN_EVT_SENDPLUS, + NETCONN_EVT_SENDMINUS +}; + +#if LWIP_IGMP +enum netconn_igmp { + NETCONN_JOIN, + NETCONN_LEAVE +}; +#endif /* LWIP_IGMP */ + +/* forward-declare some structs to avoid to include their headers */ +struct ip_pcb; +struct tcp_pcb; +struct udp_pcb; +struct raw_pcb; +struct netconn; + +/** A callback prototype to inform about events for a netconn */ +typedef void (* netconn_callback)(struct netconn *, enum netconn_evt, u16_t len); + +/** A netconn descriptor */ +struct netconn { + /** type of the netconn (TCP, UDP or RAW) */ + enum netconn_type type; + /** current state of the netconn */ + enum netconn_state state; + /** the lwIP internal protocol control block */ + union { + struct ip_pcb *ip; + struct tcp_pcb *tcp; + struct udp_pcb *udp; + struct raw_pcb *raw; + } pcb; + /** the last error this netconn had */ + err_t err; + /** sem that is used to synchroneously execute functions in the core context */ + sys_sem_t op_completed; + /** mbox where received packets are stored until they are fetched + by the netconn application thread (can grow quite big) */ + sys_mbox_t recvmbox; + /** mbox where new connections are stored until processed + by the application thread */ + sys_mbox_t acceptmbox; + /** only used for socket layer */ + int socket; +#if LWIP_SO_RCVTIMEO + /** timeout to wait for new data to be received + (or connections to arrive for listening netconns) */ + int recv_timeout; +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVBUF + /** maximum amount of bytes queued in recvmbox */ + int recv_bufsize; +#endif /* LWIP_SO_RCVBUF */ + s16_t recv_avail; +#if LWIP_TCP + /** TCP: when data passed to netconn_write doesn't fit into the send buffer, + this temporarily stores the message. */ + struct api_msg_msg *write_msg; + /** TCP: when data passed to netconn_write doesn't fit into the send buffer, + this temporarily stores how much is already sent. */ + size_t write_offset; +#if LWIP_TCPIP_CORE_LOCKING + /** TCP: when data passed to netconn_write doesn't fit into the send buffer, + this temporarily stores whether to wake up the original application task + if data couldn't be sent in the first try. */ + u8_t write_delayed; +#endif /* LWIP_TCPIP_CORE_LOCKING */ +#endif /* LWIP_TCP */ + /** A callback function that is informed about events for this netconn */ + netconn_callback callback; +}; + +/* Register an Network connection event */ +#define API_EVENT(c,e,l) if (c->callback) { \ + (*c->callback)(c, e, l); \ + } + +/* Network connection functions: */ +#define netconn_new(t) netconn_new_with_proto_and_callback(t, 0, NULL) +#define netconn_new_with_callback(t, c) netconn_new_with_proto_and_callback(t, 0, c) +struct +netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto, + netconn_callback callback); +err_t netconn_delete (struct netconn *conn); +/** Get the type of a netconn (as enum netconn_type). */ +#define netconn_type(conn) (conn->type) + +err_t netconn_getaddr (struct netconn *conn, + struct ip_addr *addr, + u16_t *port, + u8_t local); +#define netconn_peer(c,i,p) netconn_getaddr(c,i,p,0) +#define netconn_addr(c,i,p) netconn_getaddr(c,i,p,1) + +err_t netconn_bind (struct netconn *conn, + struct ip_addr *addr, + u16_t port); +err_t netconn_connect (struct netconn *conn, + struct ip_addr *addr, + u16_t port); +err_t netconn_disconnect (struct netconn *conn); +err_t netconn_listen_with_backlog(struct netconn *conn, u8_t backlog); +#define netconn_listen(conn) netconn_listen_with_backlog(conn, TCP_DEFAULT_LISTEN_BACKLOG) +struct netconn * netconn_accept (struct netconn *conn); +struct netbuf * netconn_recv (struct netconn *conn); +err_t netconn_sendto (struct netconn *conn, + struct netbuf *buf, struct ip_addr *addr, u16_t port); +err_t netconn_send (struct netconn *conn, + struct netbuf *buf); +err_t netconn_write (struct netconn *conn, + const void *dataptr, size_t size, + u8_t apiflags); +err_t netconn_close (struct netconn *conn); + +#if LWIP_IGMP +err_t netconn_join_leave_group (struct netconn *conn, + struct ip_addr *multiaddr, + struct ip_addr *interface, + enum netconn_igmp join_or_leave); +#endif /* LWIP_IGMP */ +#if LWIP_DNS +err_t netconn_gethostbyname(const char *name, struct ip_addr *addr); +#endif /* LWIP_DNS */ + +#define netconn_err(conn) ((conn)->err) +#define netconn_recv_bufsize(conn) ((conn)->recv_bufsize) + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_NETCONN */ + +#endif /* __LWIP_API_H__ */ diff --git a/firmware/octoclock/include/lwip/api_msg.h b/firmware/octoclock/include/lwip/api_msg.h new file mode 100644 index 000000000..4272d77cc --- /dev/null +++ b/firmware/octoclock/include/lwip/api_msg.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __LWIP_API_MSG_H__ +#define __LWIP_API_MSG_H__ + +#include "lwip/opt.h" + +#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */ + +#include <stddef.h> /* for size_t */ + +#include "lwip/ip_addr.h" +#include "lwip/err.h" +#include "lwip/sys.h" +#include "lwip/igmp.h" +#include "lwip/api.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* IP addresses and port numbers are expected to be in + * the same byte order as in the corresponding pcb. + */ +/** This struct includes everything that is necessary to execute a function + for a netconn in another thread context (mainly used to process netconns + in the tcpip_thread context to be thread safe). */ +struct api_msg_msg { + /** The netconn which to process - always needed: it includes the semaphore + which is used to block the application thread until the function finished. */ + struct netconn *conn; + /** Depending on the executed function, one of these union members is used */ + union { + /** used for do_send */ + struct netbuf *b; + /** used for do_newconn */ + struct { + u8_t proto; + } n; + /** used for do_bind and do_connect */ + struct { + struct ip_addr *ipaddr; + u16_t port; + } bc; + /** used for do_getaddr */ + struct { + struct ip_addr *ipaddr; + u16_t *port; + u8_t local; + } ad; + /** used for do_write */ + struct { + const void *dataptr; + size_t len; + u8_t apiflags; + } w; + /** used ofr do_recv */ + struct { + u16_t len; + } r; +#if LWIP_IGMP + /** used for do_join_leave_group */ + struct { + struct ip_addr *multiaddr; + struct ip_addr *interface; + enum netconn_igmp join_or_leave; + } jl; +#endif /* LWIP_IGMP */ +#if TCP_LISTEN_BACKLOG + struct { + u8_t backlog; + } lb; +#endif /* TCP_LISTEN_BACKLOG */ + } msg; +}; + +/** This struct contains a function to execute in another thread context and + a struct api_msg_msg that serves as an argument for this function. + This is passed to tcpip_apimsg to execute functions in tcpip_thread context. */ +struct api_msg { + /** function to execute in tcpip_thread context */ + void (* function)(struct api_msg_msg *msg); + /** arguments for this function */ + struct api_msg_msg msg; +}; + +#if LWIP_DNS +/** As do_gethostbyname requires more arguments but doesn't require a netconn, + it has its own struct (to avoid struct api_msg getting bigger than necessary). + do_gethostbyname must be called using tcpip_callback instead of tcpip_apimsg + (see netconn_gethostbyname). */ +struct dns_api_msg { + /** Hostname to query or dotted IP address string */ + const char *name; + /** Rhe resolved address is stored here */ + struct ip_addr *addr; + /** This semaphore is posted when the name is resolved, the application thread + should wait on it. */ + sys_sem_t sem; + /** Errors are given back here */ + err_t *err; +}; +#endif /* LWIP_DNS */ + +void do_newconn ( struct api_msg_msg *msg); +void do_delconn ( struct api_msg_msg *msg); +void do_bind ( struct api_msg_msg *msg); +void do_connect ( struct api_msg_msg *msg); +void do_disconnect ( struct api_msg_msg *msg); +void do_listen ( struct api_msg_msg *msg); +void do_send ( struct api_msg_msg *msg); +void do_recv ( struct api_msg_msg *msg); +void do_write ( struct api_msg_msg *msg); +void do_getaddr ( struct api_msg_msg *msg); +void do_close ( struct api_msg_msg *msg); +#if LWIP_IGMP +void do_join_leave_group( struct api_msg_msg *msg); +#endif /* LWIP_IGMP */ + +#if LWIP_DNS +void do_gethostbyname(void *arg); +#endif /* LWIP_DNS */ + +struct netconn* netconn_alloc(enum netconn_type t, netconn_callback callback); +void netconn_free(struct netconn *conn); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_NETCONN */ + +#endif /* __LWIP_API_MSG_H__ */ diff --git a/firmware/octoclock/include/lwip/arch.h b/firmware/octoclock/include/lwip/arch.h new file mode 100644 index 000000000..3a5a0e4f2 --- /dev/null +++ b/firmware/octoclock/include/lwip/arch.h @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __LWIP_ARCH_H__ +#define __LWIP_ARCH_H__ + +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN 1234 +#endif + +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 4321 +#endif + +#include "arch/cc.h" + +/** Temporary: define format string for size_t if not defined in cc.h */ +#ifndef SZT_F +#define SZT_F U32_F +#endif /* SZT_F */ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef PACK_STRUCT_BEGIN +#define PACK_STRUCT_BEGIN +#endif /* PACK_STRUCT_BEGIN */ + +#ifndef PACK_STRUCT_END +#define PACK_STRUCT_END +#endif /* PACK_STRUCT_END */ + +#ifndef PACK_STRUCT_FIELD +#define PACK_STRUCT_FIELD(x) x +#endif /* PACK_STRUCT_FIELD */ + + +#ifndef LWIP_UNUSED_ARG +#define LWIP_UNUSED_ARG(x) (void)x +#endif /* LWIP_UNUSED_ARG */ + + +#ifdef LWIP_PROVIDE_ERRNO + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Arg list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale NFS file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ + + +#define ENSROK 0 /* DNS server returned answer with no data */ +#define ENSRNODATA 160 /* DNS server returned answer with no data */ +#define ENSRFORMERR 161 /* DNS server claims query was misformatted */ +#define ENSRSERVFAIL 162 /* DNS server returned general failure */ +#define ENSRNOTFOUND 163 /* Domain name not found */ +#define ENSRNOTIMP 164 /* DNS server does not implement requested operation */ +#define ENSRREFUSED 165 /* DNS server refused query */ +#define ENSRBADQUERY 166 /* Misformatted DNS query */ +#define ENSRBADNAME 167 /* Misformatted domain name */ +#define ENSRBADFAMILY 168 /* Unsupported address family */ +#define ENSRBADRESP 169 /* Misformatted DNS reply */ +#define ENSRCONNREFUSED 170 /* Could not contact DNS servers */ +#define ENSRTIMEOUT 171 /* Timeout while contacting DNS servers */ +#define ENSROF 172 /* End of file */ +#define ENSRFILE 173 /* Error reading file */ +#define ENSRNOMEM 174 /* Out of memory */ +#define ENSRDESTRUCTION 175 /* Application terminated lookup */ +#define ENSRQUERYDOMAINTOOLONG 176 /* Domain name is too long */ +#define ENSRCNAMELOOP 177 /* Domain name is too long */ + +#ifndef errno +extern int errno; +#endif + +#endif /* LWIP_PROVIDE_ERRNO */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_ARCH_H__ */ diff --git a/firmware/octoclock/include/lwip/autoip.h b/firmware/octoclock/include/lwip/autoip.h new file mode 100644 index 000000000..076a2ed23 --- /dev/null +++ b/firmware/octoclock/include/lwip/autoip.h @@ -0,0 +1,105 @@ +/** + * @file + * + * AutoIP Automatic LinkLocal IP Configuration + */ + +/* + * + * Copyright (c) 2007 Dominik Spies <kontakt@dspies.de> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Dominik Spies <kontakt@dspies.de> + * + * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform + * with RFC 3927. + * + * + * Please coordinate changes and requests with Dominik Spies + * <kontakt@dspies.de> + */ + +#ifndef __LWIP_AUTOIP_H__ +#define __LWIP_AUTOIP_H__ + +#include "lwip/opt.h" + +#if LWIP_AUTOIP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/netif.h" +#include "lwip/udp.h" +#include "netif/etharp.h" + +/* AutoIP Timing */ +#define AUTOIP_TMR_INTERVAL 100 +#define AUTOIP_TICKS_PER_SECOND (1000 / AUTOIP_TMR_INTERVAL) + +/* RFC 3927 Constants */ +#define PROBE_WAIT 1 /* second (initial random delay) */ +#define PROBE_MIN 1 /* second (minimum delay till repeated probe) */ +#define PROBE_MAX 2 /* seconds (maximum delay till repeated probe) */ +#define PROBE_NUM 3 /* (number of probe packets) */ +#define ANNOUNCE_NUM 2 /* (number of announcement packets) */ +#define ANNOUNCE_INTERVAL 2 /* seconds (time between announcement packets) */ +#define ANNOUNCE_WAIT 2 /* seconds (delay before announcing) */ +#define MAX_CONFLICTS 10 /* (max conflicts before rate limiting) */ +#define RATE_LIMIT_INTERVAL 60 /* seconds (delay between successive attempts) */ +#define DEFEND_INTERVAL 10 /* seconds (min. wait between defensive ARPs) */ + +/* AutoIP client states */ +#define AUTOIP_STATE_OFF 0 +#define AUTOIP_STATE_PROBING 1 +#define AUTOIP_STATE_ANNOUNCING 2 +#define AUTOIP_STATE_BOUND 3 + +struct autoip +{ + struct ip_addr llipaddr; /* the currently selected, probed, announced or used LL IP-Address */ + u8_t state; /* current AutoIP state machine state */ + u8_t sent_num; /* sent number of probes or announces, dependent on state */ + u16_t ttw; /* ticks to wait, tick is AUTOIP_TMR_INTERVAL long */ + u8_t lastconflict; /* ticks until a conflict can be solved by defending */ + u8_t tried_llipaddr; /* total number of probed/used Link Local IP-Addresses */ +}; + + +/** Init srand, has to be called before entering mainloop */ +void autoip_init(void); + +/** Start AutoIP client */ +err_t autoip_start(struct netif *netif); + +/** Stop AutoIP client */ +err_t autoip_stop(struct netif *netif); + +/** Handles every incoming ARP Packet, called by etharp_arp_input */ +void autoip_arp_reply(struct netif *netif, struct etharp_hdr *hdr); + +/** Has to be called in loop every AUTOIP_TMR_INTERVAL milliseconds */ +void autoip_tmr(void); + +#endif /* LWIP_AUTOIP */ + +#endif /* __LWIP_AUTOIP_H__ */ diff --git a/firmware/octoclock/include/lwip/debug.h b/firmware/octoclock/include/lwip/debug.h new file mode 100644 index 000000000..d5c4e4747 --- /dev/null +++ b/firmware/octoclock/include/lwip/debug.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __LWIP_DEBUG_H__ +#define __LWIP_DEBUG_H__ + +#include "lwip/arch.h" + +/** lower two bits indicate debug level + * - 0 off + * - 1 warning + * - 2 serious + * - 3 severe + */ +#define LWIP_DBG_LEVEL_OFF 0x00 +#define LWIP_DBG_LEVEL_WARNING 0x01 /* bad checksums, dropped packets, ... */ +#define LWIP_DBG_LEVEL_SERIOUS 0x02 /* memory allocation failures, ... */ +#define LWIP_DBG_LEVEL_SEVERE 0x03 +#define LWIP_DBG_MASK_LEVEL 0x03 + +/** flag for LWIP_DEBUGF to enable that debug message */ +#define LWIP_DBG_ON 0x80U +/** flag for LWIP_DEBUGF to disable that debug message */ +#define LWIP_DBG_OFF 0x00U + +/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */ +#define LWIP_DBG_TRACE 0x40U +/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */ +#define LWIP_DBG_STATE 0x20U +/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */ +#define LWIP_DBG_FRESH 0x10U +/** flag for LWIP_DEBUGF to halt after printing this debug message */ +#define LWIP_DBG_HALT 0x08U + +#ifndef LWIP_NOASSERT +#define LWIP_ASSERT(message, assertion) do { if(!(assertion)) \ + LWIP_PLATFORM_ASSERT(message); } while(0) +#else /* LWIP_NOASSERT */ +#define LWIP_ASSERT(message, assertion) +#endif /* LWIP_NOASSERT */ + +/** if "expression" isn't true, then print "message" and execute "handler" expression */ +#ifndef LWIP_ERROR +#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \ + LWIP_PLATFORM_ASSERT(message); handler;}} while(0) +#endif /* LWIP_ERROR */ + +#ifdef LWIP_DEBUG +/** print debug message only if debug message type is enabled... + * AND is of correct type AND is at least LWIP_DBG_LEVEL + */ +#define LWIP_DEBUGF(debug, message) do { \ + if ( \ + ((debug) & LWIP_DBG_ON) && \ + ((debug) & LWIP_DBG_TYPES_ON) && \ + ((s16_t)((debug) & LWIP_DBG_MASK_LEVEL) >= LWIP_DBG_MIN_LEVEL)) { \ + LWIP_PLATFORM_DIAG(message); \ + if ((debug) & LWIP_DBG_HALT) { \ + while(1); \ + } \ + } \ + } while(0) + +#else /* LWIP_DEBUG */ +#define LWIP_DEBUGF(debug, message) +#endif /* LWIP_DEBUG */ + +#endif /* __LWIP_DEBUG_H__ */ + diff --git a/firmware/octoclock/include/lwip/def.h b/firmware/octoclock/include/lwip/def.h new file mode 100644 index 000000000..d2ed251df --- /dev/null +++ b/firmware/octoclock/include/lwip/def.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __LWIP_DEF_H__ +#define __LWIP_DEF_H__ + +/* this might define NULL already */ +#include "lwip/arch.h" + +#define LWIP_MAX(x , y) (((x) > (y)) ? (x) : (y)) +#define LWIP_MIN(x , y) (((x) < (y)) ? (x) : (y)) + +#ifndef NULL +#define NULL ((void *)0) +#endif + + +#endif /* __LWIP_DEF_H__ */ + diff --git a/firmware/octoclock/include/lwip/dhcp.h b/firmware/octoclock/include/lwip/dhcp.h new file mode 100644 index 000000000..825dba6ec --- /dev/null +++ b/firmware/octoclock/include/lwip/dhcp.h @@ -0,0 +1,246 @@ +/** @file + */ + +#ifndef __LWIP_DHCP_H__ +#define __LWIP_DHCP_H__ + +#include "lwip/opt.h" + +#if LWIP_DHCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/netif.h" +#include "lwip/udp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** period (in seconds) of the application calling dhcp_coarse_tmr() */ +#define DHCP_COARSE_TIMER_SECS 60 +/** period (in milliseconds) of the application calling dhcp_coarse_tmr() */ +#define DHCP_COARSE_TIMER_MSECS (DHCP_COARSE_TIMER_SECS * 1000UL) +/** period (in milliseconds) of the application calling dhcp_fine_tmr() */ +#define DHCP_FINE_TIMER_MSECS 500 + +struct dhcp +{ + /** current DHCP state machine state */ + u8_t state; + /** retries of current request */ + u8_t tries; + /** transaction identifier of last sent request */ + u32_t xid; + /** our connection to the DHCP server */ + struct udp_pcb *pcb; + /** (first) pbuf of incoming msg */ + struct pbuf *p; + /** incoming msg */ + struct dhcp_msg *msg_in; + /** incoming msg options */ + struct dhcp_msg *options_in; + /** ingoing msg options length */ + u16_t options_in_len; + + struct pbuf *p_out; /* pbuf of outcoming msg */ + struct dhcp_msg *msg_out; /* outgoing msg */ + u16_t options_out_len; /* outgoing msg options length */ + u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */ + u16_t t1_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */ + u16_t t2_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */ + struct ip_addr server_ip_addr; /* dhcp server address that offered this lease */ + struct ip_addr offered_ip_addr; + struct ip_addr offered_sn_mask; + struct ip_addr offered_gw_addr; + struct ip_addr offered_bc_addr; +#define DHCP_MAX_DNS 2 + u32_t dns_count; /* actual number of DNS servers obtained */ + struct ip_addr offered_dns_addr[DHCP_MAX_DNS]; /* DNS server addresses */ + + u32_t offered_t0_lease; /* lease period (in seconds) */ + u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */ + u32_t offered_t2_rebind; /* recommended rebind time (usually 66% of lease period) */ +#if LWIP_DHCP_AUTOIP_COOP + u8_t autoip_coop_state; +#endif +/** Patch #1308 + * TODO: See dhcp.c "TODO"s + */ +#if 0 + struct ip_addr offered_si_addr; + u8_t *boot_file_name; +#endif +}; + +/* MUST be compiled with "pack structs" or equivalent! */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** minimum set of fields of any DHCP message */ +struct dhcp_msg +{ + PACK_STRUCT_FIELD(u8_t op); + PACK_STRUCT_FIELD(u8_t htype); + PACK_STRUCT_FIELD(u8_t hlen); + PACK_STRUCT_FIELD(u8_t hops); + PACK_STRUCT_FIELD(u32_t xid); + PACK_STRUCT_FIELD(u16_t secs); + PACK_STRUCT_FIELD(u16_t flags); + PACK_STRUCT_FIELD(struct ip_addr ciaddr); + PACK_STRUCT_FIELD(struct ip_addr yiaddr); + PACK_STRUCT_FIELD(struct ip_addr siaddr); + PACK_STRUCT_FIELD(struct ip_addr giaddr); +#define DHCP_CHADDR_LEN 16U + PACK_STRUCT_FIELD(u8_t chaddr[DHCP_CHADDR_LEN]); +#define DHCP_SNAME_LEN 64U + PACK_STRUCT_FIELD(u8_t sname[DHCP_SNAME_LEN]); +#define DHCP_FILE_LEN 128U + PACK_STRUCT_FIELD(u8_t file[DHCP_FILE_LEN]); + PACK_STRUCT_FIELD(u32_t cookie); +#define DHCP_MIN_OPTIONS_LEN 68U +/** make sure user does not configure this too small */ +#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN)) +# undef DHCP_OPTIONS_LEN +#endif +/** allow this to be configured in lwipopts.h, but not too small */ +#if (!defined(DHCP_OPTIONS_LEN)) +/** set this to be sufficient for your options in outgoing DHCP msgs */ +# define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN +#endif + PACK_STRUCT_FIELD(u8_t options[DHCP_OPTIONS_LEN]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/** start DHCP configuration */ +err_t dhcp_start(struct netif *netif); +/** enforce early lease renewal (not needed normally)*/ +err_t dhcp_renew(struct netif *netif); +/** release the DHCP lease, usually called before dhcp_stop()*/ +err_t dhcp_release(struct netif *netif); +/** stop DHCP configuration */ +void dhcp_stop(struct netif *netif); +/** inform server of our manual IP address */ +void dhcp_inform(struct netif *netif); + +/** if enabled, check whether the offered IP address is not in use, using ARP */ +#if DHCP_DOES_ARP_CHECK +void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr); +#endif + +/** to be called every minute */ +void dhcp_coarse_tmr(void); +/** to be called every half second */ +void dhcp_fine_tmr(void); + +/** DHCP message item offsets and length */ +#define DHCP_MSG_OFS (UDP_DATA_OFS) + #define DHCP_OP_OFS (DHCP_MSG_OFS + 0) + #define DHCP_HTYPE_OFS (DHCP_MSG_OFS + 1) + #define DHCP_HLEN_OFS (DHCP_MSG_OFS + 2) + #define DHCP_HOPS_OFS (DHCP_MSG_OFS + 3) + #define DHCP_XID_OFS (DHCP_MSG_OFS + 4) + #define DHCP_SECS_OFS (DHCP_MSG_OFS + 8) + #define DHCP_FLAGS_OFS (DHCP_MSG_OFS + 10) + #define DHCP_CIADDR_OFS (DHCP_MSG_OFS + 12) + #define DHCP_YIADDR_OFS (DHCP_MSG_OFS + 16) + #define DHCP_SIADDR_OFS (DHCP_MSG_OFS + 20) + #define DHCP_GIADDR_OFS (DHCP_MSG_OFS + 24) + #define DHCP_CHADDR_OFS (DHCP_MSG_OFS + 28) + #define DHCP_SNAME_OFS (DHCP_MSG_OFS + 44) + #define DHCP_FILE_OFS (DHCP_MSG_OFS + 108) +#define DHCP_MSG_LEN 236 + +#define DHCP_COOKIE_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN) +#define DHCP_OPTIONS_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN + 4) + +#define DHCP_CLIENT_PORT 68 +#define DHCP_SERVER_PORT 67 + +/** DHCP client states */ +#define DHCP_REQUESTING 1 +#define DHCP_INIT 2 +#define DHCP_REBOOTING 3 +#define DHCP_REBINDING 4 +#define DHCP_RENEWING 5 +#define DHCP_SELECTING 6 +#define DHCP_INFORMING 7 +#define DHCP_CHECKING 8 +#define DHCP_PERMANENT 9 +#define DHCP_BOUND 10 +/** not yet implemented #define DHCP_RELEASING 11 */ +#define DHCP_BACKING_OFF 12 +#define DHCP_OFF 13 + +/** AUTOIP cooperatation flags */ +#define DHCP_AUTOIP_COOP_STATE_OFF 0 +#define DHCP_AUTOIP_COOP_STATE_ON 1 + +#define DHCP_BOOTREQUEST 1 +#define DHCP_BOOTREPLY 2 + +#define DHCP_DISCOVER 1 +#define DHCP_OFFER 2 +#define DHCP_REQUEST 3 +#define DHCP_DECLINE 4 +#define DHCP_ACK 5 +#define DHCP_NAK 6 +#define DHCP_RELEASE 7 +#define DHCP_INFORM 8 + +#define DHCP_HTYPE_ETH 1 + +#define DHCP_HLEN_ETH 6 + +#define DHCP_BROADCAST_FLAG 15 +#define DHCP_BROADCAST_MASK (1 << DHCP_FLAG_BROADCAST) + +/** BootP options */ +#define DHCP_OPTION_PAD 0 +#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */ +#define DHCP_OPTION_ROUTER 3 +#define DHCP_OPTION_DNS_SERVER 6 +#define DHCP_OPTION_HOSTNAME 12 +#define DHCP_OPTION_IP_TTL 23 +#define DHCP_OPTION_MTU 26 +#define DHCP_OPTION_BROADCAST 28 +#define DHCP_OPTION_TCP_TTL 37 +#define DHCP_OPTION_END 255 + +/** DHCP options */ +#define DHCP_OPTION_REQUESTED_IP 50 /* RFC 2132 9.1, requested IP address */ +#define DHCP_OPTION_LEASE_TIME 51 /* RFC 2132 9.2, time in seconds, in 4 bytes */ +#define DHCP_OPTION_OVERLOAD 52 /* RFC2132 9.3, use file and/or sname field for options */ + +#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */ +#define DHCP_OPTION_MESSAGE_TYPE_LEN 1 + + +#define DHCP_OPTION_SERVER_ID 54 /* RFC 2132 9.7, server IP address */ +#define DHCP_OPTION_PARAMETER_REQUEST_LIST 55 /* RFC 2132 9.8, requested option types */ + +#define DHCP_OPTION_MAX_MSG_SIZE 57 /* RFC 2132 9.10, message size accepted >= 576 */ +#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2 + +#define DHCP_OPTION_T1 58 /* T1 renewal time */ +#define DHCP_OPTION_T2 59 /* T2 rebinding time */ +#define DHCP_OPTION_US 60 +#define DHCP_OPTION_CLIENT_ID 61 +#define DHCP_OPTION_TFTP_SERVERNAME 66 +#define DHCP_OPTION_BOOTFILE 67 + +/** possible combinations of overloading the file and sname fields with options */ +#define DHCP_OVERLOAD_NONE 0 +#define DHCP_OVERLOAD_FILE 1 +#define DHCP_OVERLOAD_SNAME 2 +#define DHCP_OVERLOAD_SNAME_FILE 3 + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_DHCP */ + +#endif /*__LWIP_DHCP_H__*/ diff --git a/firmware/octoclock/include/lwip/dns.h b/firmware/octoclock/include/lwip/dns.h new file mode 100644 index 000000000..e5f4b7a3d --- /dev/null +++ b/firmware/octoclock/include/lwip/dns.h @@ -0,0 +1,97 @@ +/** + * lwip DNS resolver header file. + + * Author: Jim Pettinato + * April 2007 + + * ported from uIP resolv.c Copyright (c) 2002-2003, Adam Dunkels. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __LWIP_DNS_H__ +#define __LWIP_DNS_H__ + +#include "lwip/opt.h" + +#if LWIP_DNS /* don't build if not configured for use in lwipopts.h */ + +/** DNS timer period */ +#define DNS_TMR_INTERVAL 1000 + +/** DNS field TYPE used for "Resource Records" */ +#define DNS_RRTYPE_A 1 /* a host address */ +#define DNS_RRTYPE_NS 2 /* an authoritative name server */ +#define DNS_RRTYPE_MD 3 /* a mail destination (Obsolete - use MX) */ +#define DNS_RRTYPE_MF 4 /* a mail forwarder (Obsolete - use MX) */ +#define DNS_RRTYPE_CNAME 5 /* the canonical name for an alias */ +#define DNS_RRTYPE_SOA 6 /* marks the start of a zone of authority */ +#define DNS_RRTYPE_MB 7 /* a mailbox domain name (EXPERIMENTAL) */ +#define DNS_RRTYPE_MG 8 /* a mail group member (EXPERIMENTAL) */ +#define DNS_RRTYPE_MR 9 /* a mail rename domain name (EXPERIMENTAL) */ +#define DNS_RRTYPE_NULL 10 /* a null RR (EXPERIMENTAL) */ +#define DNS_RRTYPE_WKS 11 /* a well known service description */ +#define DNS_RRTYPE_PTR 12 /* a domain name pointer */ +#define DNS_RRTYPE_HINFO 13 /* host information */ +#define DNS_RRTYPE_MINFO 14 /* mailbox or mail list information */ +#define DNS_RRTYPE_MX 15 /* mail exchange */ +#define DNS_RRTYPE_TXT 16 /* text strings */ + +/** DNS field CLASS used for "Resource Records" */ +#define DNS_RRCLASS_IN 1 /* the Internet */ +#define DNS_RRCLASS_CS 2 /* the CSNET class (Obsolete - used only for examples in some obsolete RFCs) */ +#define DNS_RRCLASS_CH 3 /* the CHAOS class */ +#define DNS_RRCLASS_HS 4 /* Hesiod [Dyer 87] */ +#define DNS_RRCLASS_FLUSH 0x800 /* Flush bit */ + +/** Callback which is invoked when a hostname is found. + * A function of this type must be implemented by the application using the DNS resolver. + * @param name pointer to the name that was looked up. + * @param ipaddr pointer to a struct ip_addr containing the IP address of the hostname, + * or NULL if the name could not be found (or on any other error). + * @param callback_arg a user-specified callback argument passed to dns_gethostbyname +*/ +typedef void (*dns_found_callback)(const char *name, struct ip_addr *ipaddr, void *callback_arg); + + +void dns_init(void); + +void dns_tmr(void); + +void dns_setserver(u8_t numdns, struct ip_addr *dnsserver); + +struct ip_addr dns_getserver(u8_t numdns); + +err_t dns_gethostbyname(const char *hostname, struct ip_addr *addr, + dns_found_callback found, void *callback_arg); + +#if DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC +int dns_local_removehost(const char *hostname, const struct ip_addr *addr); +err_t dns_local_addhost(const char *hostname, const struct ip_addr *addr); +#endif /* DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +#endif /* LWIP_DNS */ + +#endif /* __LWIP_DNS_H__ */ diff --git a/firmware/octoclock/include/lwip/err.h b/firmware/octoclock/include/lwip/err.h new file mode 100644 index 000000000..696764454 --- /dev/null +++ b/firmware/octoclock/include/lwip/err.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __LWIP_ERR_H__ +#define __LWIP_ERR_H__ + +#include "lwip/opt.h" +#include "lwip/arch.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** Define LWIP_ERR_T in cc.h if you want to use + * a different type for your platform (must be signed). */ +#ifdef LWIP_ERR_T +typedef LWIP_ERR_T err_t; +#else /* LWIP_ERR_T */ + typedef s8_t err_t; +#endif /* LWIP_ERR_T*/ + +/* Definitions for error constants. */ + +#define ERR_OK 0 /* No error, everything OK. */ +#define ERR_MEM -1 /* Out of memory error. */ +#define ERR_BUF -2 /* Buffer error. */ +#define ERR_TIMEOUT -3 /* Timeout. */ +#define ERR_RTE -4 /* Routing problem. */ + +#define ERR_IS_FATAL(e) ((e) < ERR_RTE) + +#define ERR_ABRT -5 /* Connection aborted. */ +#define ERR_RST -6 /* Connection reset. */ +#define ERR_CLSD -7 /* Connection closed. */ +#define ERR_CONN -8 /* Not connected. */ + +#define ERR_VAL -9 /* Illegal value. */ + +#define ERR_ARG -10 /* Illegal argument. */ + +#define ERR_USE -11 /* Address in use. */ + +#define ERR_IF -12 /* Low-level netif error */ +#define ERR_ISCONN -13 /* Already connected. */ + +#define ERR_INPROGRESS -14 /* Operation in progress */ + + +#ifdef LWIP_DEBUG +extern const char *lwip_strerr(err_t err); +#else +#define lwip_strerr(x) "" +#endif /* LWIP_DEBUG */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_ERR_H__ */ diff --git a/firmware/octoclock/include/lwip/icmp.h b/firmware/octoclock/include/lwip/icmp.h new file mode 100644 index 000000000..ff838f43a --- /dev/null +++ b/firmware/octoclock/include/lwip/icmp.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __LWIP_ICMP_H__ +#define __LWIP_ICMP_H__ + +#include "lwip/opt.h" + +#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ICMP_ER 0 /* echo reply */ +#define ICMP_DUR 3 /* destination unreachable */ +#define ICMP_SQ 4 /* source quench */ +#define ICMP_RD 5 /* redirect */ +#define ICMP_ECHO 8 /* echo */ +#define ICMP_TE 11 /* time exceeded */ +#define ICMP_PP 12 /* parameter problem */ +#define ICMP_TS 13 /* timestamp */ +#define ICMP_TSR 14 /* timestamp reply */ +#define ICMP_IRQ 15 /* information request */ +#define ICMP_IR 16 /* information reply */ + +enum icmp_dur_type { + ICMP_DUR_NET = 0, /* net unreachable */ + ICMP_DUR_HOST = 1, /* host unreachable */ + ICMP_DUR_PROTO = 2, /* protocol unreachable */ + ICMP_DUR_PORT = 3, /* port unreachable */ + ICMP_DUR_FRAG = 4, /* fragmentation needed and DF set */ + ICMP_DUR_SR = 5 /* source route failed */ +}; + +enum icmp_te_type { + ICMP_TE_TTL = 0, /* time to live exceeded in transit */ + ICMP_TE_FRAG = 1 /* fragment reassembly time exceeded */ +}; + +void icmp_input(struct pbuf *p, struct netif *inp); + +void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t); +void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t); + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +/** This is the standard ICMP header only that the u32_t data + * is splitted to two u16_t like ICMP echo needs it. + * This header is also used for other ICMP types that do not + * use the data part. + */ +PACK_STRUCT_BEGIN +struct icmp_echo_hdr { + PACK_STRUCT_FIELD(u8_t type); + PACK_STRUCT_FIELD(u8_t code); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u16_t id); + PACK_STRUCT_FIELD(u16_t seqno); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define ICMPH_TYPE(hdr) ((hdr)->type) +#define ICMPH_CODE(hdr) ((hdr)->code) + +/** Combines type and code to an u16_t */ +#define ICMPH_TYPE_SET(hdr, t) ((hdr)->type = (t)) +#define ICMPH_CODE_SET(hdr, c) ((hdr)->code = (c)) + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_ICMP */ + +#endif /* __LWIP_ICMP_H__ */ diff --git a/firmware/octoclock/include/lwip/igmp.h b/firmware/octoclock/include/lwip/igmp.h new file mode 100644 index 000000000..59c933f35 --- /dev/null +++ b/firmware/octoclock/include/lwip/igmp.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2002 CITEL Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS'' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is a contribution to the lwIP TCP/IP stack. + * The Swedish Institute of Computer Science and Adam Dunkels + * are specifically granted permission to redistribute this + * source code. +*/ + +#ifndef __LWIP_IGMP_H__ +#define __LWIP_IGMP_H__ + +#include "lwip/opt.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/pbuf.h" + +#if LWIP_IGMP /* don't build if not configured for use in lwipopts.h */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * IGMP constants + */ +#define IP_PROTO_IGMP 2 +#define IGMP_TTL 1 +#define IGMP_MINLEN 8 +#define ROUTER_ALERT 0x9404 +#define ROUTER_ALERTLEN 4 + +/* + * IGMP message types, including version number. + */ +#define IGMP_MEMB_QUERY 0x11 /* Membership query */ +#define IGMP_V1_MEMB_REPORT 0x12 /* Ver. 1 membership report */ +#define IGMP_V2_MEMB_REPORT 0x16 /* Ver. 2 membership report */ +#define IGMP_LEAVE_GROUP 0x17 /* Leave-group message */ + +/* IGMP timer */ +#define IGMP_TMR_INTERVAL 100 /* Milliseconds */ +#define IGMP_V1_DELAYING_MEMBER_TMR (1000/IGMP_TMR_INTERVAL) +#define IGMP_JOIN_DELAYING_MEMBER_TMR (500 /IGMP_TMR_INTERVAL) + +/* MAC Filter Actions */ +#define IGMP_DEL_MAC_FILTER 0 +#define IGMP_ADD_MAC_FILTER 1 + +/* Group membership states */ +#define IGMP_GROUP_NON_MEMBER 0 +#define IGMP_GROUP_DELAYING_MEMBER 1 +#define IGMP_GROUP_IDLE_MEMBER 2 + +/* + * IGMP packet format. + */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct igmp_msg { + PACK_STRUCT_FIELD(u8_t igmp_msgtype); + PACK_STRUCT_FIELD(u8_t igmp_maxresp); + PACK_STRUCT_FIELD(u16_t igmp_checksum); + PACK_STRUCT_FIELD(struct ip_addr igmp_group_address); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/* + * now a group structure - there is + * a list of groups for each interface + * these should really be linked from the interface, but + * if we keep them separate we will not affect the lwip original code + * too much + * + * There will be a group for the all systems group address but this + * will not run the state machine as it is used to kick off reports + * from all the other groups + */ + +struct igmp_group { + struct igmp_group *next; + struct netif *interface; + struct ip_addr group_address; + u8_t last_reporter_flag; /* signifies we were the last person to report */ + u8_t group_state; + u16_t timer; + u8_t use; /* counter of simultaneous uses */ +}; + + +/* Prototypes */ +void igmp_init(void); + +err_t igmp_start( struct netif *netif); + +err_t igmp_stop( struct netif *netif); + +void igmp_report_groups( struct netif *netif); + +struct igmp_group *igmp_lookfor_group( struct netif *ifp, struct ip_addr *addr); + +struct igmp_group *igmp_lookup_group( struct netif *ifp, struct ip_addr *addr); + +err_t igmp_remove_group( struct igmp_group *group); + +void igmp_input( struct pbuf *p, struct netif *inp, struct ip_addr *dest); + +err_t igmp_joingroup( struct ip_addr *ifaddr, struct ip_addr *groupaddr); + +err_t igmp_leavegroup( struct ip_addr *ifaddr, struct ip_addr *groupaddr); + +void igmp_tmr(void); + +void igmp_timeout( struct igmp_group *group); + +void igmp_start_timer( struct igmp_group *group, u8_t max_time); + +void igmp_stop_timer( struct igmp_group *group); + +void igmp_delaying_member( struct igmp_group *group, u8_t maxresp); + +err_t igmp_ip_output_if( struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, u8_t ttl, u8_t proto, struct netif *netif); + +void igmp_send( struct igmp_group *group, u8_t type); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_IGMP */ + +#endif /* __LWIP_IGMP_H__ */ diff --git a/firmware/octoclock/include/lwip/inet.h b/firmware/octoclock/include/lwip/inet.h new file mode 100644 index 000000000..ffe763d45 --- /dev/null +++ b/firmware/octoclock/include/lwip/inet.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __LWIP_INET_H__ +#define __LWIP_INET_H__ + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* For compatibility with BSD code */ +struct in_addr { + u32_t s_addr; +}; + +#define INADDR_NONE ((u32_t)0xffffffffUL) /* 255.255.255.255 */ +#define INADDR_LOOPBACK ((u32_t)0x7f000001UL) /* 127.0.0.1 */ +#define INADDR_ANY ((u32_t)0x00000000UL) /* 0.0.0.0 */ +#define INADDR_BROADCAST ((u32_t)0xffffffffUL) /* 255.255.255.255 */ + +u32_t inet_addr(const char *cp); +int inet_aton(const char *cp, struct in_addr *addr); +char *inet_ntoa(struct in_addr addr); /* returns ptr to static buffer; not reentrant! */ + +#ifdef htons +#undef htons +#endif /* htons */ +#ifdef htonl +#undef htonl +#endif /* htonl */ +#ifdef ntohs +#undef ntohs +#endif /* ntohs */ +#ifdef ntohl +#undef ntohl +#endif /* ntohl */ + +#ifndef LWIP_PLATFORM_BYTESWAP +#define LWIP_PLATFORM_BYTESWAP 0 +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_INET_H__ */ diff --git a/firmware/octoclock/include/lwip/inet_chksum.h b/firmware/octoclock/include/lwip/inet_chksum.h new file mode 100644 index 000000000..5cae59cbd --- /dev/null +++ b/firmware/octoclock/include/lwip/inet_chksum.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __LWIP_INET_CHKSUM_H__ +#define __LWIP_INET_CHKSUM_H__ + +#include "lwip/opt.h" + +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +u16_t inet_chksum(void *dataptr, u16_t len); +u16_t inet_chksum_pbuf(struct pbuf *p); +u16_t inet_chksum_pseudo(struct pbuf *p, + struct ip_addr *src, struct ip_addr *dest, + u8_t proto, u16_t proto_len); +#if LWIP_UDPLITE +u16_t inet_chksum_pseudo_partial(struct pbuf *p, + struct ip_addr *src, struct ip_addr *dest, + u8_t proto, u16_t proto_len, u16_t chksum_len); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_INET_H__ */ + diff --git a/firmware/octoclock/include/lwip/init.h b/firmware/octoclock/include/lwip/init.h new file mode 100644 index 000000000..a4dc0577f --- /dev/null +++ b/firmware/octoclock/include/lwip/init.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __LWIP_INIT_H__ +#define __LWIP_INIT_H__ + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** X.x.x: Major version of the stack */ +#define LWIP_VERSION_MAJOR 1U +/** x.X.x: Minor version of the stack */ +#define LWIP_VERSION_MINOR 3U +/** x.x.X: Revision of the stack */ +#define LWIP_VERSION_REVISION 1U +/** For release candidates, this is set to 1..254 + * For official releases, this is set to 255 (LWIP_RC_RELEASE) + * For development versions (CVS), this is set to 0 (LWIP_RC_DEVELOPMENT) */ +#define LWIP_VERSION_RC 255U + +/** LWIP_VERSION_RC is set to LWIP_RC_RELEASE for official releases */ +#define LWIP_RC_RELEASE 255U +/** LWIP_VERSION_RC is set to LWIP_RC_DEVELOPMENT for CVS versions */ +#define LWIP_RC_DEVELOPMENT 0U + +#define LWIP_VERSION_IS_RELEASE (LWIP_VERSION_RC == LWIP_RC_RELEASE) +#define LWIP_VERSION_IS_DEVELOPMENT (LWIP_VERSION_RC == LWIP_RC_DEVELOPMENT) +#define LWIP_VERSION_IS_RC ((LWIP_VERSION_RC != LWIP_RC_RELEASE) && (LWIP_VERSION_RC != LWIP_RC_DEVELOPMENT)) + +/** Provides the version of the stack */ +#define LWIP_VERSION (LWIP_VERSION_MAJOR << 24 | LWIP_VERSION_MINOR << 16 | \ + LWIP_VERSION_REVISION << 8 | LWIP_VERSION_RC) + +/* Modules initialization */ +void lwip_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_INIT_H__ */ diff --git a/firmware/octoclock/include/lwip/ip.h b/firmware/octoclock/include/lwip/ip.h new file mode 100644 index 000000000..14eba3ca5 --- /dev/null +++ b/firmware/octoclock/include/lwip/ip.h @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __LWIP_IP_H__ +#define __LWIP_IP_H__ + +#include "lwip/opt.h" + +#include "lwip/def.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" +#include "lwip/err.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** Currently, the function ip_output_if_opt() is only used with IGMP */ +#define IP_OPTIONS_SEND LWIP_IGMP + +#define IP_HLEN 20 + +#define IP_PROTO_ICMP 1 +#define IP_PROTO_UDP 17 +#define IP_PROTO_UDPLITE 136 +#define IP_PROTO_TCP 6 + +/* This is passed as the destination address to ip_output_if (not + to ip_output), meaning that an IP header already is constructed + in the pbuf. This is used when TCP retransmits. */ +#ifdef IP_HDRINCL +#undef IP_HDRINCL +#endif /* IP_HDRINCL */ +#define IP_HDRINCL NULL + +#if LWIP_NETIF_HWADDRHINT +#define IP_PCB_ADDRHINT ;u8_t addr_hint +#else +#define IP_PCB_ADDRHINT +#endif /* LWIP_NETIF_HWADDRHINT */ + +/* This is the common part of all PCB types. It needs to be at the + beginning of a PCB type definition. It is located here so that + changes to this common part are made in one location instead of + having to change all PCB structs. */ +#define IP_PCB \ + /* ip addresses in network byte order */ \ + struct ip_addr local_ip; \ + struct ip_addr remote_ip; \ + /* Socket options */ \ + u16_t so_options; \ + /* Type Of Service */ \ + u8_t tos; \ + /* Time To Live */ \ + u8_t ttl \ + /* link layer address resolution hint */ \ + IP_PCB_ADDRHINT + +struct ip_pcb { +/* Common members of all PCB types */ + IP_PCB; +}; + +/* + * Option flags per-socket. These are the same like SO_XXX. + */ +#define SOF_DEBUG (u16_t)0x0001U /* turn on debugging info recording */ +#define SOF_ACCEPTCONN (u16_t)0x0002U /* socket has had listen() */ +#define SOF_REUSEADDR (u16_t)0x0004U /* allow local address reuse */ +#define SOF_KEEPALIVE (u16_t)0x0008U /* keep connections alive */ +#define SOF_DONTROUTE (u16_t)0x0010U /* just use interface addresses */ +#define SOF_BROADCAST (u16_t)0x0020U /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */ +#define SOF_USELOOPBACK (u16_t)0x0040U /* bypass hardware when possible */ +#define SOF_LINGER (u16_t)0x0080U /* linger on close if data present */ +#define SOF_OOBINLINE (u16_t)0x0100U /* leave received OOB data in line */ +#define SOF_REUSEPORT (u16_t)0x0200U /* allow local address & port reuse */ + + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip_hdr { + /* version / header length / type of service */ + PACK_STRUCT_FIELD(u16_t _v_hl_tos); + /* total length */ + PACK_STRUCT_FIELD(u16_t _len); + /* identification */ + PACK_STRUCT_FIELD(u16_t _id); + /* fragment offset field */ + PACK_STRUCT_FIELD(u16_t _offset); +#define IP_RF 0x8000 /* reserved fragment flag */ +#define IP_DF 0x4000 /* dont fragment flag */ +#define IP_MF 0x2000 /* more fragments flag */ +#define IP_OFFMASK 0x1fff /* mask for fragmenting bits */ + /* time to live / protocol*/ + PACK_STRUCT_FIELD(u16_t _ttl_proto); + /* checksum */ + PACK_STRUCT_FIELD(u16_t _chksum); + /* source and destination IP addresses */ + PACK_STRUCT_FIELD(struct ip_addr src); + PACK_STRUCT_FIELD(struct ip_addr dest); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define IPH_V(hdr) (ntohs((hdr)->_v_hl_tos) >> 12) +#define IPH_HL(hdr) ((ntohs((hdr)->_v_hl_tos) >> 8) & 0x0f) +#define IPH_TOS(hdr) (ntohs((hdr)->_v_hl_tos) & 0xff) +#define IPH_LEN(hdr) ((hdr)->_len) +#define IPH_ID(hdr) ((hdr)->_id) +#define IPH_OFFSET(hdr) ((hdr)->_offset) +#define IPH_TTL(hdr) (ntohs((hdr)->_ttl_proto) >> 8) +#define IPH_PROTO(hdr) (ntohs((hdr)->_ttl_proto) & 0xff) +#define IPH_CHKSUM(hdr) ((hdr)->_chksum) + +#define IPH_VHLTOS_SET(hdr, v, hl, tos) (hdr)->_v_hl_tos = (htons(((v) << 12) | ((hl) << 8) | (tos))) +#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len) +#define IPH_ID_SET(hdr, id) (hdr)->_id = (id) +#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off) +#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl_proto = (htons(IPH_PROTO(hdr) | ((u16_t)(ttl) << 8))) +#define IPH_PROTO_SET(hdr, proto) (hdr)->_ttl_proto = (htons((proto) | (IPH_TTL(hdr) << 8))) +#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum) + +#define ip_init() /* Compatibility define, not init needed. */ +struct netif *ip_route(struct ip_addr *dest); +err_t ip_input(struct pbuf *p, struct netif *inp); +err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, + u8_t ttl, u8_t tos, u8_t proto); +err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, + u8_t ttl, u8_t tos, u8_t proto, + struct netif *netif); +#if LWIP_NETIF_HWADDRHINT +err_t ip_output_hinted(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, + u8_t ttl, u8_t tos, u8_t proto, u8_t *addr_hint); +#endif /* LWIP_NETIF_HWADDRHINT */ +#if IP_OPTIONS_SEND +err_t ip_output_if_opt(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, + u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options, + u16_t optlen); +#endif /* IP_OPTIONS_SEND */ +struct netif *ip_current_netif(void); +const struct ip_hdr *ip_current_header(void); +#if IP_DEBUG +void ip_debug_print(struct pbuf *p); +#else +#define ip_debug_print(p) +#endif /* IP_DEBUG */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_IP_H__ */ + + diff --git a/firmware/octoclock/include/lwip/ip_addr.h b/firmware/octoclock/include/lwip/ip_addr.h new file mode 100644 index 000000000..f2e4c2233 --- /dev/null +++ b/firmware/octoclock/include/lwip/ip_addr.h @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __LWIP_IP_ADDR_H__ +#define __LWIP_IP_ADDR_H__ + +#include "lwip/opt.h" + +#include "lwip/inet.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip_addr { + PACK_STRUCT_FIELD(u32_t addr); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/* + * struct ipaddr2 is used in the definition of the ARP packet format in + * order to support compilers that don't have structure packing. + */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip_addr2 { + PACK_STRUCT_FIELD(u16_t addrw[2]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +struct netif; + +extern const struct ip_addr ip_addr_any; +extern const struct ip_addr ip_addr_broadcast; + +/** IP_ADDR_ can be used as a fixed IP address + * for the wildcard and the broadcast address + */ +#define IP_ADDR_ANY ((struct ip_addr *)&ip_addr_any) +#define IP_ADDR_BROADCAST ((struct ip_addr *)&ip_addr_broadcast) + +/* Definitions of the bits in an Internet address integer. + + On subnets, host and network parts are found according to + the subnet mask, not these masks. */ + +#define IN_CLASSA(a) ((((u32_t)(a)) & 0x80000000UL) == 0) +#define IN_CLASSA_NET 0xff000000 +#define IN_CLASSA_NSHIFT 24 +#define IN_CLASSA_HOST (0xffffffff & ~IN_CLASSA_NET) +#define IN_CLASSA_MAX 128 + +#define IN_CLASSB(a) ((((u32_t)(a)) & 0xc0000000UL) == 0x80000000UL) +#define IN_CLASSB_NET 0xffff0000 +#define IN_CLASSB_NSHIFT 16 +#define IN_CLASSB_HOST (0xffffffff & ~IN_CLASSB_NET) +#define IN_CLASSB_MAX 65536 + +#define IN_CLASSC(a) ((((u32_t)(a)) & 0xe0000000UL) == 0xc0000000UL) +#define IN_CLASSC_NET 0xffffff00 +#define IN_CLASSC_NSHIFT 8 +#define IN_CLASSC_HOST (0xffffffff & ~IN_CLASSC_NET) + +#define IN_CLASSD(a) (((u32_t)(a) & 0xf0000000UL) == 0xe0000000UL) +#define IN_CLASSD_NET 0xf0000000 /* These ones aren't really */ +#define IN_CLASSD_NSHIFT 28 /* net and host fields, but */ +#define IN_CLASSD_HOST 0x0fffffff /* routing needn't know. */ +#define IN_MULTICAST(a) IN_CLASSD(a) + +#define IN_EXPERIMENTAL(a) (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL) +#define IN_BADCLASS(a) (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL) + +#define IN_LOOPBACKNET 127 /* official! */ + +#define IP4_ADDR(ipaddr, a,b,c,d) \ + (ipaddr)->addr = htonl(((u32_t)((a) & 0xff) << 24) | \ + ((u32_t)((b) & 0xff) << 16) | \ + ((u32_t)((c) & 0xff) << 8) | \ + (u32_t)((d) & 0xff)) + +#define ip_addr_set(dest, src) (dest)->addr = \ + ((src) == NULL? 0:\ + (src)->addr) +/** + * Determine if two address are on the same network. + * + * @arg addr1 IP address 1 + * @arg addr2 IP address 2 + * @arg mask network identifier mask + * @return !0 if the network identifiers of both address match + */ +#define ip_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \ + (mask)->addr) == \ + ((addr2)->addr & \ + (mask)->addr)) +#define ip_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr) + +#define ip_addr_isany(addr1) ((addr1) == NULL || (addr1)->addr == 0) + +u8_t ip_addr_isbroadcast(struct ip_addr *, struct netif *); + +#define ip_addr_ismulticast(addr1) (((addr1)->addr & ntohl(0xf0000000UL)) == ntohl(0xe0000000UL)) + +#define ip_addr_islinklocal(addr1) (((addr1)->addr & ntohl(0xffff0000UL)) == ntohl(0xa9fe0000UL)) + +#define ip_addr_debug_print(debug, ipaddr) \ + LWIP_DEBUGF(debug, ("%"U16_F".%"U16_F".%"U16_F".%"U16_F, \ + ipaddr != NULL ? \ + (u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff : 0, \ + ipaddr != NULL ? \ + (u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff : 0, \ + ipaddr != NULL ? \ + (u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff : 0, \ + ipaddr != NULL ? \ + (u16_t)ntohl((ipaddr)->addr) & 0xff : 0)) + +/* These are cast to u16_t, with the intent that they are often arguments + * to printf using the U16_F format from cc.h. */ +#define ip4_addr1(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff) +#define ip4_addr2(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff) +#define ip4_addr3(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff) +#define ip4_addr4(ipaddr) ((u16_t)(ntohl((ipaddr)->addr)) & 0xff) + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_IP_ADDR_H__ */ diff --git a/firmware/octoclock/include/lwip/ip_frag.h b/firmware/octoclock/include/lwip/ip_frag.h new file mode 100644 index 000000000..380e604dc --- /dev/null +++ b/firmware/octoclock/include/lwip/ip_frag.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Jani Monoses <jani@iv.ro> + * + */ + +#ifndef __LWIP_IP_FRAG_H__ +#define __LWIP_IP_FRAG_H__ + +#include "lwip/opt.h" +#include "lwip/err.h" +#include "lwip/pbuf.h" +#include "lwip/netif.h" +#include "lwip/ip_addr.h" +#include "lwip/ip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if IP_REASSEMBLY +/* The IP reassembly timer interval in milliseconds. */ +#define IP_TMR_INTERVAL 1000 + +/* IP reassembly helper struct. + * This is exported because memp needs to know the size. + */ +struct ip_reassdata { + struct ip_reassdata *next; + struct pbuf *p; + struct ip_hdr iphdr; + u16_t datagram_len; + u8_t flags; + u8_t timer; +}; + +void ip_reass_init(void); +void ip_reass_tmr(void); +struct pbuf * ip_reass(struct pbuf *p); +#endif /* IP_REASSEMBLY */ + +#if IP_FRAG +err_t ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest); +#endif /* IP_FRAG */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_IP_FRAG_H__ */ diff --git a/firmware/octoclock/include/lwip/mem.h b/firmware/octoclock/include/lwip/mem.h new file mode 100644 index 000000000..327c2049f --- /dev/null +++ b/firmware/octoclock/include/lwip/mem.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __LWIP_MEM_H__ +#define __LWIP_MEM_H__ + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if MEM_LIBC_MALLOC + +#include <stddef.h> /* for size_t */ + +typedef size_t mem_size_t; + +/* aliases for C library malloc() */ +#define mem_init() +/* in case C library malloc() needs extra protection, + * allow these defines to be overridden. + */ +#ifndef mem_free +#define mem_free free +#endif +#ifndef mem_malloc +#define mem_malloc malloc +#endif +#ifndef mem_calloc +#define mem_calloc calloc +#endif +#ifndef mem_realloc +static void *mem_realloc(void *mem, mem_size_t size) +{ + LWIP_UNUSED_ARG(size); + return mem; +} +#endif +#else /* MEM_LIBC_MALLOC */ + +/* MEM_SIZE would have to be aligned, but using 64000 here instead of + * 65535 leaves some room for alignment... + */ +#if MEM_SIZE > 64000l +typedef u32_t mem_size_t; +#else +typedef u16_t mem_size_t; +#endif /* MEM_SIZE > 64000 */ + +#if MEM_USE_POOLS +/** mem_init is not used when using pools instead of a heap */ +#define mem_init() +/** mem_realloc is not used when using pools instead of a heap: + we can't free part of a pool element and don't want to copy the rest */ +#define mem_realloc(mem, size) (mem) +#else /* MEM_USE_POOLS */ +/* lwIP alternative malloc */ +void mem_init(void); +void *mem_realloc(void *mem, mem_size_t size); +#endif /* MEM_USE_POOLS */ +void *mem_malloc(mem_size_t size); +void *mem_calloc(mem_size_t count, mem_size_t size); +void mem_free(void *mem); +#endif /* MEM_LIBC_MALLOC */ + +#ifndef LWIP_MEM_ALIGN_SIZE +#define LWIP_MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1) & ~(MEM_ALIGNMENT-1)) +#endif + +#ifndef LWIP_MEM_ALIGN +#define LWIP_MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1))) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_MEM_H__ */ diff --git a/firmware/octoclock/include/lwip/memp.h b/firmware/octoclock/include/lwip/memp.h new file mode 100644 index 000000000..f0d073994 --- /dev/null +++ b/firmware/octoclock/include/lwip/memp.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ + +#ifndef __LWIP_MEMP_H__ +#define __LWIP_MEMP_H__ + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Create the list of all memory pools managed by memp. MEMP_MAX represents a NULL pool at the end */ +typedef enum { +#define LWIP_MEMPOOL(name,num,size,desc) MEMP_##name, +#include "lwip/memp_std.h" + MEMP_MAX +} memp_t; + +#if MEM_USE_POOLS +/* Use a helper type to get the start and end of the user "memory pools" for mem_malloc */ +typedef enum { + /* Get the first (via: + MEMP_POOL_HELPER_START = ((u8_t) 1*MEMP_POOL_A + 0*MEMP_POOL_B + 0*MEMP_POOL_C + 0)*/ + MEMP_POOL_HELPER_FIRST = ((u8_t) +#define LWIP_MEMPOOL(name,num,size,desc) +#define LWIP_MALLOC_MEMPOOL_START 1 +#define LWIP_MALLOC_MEMPOOL(num, size) * MEMP_POOL_##size + 0 +#define LWIP_MALLOC_MEMPOOL_END +#include "lwip/memp_std.h" + ) , + /* Get the last (via: + MEMP_POOL_HELPER_END = ((u8_t) 0 + MEMP_POOL_A*0 + MEMP_POOL_B*0 + MEMP_POOL_C*1) */ + MEMP_POOL_HELPER_LAST = ((u8_t) +#define LWIP_MEMPOOL(name,num,size,desc) +#define LWIP_MALLOC_MEMPOOL_START +#define LWIP_MALLOC_MEMPOOL(num, size) 0 + MEMP_POOL_##size * +#define LWIP_MALLOC_MEMPOOL_END 1 +#include "lwip/memp_std.h" + ) +} memp_pool_helper_t; + +/* The actual start and stop values are here (cast them over) + We use this helper type and these defines so we can avoid using const memp_t values */ +#define MEMP_POOL_FIRST ((memp_t) MEMP_POOL_HELPER_FIRST) +#define MEMP_POOL_LAST ((memp_t) MEMP_POOL_HELPER_LAST) +#endif /* MEM_USE_POOLS */ + +#if MEMP_MEM_MALLOC || MEM_USE_POOLS +extern const u16_t memp_sizes[MEMP_MAX]; +#endif /* MEMP_MEM_MALLOC || MEM_USE_POOLS */ + +#if MEMP_MEM_MALLOC + +#include "mem.h" + +#define memp_init() +#define memp_malloc(type) mem_malloc(memp_sizes[type]) +#define memp_free(type, mem) mem_free(mem) + +#else /* MEMP_MEM_MALLOC */ + +#if MEM_USE_POOLS +/** This structure is used to save the pool one element came from. */ +struct memp_malloc_helper +{ + memp_t poolnr; +}; +#endif /* MEM_USE_POOLS */ + +void memp_init(void); + +#if MEMP_OVERFLOW_CHECK +void *memp_malloc_fn(memp_t type, const char* file, const int line); +#define memp_malloc(t) memp_malloc_fn((t), __FILE__, __LINE__) +#else +void *memp_malloc(memp_t type); +#endif +void memp_free(memp_t type, void *mem); + +#endif /* MEMP_MEM_MALLOC */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_MEMP_H__ */ diff --git a/firmware/octoclock/include/lwip/memp_std.h b/firmware/octoclock/include/lwip/memp_std.h new file mode 100644 index 000000000..344690328 --- /dev/null +++ b/firmware/octoclock/include/lwip/memp_std.h @@ -0,0 +1,102 @@ +/* + * SETUP: Make sure we define everything we will need. + * + * We have create three types of pools: + * 1) MEMPOOL - standard pools + * 2) MALLOC_MEMPOOL - to be used by mem_malloc in mem.c + * 3) PBUF_MEMPOOL - a mempool of pbuf's, so include space for the pbuf struct + * + * If the include'r doesn't require any special treatment of each of the types + * above, then will declare #2 & #3 to be just standard mempools. + */ +#ifndef LWIP_MALLOC_MEMPOOL +/* This treats "malloc pools" just like any other pool. + The pools are a little bigger to provide 'size' as the amount of user data. */ +#define LWIP_MALLOC_MEMPOOL(num, size) LWIP_MEMPOOL(POOL_##size, num, (size + sizeof(struct memp_malloc_helper)), "MALLOC_"#size) +#define LWIP_MALLOC_MEMPOOL_START +#define LWIP_MALLOC_MEMPOOL_END +#endif /* LWIP_MALLOC_MEMPOOL */ + +#ifndef LWIP_PBUF_MEMPOOL +/* This treats "pbuf pools" just like any other pool. + * Allocates buffers for a pbuf struct AND a payload size */ +#define LWIP_PBUF_MEMPOOL(name, num, payload, desc) LWIP_MEMPOOL(name, num, (MEMP_ALIGN_SIZE(sizeof(struct pbuf)) + MEMP_ALIGN_SIZE(payload)), desc) +#endif /* LWIP_PBUF_MEMPOOL */ + + +/* + * A list of internal pools used by LWIP. + * + * LWIP_MEMPOOL(pool_name, number_elements, element_size, pool_description) + * creates a pool name MEMP_pool_name. description is used in stats.c + */ +#if LWIP_RAW +LWIP_MEMPOOL(RAW_PCB, MEMP_NUM_RAW_PCB, sizeof(struct raw_pcb), "RAW_PCB") +#endif /* LWIP_RAW */ + +#if LWIP_UDP +LWIP_MEMPOOL(UDP_PCB, MEMP_NUM_UDP_PCB, sizeof(struct udp_pcb), "UDP_PCB") +#endif /* LWIP_UDP */ + +#if LWIP_TCP +LWIP_MEMPOOL(TCP_PCB, MEMP_NUM_TCP_PCB, sizeof(struct tcp_pcb), "TCP_PCB") +LWIP_MEMPOOL(TCP_PCB_LISTEN, MEMP_NUM_TCP_PCB_LISTEN, sizeof(struct tcp_pcb_listen), "TCP_PCB_LISTEN") +LWIP_MEMPOOL(TCP_SEG, MEMP_NUM_TCP_SEG, sizeof(struct tcp_seg), "TCP_SEG") +#endif /* LWIP_TCP */ + +#if IP_REASSEMBLY +LWIP_MEMPOOL(REASSDATA, MEMP_NUM_REASSDATA, sizeof(struct ip_reassdata), "REASSDATA") +#endif /* IP_REASSEMBLY */ + +#if LWIP_NETCONN +LWIP_MEMPOOL(NETBUF, MEMP_NUM_NETBUF, sizeof(struct netbuf), "NETBUF") +LWIP_MEMPOOL(NETCONN, MEMP_NUM_NETCONN, sizeof(struct netconn), "NETCONN") +#endif /* LWIP_NETCONN */ + +#if NO_SYS==0 +LWIP_MEMPOOL(TCPIP_MSG_API, MEMP_NUM_TCPIP_MSG_API, sizeof(struct tcpip_msg), "TCPIP_MSG_API") +LWIP_MEMPOOL(TCPIP_MSG_INPKT,MEMP_NUM_TCPIP_MSG_INPKT, sizeof(struct tcpip_msg), "TCPIP_MSG_INPKT") +#endif /* NO_SYS==0 */ + +#if ARP_QUEUEING +LWIP_MEMPOOL(ARP_QUEUE, MEMP_NUM_ARP_QUEUE, sizeof(struct etharp_q_entry), "ARP_QUEUE") +#endif /* ARP_QUEUEING */ + +#if LWIP_IGMP +LWIP_MEMPOOL(IGMP_GROUP, MEMP_NUM_IGMP_GROUP, sizeof(struct igmp_group), "IGMP_GROUP") +#endif /* LWIP_IGMP */ + +#if NO_SYS==0 +LWIP_MEMPOOL(SYS_TIMEOUT, MEMP_NUM_SYS_TIMEOUT, sizeof(struct sys_timeo), "SYS_TIMEOUT") +#endif /* NO_SYS==0 */ + + +/* + * A list of pools of pbuf's used by LWIP. + * + * LWIP_PBUF_MEMPOOL(pool_name, number_elements, pbuf_payload_size, pool_description) + * creates a pool name MEMP_pool_name. description is used in stats.c + * This allocates enough space for the pbuf struct and a payload. + * (Example: pbuf_payload_size=0 allocates only size for the struct) + */ +LWIP_PBUF_MEMPOOL(PBUF, MEMP_NUM_PBUF, 0, "PBUF_REF/ROM") +LWIP_PBUF_MEMPOOL(PBUF_POOL, PBUF_POOL_SIZE, PBUF_POOL_BUFSIZE, "PBUF_POOL") + + +/* + * Allow for user-defined pools; this must be explicitly set in lwipopts.h + * since the default is to NOT look for lwippools.h + */ +#if MEMP_USE_CUSTOM_POOLS +#include "lwippools.h" +#endif /* MEMP_USE_CUSTOM_POOLS */ + +/* + * REQUIRED CLEANUP: Clear up so we don't get "multiply defined" error later + * (#undef is ignored for something that is not defined) + */ +#undef LWIP_MEMPOOL +#undef LWIP_MALLOC_MEMPOOL +#undef LWIP_MALLOC_MEMPOOL_START +#undef LWIP_MALLOC_MEMPOOL_END +#undef LWIP_PBUF_MEMPOOL diff --git a/firmware/octoclock/include/lwip/netbuf.h b/firmware/octoclock/include/lwip/netbuf.h new file mode 100644 index 000000000..6d84dd073 --- /dev/null +++ b/firmware/octoclock/include/lwip/netbuf.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __LWIP_NETBUF_H__ +#define __LWIP_NETBUF_H__ + +#include "lwip/opt.h" +#include "lwip/pbuf.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct netbuf { + struct pbuf *p, *ptr; + struct ip_addr *addr; + u16_t port; +}; + +/* Network buffer functions: */ +struct netbuf * netbuf_new (void); +void netbuf_delete (struct netbuf *buf); +void * netbuf_alloc (struct netbuf *buf, u16_t size); +void netbuf_free (struct netbuf *buf); +err_t netbuf_ref (struct netbuf *buf, + const void *dataptr, u16_t size); +void netbuf_chain (struct netbuf *head, + struct netbuf *tail); + +u16_t netbuf_len (struct netbuf *buf); +err_t netbuf_data (struct netbuf *buf, + void **dataptr, u16_t *len); +s8_t netbuf_next (struct netbuf *buf); +void netbuf_first (struct netbuf *buf); + + +#define netbuf_copy_partial(buf, dataptr, len, offset) \ + pbuf_copy_partial((buf)->p, (dataptr), (len), (offset)) +#define netbuf_copy(buf,dataptr,len) netbuf_copy_partial(buf, dataptr, len, 0) +#define netbuf_take(buf, dataptr, len) pbuf_take((buf)->p, dataptr, len) +#define netbuf_len(buf) ((buf)->p->tot_len) +#define netbuf_fromaddr(buf) ((buf)->addr) +#define netbuf_fromport(buf) ((buf)->port) + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_NETBUF_H__ */ diff --git a/firmware/octoclock/include/lwip/netdb.h b/firmware/octoclock/include/lwip/netdb.h new file mode 100644 index 000000000..0f7b2ec04 --- /dev/null +++ b/firmware/octoclock/include/lwip/netdb.h @@ -0,0 +1,111 @@ +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ + +#include "lwip/opt.h" + +#if LWIP_DNS && LWIP_SOCKET + +#include <stddef.h> /* for size_t */ + +#include "lwip/sockets.h" + +/* some rarely used options */ +#ifndef LWIP_DNS_API_DECLARE_H_ERRNO +#define LWIP_DNS_API_DECLARE_H_ERRNO 1 +#endif + +#ifndef LWIP_DNS_API_DEFINE_ERRORS +#define LWIP_DNS_API_DEFINE_ERRORS 1 +#endif + +#ifndef LWIP_DNS_API_DECLARE_STRUCTS +#define LWIP_DNS_API_DECLARE_STRUCTS 1 +#endif + +#if LWIP_DNS_API_DEFINE_ERRORS +/** Errors used by the DNS API functions, h_errno can be one of them */ +#define EAI_NONAME 200 +#define EAI_SERVICE 201 +#define EAI_FAIL 202 +#define EAI_MEMORY 203 + +#define HOST_NOT_FOUND 210 +#define NO_DATA 211 +#define NO_RECOVERY 212 +#define TRY_AGAIN 213 +#endif /* LWIP_DNS_API_DEFINE_ERRORS */ + +#if LWIP_DNS_API_DECLARE_STRUCTS +struct hostent { + char *h_name; /* Official name of the host. */ + char **h_aliases; /* A pointer to an array of pointers to alternative host names, + terminated by a null pointer. */ + int h_addrtype; /* Address type. */ + int h_length; /* The length, in bytes, of the address. */ + char **h_addr_list; /* A pointer to an array of pointers to network addresses (in + network byte order) for the host, terminated by a null pointer. */ +#define h_addr h_addr_list[0] /* for backward compatibility */ +}; + +struct addrinfo { + int ai_flags; /* Input flags. */ + int ai_family; /* Address family of socket. */ + int ai_socktype; /* Socket type. */ + int ai_protocol; /* Protocol of socket. */ + socklen_t ai_addrlen; /* Length of socket address. */ + struct sockaddr *ai_addr; /* Socket address of socket. */ + char *ai_canonname; /* Canonical name of service location. */ + struct addrinfo *ai_next; /* Pointer to next in list. */ +}; +#endif /* LWIP_DNS_API_DECLARE_STRUCTS */ + +#if LWIP_DNS_API_DECLARE_H_ERRNO +/* application accessable error code set by the DNS API functions */ +extern int h_errno; +#endif /* LWIP_DNS_API_DECLARE_H_ERRNO*/ + +struct hostent *lwip_gethostbyname(const char *name); +int lwip_gethostbyname_r(const char *name, struct hostent *ret, char *buf, + size_t buflen, struct hostent **result, int *h_errnop); +void lwip_freeaddrinfo(struct addrinfo *ai); +int lwip_getaddrinfo(const char *nodename, + const char *servname, + const struct addrinfo *hints, + struct addrinfo **res); + +#if LWIP_COMPAT_SOCKETS +#define gethostbyname(name) lwip_gethostbyname(name) +#define gethostbyname_r(name, ret, buf, buflen, result, h_errnop) \ + lwip_gethostbyname_r(name, ret, buf, buflen, result, h_errnop) +#define freeaddrinfo(addrinfo) lwip_freeaddrinfo(a) +#define getaddrinfo(nodname, servname, hints, res) \ + lwip_getaddrinfo(nodname, servname, hints, res) +#endif /* LWIP_COMPAT_SOCKETS */ + +#endif /* LWIP_DNS && LWIP_SOCKET */ diff --git a/firmware/octoclock/include/lwip/netif.h b/firmware/octoclock/include/lwip/netif.h new file mode 100644 index 000000000..a32503052 --- /dev/null +++ b/firmware/octoclock/include/lwip/netif.h @@ -0,0 +1,263 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __LWIP_NETIF_H__ +#define __LWIP_NETIF_H__ + +#include "lwip/opt.h" + +#define ENABLE_LOOPBACK (LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF) + +#include "lwip/err.h" + +#include "lwip/ip_addr.h" + +#include "lwip/inet.h" +#include "lwip/pbuf.h" +#if LWIP_DHCP +struct dhcp; +#endif +#if LWIP_AUTOIP +struct autoip; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* Throughout this file, IP addresses are expected to be in + * the same byte order as in IP_PCB. */ + +/** must be the maximum of all used hardware address lengths + across all types of interfaces in use */ +#define NETIF_MAX_HWADDR_LEN 6U + +/** TODO: define the use (where, when, whom) of netif flags */ + +/** whether the network interface is 'up'. this is + * a software flag used to control whether this network + * interface is enabled and processes traffic. + */ +#define NETIF_FLAG_UP 0x01U +/** if set, the netif has broadcast capability */ +#define NETIF_FLAG_BROADCAST 0x02U +/** if set, the netif is one end of a point-to-point connection */ +#define NETIF_FLAG_POINTTOPOINT 0x04U +/** if set, the interface is configured using DHCP */ +#define NETIF_FLAG_DHCP 0x08U +/** if set, the interface has an active link + * (set by the network interface driver) */ +#define NETIF_FLAG_LINK_UP 0x10U +/** if set, the netif is an device using ARP */ +#define NETIF_FLAG_ETHARP 0x20U +/** if set, the netif has IGMP capability */ +#define NETIF_FLAG_IGMP 0x40U + +/** Generic data structure used for all lwIP network interfaces. + * The following fields should be filled in by the initialization + * function for the device driver: hwaddr_len, hwaddr[], mtu, flags */ + +struct netif { + /** pointer to next in linked list */ + struct netif *next; + + /** IP address configuration in network byte order */ + struct ip_addr ip_addr; + struct ip_addr netmask; + struct ip_addr gw; + + /** This function is called by the network device driver + * to pass a packet up the TCP/IP stack. */ + err_t (* input)(struct pbuf *p, struct netif *inp); + /** This function is called by the IP module when it wants + * to send a packet on the interface. This function typically + * first resolves the hardware address, then sends the packet. */ + err_t (* output)(struct netif *netif, struct pbuf *p, + struct ip_addr *ipaddr); + /** This function is called by the ARP module when it wants + * to send a packet on the interface. This function outputs + * the pbuf as-is on the link medium. */ + err_t (* linkoutput)(struct netif *netif, struct pbuf *p); +#if LWIP_NETIF_STATUS_CALLBACK + /** This function is called when the netif state is set to up or down + */ + void (* status_callback)(struct netif *netif); +#endif /* LWIP_NETIF_STATUS_CALLBACK */ +#if LWIP_NETIF_LINK_CALLBACK + /** This function is called when the netif link is set to up or down + */ + void (* link_callback)(struct netif *netif); +#endif /* LWIP_NETIF_LINK_CALLBACK */ + /** This field can be set by the device driver and could point + * to state information for the device. */ + void *state; +#if LWIP_DHCP + /** the DHCP client state information for this netif */ + struct dhcp *dhcp; +#endif /* LWIP_DHCP */ +#if LWIP_AUTOIP + /** the AutoIP client state information for this netif */ + struct autoip *autoip; +#endif +#if LWIP_NETIF_HOSTNAME + /* the hostname for this netif, NULL is a valid value */ + char* hostname; +#endif /* LWIP_NETIF_HOSTNAME */ + /** number of bytes used in hwaddr */ + u8_t hwaddr_len; + /** link level hardware address of this interface */ + u8_t hwaddr[NETIF_MAX_HWADDR_LEN]; + /** maximum transfer unit (in bytes) */ + u16_t mtu; + /** flags (see NETIF_FLAG_ above) */ + u8_t flags; + /** descriptive abbreviation */ + char name[2]; + /** number of this interface */ + u8_t num; +#if LWIP_SNMP + /** link type (from "snmp_ifType" enum from snmp.h) */ + u8_t link_type; + /** (estimate) link speed */ + u32_t link_speed; + /** timestamp at last change made (up/down) */ + u32_t ts; + /** counters */ + u32_t ifinoctets; + u32_t ifinucastpkts; + u32_t ifinnucastpkts; + u32_t ifindiscards; + u32_t ifoutoctets; + u32_t ifoutucastpkts; + u32_t ifoutnucastpkts; + u32_t ifoutdiscards; +#endif /* LWIP_SNMP */ +#if LWIP_IGMP + /* This function could be called to add or delete a entry in the multicast filter table of the ethernet MAC.*/ + err_t (*igmp_mac_filter)( struct netif *netif, struct ip_addr *group, u8_t action); +#endif /* LWIP_IGMP */ +#if LWIP_NETIF_HWADDRHINT + u8_t *addr_hint; +#endif /* LWIP_NETIF_HWADDRHINT */ +#if ENABLE_LOOPBACK + /* List of packets to be queued for ourselves. */ + struct pbuf *loop_first; + struct pbuf *loop_last; +#if LWIP_LOOPBACK_MAX_PBUFS + u16_t loop_cnt_current; +#endif /* LWIP_LOOPBACK_MAX_PBUFS */ +#endif /* ENABLE_LOOPBACK */ +}; + +#if LWIP_SNMP +#define NETIF_INIT_SNMP(netif, type, speed) \ + /* use "snmp_ifType" enum from snmp.h for "type", snmp_ifType_ethernet_csmacd by example */ \ + netif->link_type = type; \ + /* your link speed here (units: bits per second) */ \ + netif->link_speed = speed; \ + netif->ts = 0; \ + netif->ifinoctets = 0; \ + netif->ifinucastpkts = 0; \ + netif->ifinnucastpkts = 0; \ + netif->ifindiscards = 0; \ + netif->ifoutoctets = 0; \ + netif->ifoutucastpkts = 0; \ + netif->ifoutnucastpkts = 0; \ + netif->ifoutdiscards = 0 +#else /* LWIP_SNMP */ +#define NETIF_INIT_SNMP(netif, type, speed) +#endif /* LWIP_SNMP */ + + +/** The list of network interfaces. */ +extern struct netif *netif_list; +/** The default network interface. */ +extern struct netif *netif_default; + +#define netif_init() /* Compatibility define, not init needed. */ + +struct netif *netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask, + struct ip_addr *gw, + void *state, + err_t (* init)(struct netif *netif), + err_t (* input)(struct pbuf *p, struct netif *netif)); + +void +netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask, + struct ip_addr *gw); +void netif_remove(struct netif * netif); + +/* Returns a network interface given its name. The name is of the form + "et0", where the first two letters are the "name" field in the + netif structure, and the digit is in the num field in the same + structure. */ +struct netif *netif_find(char *name); + +void netif_set_default(struct netif *netif); + +void netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr); +void netif_set_netmask(struct netif *netif, struct ip_addr *netmask); +void netif_set_gw(struct netif *netif, struct ip_addr *gw); + +void netif_set_up(struct netif *netif); +void netif_set_down(struct netif *netif); +u8_t netif_is_up(struct netif *netif); + +#if LWIP_NETIF_STATUS_CALLBACK +/* + * Set callback to be called when interface is brought up/down + */ +void netif_set_status_callback(struct netif *netif, void (* status_callback)(struct netif *netif)); +#endif /* LWIP_NETIF_STATUS_CALLBACK */ + +#if LWIP_NETIF_LINK_CALLBACK +void netif_set_link_up(struct netif *netif); +void netif_set_link_down(struct netif *netif); +u8_t netif_is_link_up(struct netif *netif); +/* + * Set callback to be called when link is brought up/down + */ +void netif_set_link_callback(struct netif *netif, void (* link_callback)(struct netif *netif)); +#endif /* LWIP_NETIF_LINK_CALLBACK */ + +#ifdef __cplusplus +} +#endif + +#if ENABLE_LOOPBACK +err_t netif_loop_output(struct netif *netif, struct pbuf *p, struct ip_addr *dest_ip); +void netif_poll(struct netif *netif); +#if !LWIP_NETIF_LOOPBACK_MULTITHREADING +void netif_poll_all(void); +#endif /* !LWIP_NETIF_LOOPBACK_MULTITHREADING */ +#endif /* ENABLE_LOOPBACK */ + +#endif /* __LWIP_NETIF_H__ */ diff --git a/firmware/octoclock/include/lwip/netifapi.h b/firmware/octoclock/include/lwip/netifapi.h new file mode 100644 index 000000000..36c6bd0a2 --- /dev/null +++ b/firmware/octoclock/include/lwip/netifapi.h @@ -0,0 +1,100 @@ +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +#ifndef __LWIP_NETIFAPI_H__ +#define __LWIP_NETIFAPI_H__ + +#include "lwip/opt.h" + +#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/sys.h" +#include "lwip/netif.h" +#include "lwip/dhcp.h" +#include "lwip/autoip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct netifapi_msg_msg { +#if !LWIP_TCPIP_CORE_LOCKING + sys_sem_t sem; +#endif /* !LWIP_TCPIP_CORE_LOCKING */ + err_t err; + struct netif *netif; + union { + struct { + struct ip_addr *ipaddr; + struct ip_addr *netmask; + struct ip_addr *gw; + void *state; + err_t (* init) (struct netif *netif); + err_t (* input)(struct pbuf *p, struct netif *netif); + } add; + struct { + void (* voidfunc)(struct netif *netif); + err_t (* errtfunc)(struct netif *netif); + } common; + } msg; +}; + +struct netifapi_msg { + void (* function)(struct netifapi_msg_msg *msg); + struct netifapi_msg_msg msg; +}; + + +/* API for application */ +err_t netifapi_netif_add ( struct netif *netif, + struct ip_addr *ipaddr, + struct ip_addr *netmask, + struct ip_addr *gw, + void *state, + err_t (* init)(struct netif *netif), + err_t (* input)(struct pbuf *p, struct netif *netif) ); + +err_t netifapi_netif_common ( struct netif *netif, + void (* voidfunc)(struct netif *netif), + err_t (* errtfunc)(struct netif *netif) ); + +#define netifapi_netif_remove(n) netifapi_netif_common(n, netif_remove, NULL) +#define netifapi_netif_set_up(n) netifapi_netif_common(n, netif_set_up, NULL) +#define netifapi_netif_set_down(n) netifapi_netif_common(n, netif_set_down, NULL) +#define netifapi_netif_set_default(n) netifapi_netif_common(n, netif_set_default, NULL) +#define netifapi_dhcp_start(n) netifapi_netif_common(n, NULL, dhcp_start) +#define netifapi_dhcp_stop(n) netifapi_netif_common(n, dhcp_stop, NULL) +#define netifapi_autoip_start(n) netifapi_netif_common(n, NULL, autoip_start) +#define netifapi_autoip_stop(n) netifapi_netif_common(n, NULL, autoip_stop) + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_NETIF_API */ + +#endif /* __LWIP_NETIFAPI_H__ */ diff --git a/firmware/octoclock/include/lwip/opt.h b/firmware/octoclock/include/lwip/opt.h new file mode 100644 index 000000000..e8bd8b89e --- /dev/null +++ b/firmware/octoclock/include/lwip/opt.h @@ -0,0 +1,1820 @@ +/** + * @file + * + * lwIP Options Configuration + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __LWIP_OPT_H__ +#define __LWIP_OPT_H__ + +/* + * Include user defined options first. Anything not defined in these files + * will be set to standard values. Override anything you dont like! + */ +#include "lwipopts.h" +#include "lwip/debug.h" + +/* + ----------------------------------------------- + ---------- Platform specific locking ---------- + ----------------------------------------------- +*/ + +/** + * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain + * critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#ifndef SYS_LIGHTWEIGHT_PROT +#define SYS_LIGHTWEIGHT_PROT 0 +#endif + +/** + * NO_SYS==1: Provides VERY minimal functionality. Otherwise, + * use lwIP facilities. + */ +#ifndef NO_SYS +#define NO_SYS 0 +#endif + +/** + * MEMCPY: override this if you have a faster implementation at hand than the + * one included in your C library + */ +#ifndef MEMCPY +#define MEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/** + * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a + * call to memcpy() if the length is known at compile time and is small. + */ +#ifndef SMEMCPY +#define SMEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/* + ------------------------------------ + ---------- Memory options ---------- + ------------------------------------ +*/ +/** + * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library + * instead of the lwip internal allocator. Can save code size if you + * already use it. + */ +#ifndef MEM_LIBC_MALLOC +#define MEM_LIBC_MALLOC 0 +#endif + +/** +* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator. +* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution +* speed and usage from interrupts! +*/ +#ifndef MEMP_MEM_MALLOC +#define MEMP_MEM_MALLOC 0 +#endif + +/** + * MEM_ALIGNMENT: should be set to the alignment of the CPU + * 4 byte alignment -> #define MEM_ALIGNMENT 4 + * 2 byte alignment -> #define MEM_ALIGNMENT 2 + */ +#ifndef MEM_ALIGNMENT +#define MEM_ALIGNMENT 1 +#endif + +/** + * MEM_SIZE: the size of the heap memory. If the application will send + * a lot of data that needs to be copied, this should be set high. + */ +#ifndef MEM_SIZE +#define MEM_SIZE 1600 +#endif + +/** + * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable + * amount of bytes before and after each memp element in every pool and fills + * it with a prominent default value. + * MEMP_OVERFLOW_CHECK == 0 no checking + * MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed + * MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time + * memp_malloc() or memp_free() is called (useful but slow!) + */ +#ifndef MEMP_OVERFLOW_CHECK +#define MEMP_OVERFLOW_CHECK 0 +#endif + +/** + * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make + * sure that there are no cycles in the linked lists. + */ +#ifndef MEMP_SANITY_CHECK +#define MEMP_SANITY_CHECK 0 +#endif + +/** + * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set + * of memory pools of various sizes. When mem_malloc is called, an element of + * the smallest pool that can provide the length needed is returned. + * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled. + */ +#ifndef MEM_USE_POOLS +#define MEM_USE_POOLS 0 +#endif + +/** + * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next + * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more + * reliable. */ +#ifndef MEM_USE_POOLS_TRY_BIGGER_POOL +#define MEM_USE_POOLS_TRY_BIGGER_POOL 0 +#endif + +/** + * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h + * that defines additional pools beyond the "standard" ones required + * by lwIP. If you set this to 1, you must have lwippools.h in your + * inlude path somewhere. + */ +#ifndef MEMP_USE_CUSTOM_POOLS +#define MEMP_USE_CUSTOM_POOLS 0 +#endif + +/** + * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from + * interrupt context (or another context that doesn't allow waiting for a + * semaphore). + * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT, + * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs + * with each loop so that mem_free can run. + * + * ATTENTION: As you can see from the above description, this leads to dis-/ + * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc + * can need longer. + * + * If you don't want that, at least for NO_SYS=0, you can still use the following + * functions to enqueue a deallocation call which then runs in the tcpip_thread + * context: + * - pbuf_free_callback(p); + * - mem_free_callback(m); + */ +#ifndef LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT +#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0 +#endif + +/* + ------------------------------------------------ + ---------- Internal Memory Pool Sizes ---------- + ------------------------------------------------ +*/ +/** + * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF). + * If the application sends a lot of data out of ROM (or other static memory), + * this should be set high. + */ +#ifndef MEMP_NUM_PBUF +#define MEMP_NUM_PBUF 16 +#endif + +/** + * MEMP_NUM_RAW_PCB: Number of raw connection PCBs + * (requires the LWIP_RAW option) + */ +#ifndef MEMP_NUM_RAW_PCB +#define MEMP_NUM_RAW_PCB 4 +#endif + +/** + * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + * per active UDP "connection". + * (requires the LWIP_UDP option) + */ +#ifndef MEMP_NUM_UDP_PCB +#define MEMP_NUM_UDP_PCB 4 +#endif + +/** + * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB +#define MEMP_NUM_TCP_PCB 5 +#endif + +/** + * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB_LISTEN +#define MEMP_NUM_TCP_PCB_LISTEN 8 +#endif + +/** + * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_SEG +#define MEMP_NUM_TCP_SEG 16 +#endif + +/** + * MEMP_NUM_REASSDATA: the number of simultaneously IP packets queued for + * reassembly (whole packets, not fragments!) + */ +#ifndef MEMP_NUM_REASSDATA +#define MEMP_NUM_REASSDATA 5 +#endif + +/** + * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing + * packets (pbufs) that are waiting for an ARP request (to resolve + * their destination address) to finish. + * (requires the ARP_QUEUEING option) + */ +#ifndef MEMP_NUM_ARP_QUEUE +#define MEMP_NUM_ARP_QUEUE 30 +#endif + +/** + * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces + * can be members et the same time (one per netif - allsystems group -, plus one + * per netif membership). + * (requires the LWIP_IGMP option) + */ +#ifndef MEMP_NUM_IGMP_GROUP +#define MEMP_NUM_IGMP_GROUP 8 +#endif + +/** + * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts. + * (requires NO_SYS==0) + */ +#ifndef MEMP_NUM_SYS_TIMEOUT +#define MEMP_NUM_SYS_TIMEOUT 3 +#endif + +/** + * MEMP_NUM_NETBUF: the number of struct netbufs. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETBUF +#define MEMP_NUM_NETBUF 2 +#endif + +/** + * MEMP_NUM_NETCONN: the number of struct netconns. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETCONN +#define MEMP_NUM_NETCONN 4 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used + * for callback/timeout API communication. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_API +#define MEMP_NUM_TCPIP_MSG_API 8 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used + * for incoming packets. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_INPKT +#define MEMP_NUM_TCPIP_MSG_INPKT 8 +#endif + +/** + * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. + */ +#ifndef PBUF_POOL_SIZE +#define PBUF_POOL_SIZE 16 +#endif + +/* + --------------------------------- + ---------- ARP options ---------- + --------------------------------- +*/ +/** + * LWIP_ARP==1: Enable ARP functionality. + */ +#ifndef LWIP_ARP +#define LWIP_ARP 1 +#endif + +/** + * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached. + */ +#ifndef ARP_TABLE_SIZE +#define ARP_TABLE_SIZE 10 +#endif + +/** + * ARP_QUEUEING==1: Outgoing packets are queued during hardware address + * resolution. + */ +#ifndef ARP_QUEUEING +#define ARP_QUEUEING 1 +#endif + +/** + * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be + * updated with the source MAC and IP addresses supplied in the packet. + * You may want to disable this if you do not trust LAN peers to have the + * correct addresses, or as a limited approach to attempt to handle + * spoofing. If disabled, lwIP will need to make a new ARP request if + * the peer is not already in the ARP table, adding a little latency. + */ +#ifndef ETHARP_TRUST_IP_MAC +#define ETHARP_TRUST_IP_MAC 1 +#endif + +/* + -------------------------------- + ---------- IP options ---------- + -------------------------------- +*/ +/** + * IP_FORWARD==1: Enables the ability to forward IP packets across network + * interfaces. If you are going to run lwIP on a device with only one network + * interface, define this to 0. + */ +#ifndef IP_FORWARD +#define IP_FORWARD 0 +#endif + +/** + * IP_OPTIONS_ALLOWED: Defines the behavior for IP options. + * IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped. + * IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed). + */ +#ifndef IP_OPTIONS_ALLOWED +#define IP_OPTIONS_ALLOWED 1 +#endif + +/** + * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that + * this option does not affect outgoing packet sizes, which can be controlled + * via IP_FRAG. + */ +#ifndef IP_REASSEMBLY +#define IP_REASSEMBLY 1 +#endif + +/** + * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note + * that this option does not affect incoming packet sizes, which can be + * controlled via IP_REASSEMBLY. + */ +#ifndef IP_FRAG +#define IP_FRAG 1 +#endif + +/** + * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally) + * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived + * in this time, the whole packet is discarded. + */ +#ifndef IP_REASS_MAXAGE +#define IP_REASS_MAXAGE 3 +#endif + +/** + * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled. + * Since the received pbufs are enqueued, be sure to configure + * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive + * packets even if the maximum amount of fragments is enqueued for reassembly! + */ +#ifndef IP_REASS_MAX_PBUFS +#define IP_REASS_MAX_PBUFS 10 +#endif + +/** + * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP + * fragmentation. Otherwise pbufs are allocated and reference the original + * packet data to be fragmented. + */ +#ifndef IP_FRAG_USES_STATIC_BUF +#define IP_FRAG_USES_STATIC_BUF 1 +#endif + +/** + * IP_FRAG_MAX_MTU: Assumed max MTU on any interface for IP frag buffer + * (requires IP_FRAG_USES_STATIC_BUF==1) + */ +#if IP_FRAG_USES_STATIC_BUF && !defined(IP_FRAG_MAX_MTU) +#define IP_FRAG_MAX_MTU 1500 +#endif + +/** + * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers. + */ +#ifndef IP_DEFAULT_TTL +#define IP_DEFAULT_TTL 255 +#endif + +/** + * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast + * filter per pcb on udp and raw send operations. To enable broadcast filter + * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1. + */ +#ifndef IP_SOF_BROADCAST +#define IP_SOF_BROADCAST 0 +#endif + +/** + * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast + * filter on recv operations. + */ +#ifndef IP_SOF_BROADCAST_RECV +#define IP_SOF_BROADCAST_RECV 0 +#endif + +/* + ---------------------------------- + ---------- ICMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_ICMP==1: Enable ICMP module inside the IP stack. + * Be careful, disable that make your product non-compliant to RFC1122 + */ +#ifndef LWIP_ICMP +#define LWIP_ICMP 1 +#endif + +/** + * ICMP_TTL: Default value for Time-To-Live used by ICMP packets. + */ +#ifndef ICMP_TTL +#define ICMP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only) + */ +#ifndef LWIP_BROADCAST_PING +#define LWIP_BROADCAST_PING 0 +#endif + +/** + * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only) + */ +#ifndef LWIP_MULTICAST_PING +#define LWIP_MULTICAST_PING 0 +#endif + +/* + --------------------------------- + ---------- RAW options ---------- + --------------------------------- +*/ +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef LWIP_RAW +#define LWIP_RAW 1 +#endif + +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef RAW_TTL +#define RAW_TTL (IP_DEFAULT_TTL) +#endif + +/* + ---------------------------------- + ---------- DHCP options ---------- + ---------------------------------- +*/ +/** + * LWIP_DHCP==1: Enable DHCP module. + */ +#ifndef LWIP_DHCP +#define LWIP_DHCP 0 +#endif + +/** + * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address. + */ +#ifndef DHCP_DOES_ARP_CHECK +#define DHCP_DOES_ARP_CHECK ((LWIP_DHCP) && (LWIP_ARP)) +#endif + +/* + ------------------------------------ + ---------- AUTOIP options ---------- + ------------------------------------ +*/ +/** + * LWIP_AUTOIP==1: Enable AUTOIP module. + */ +#ifndef LWIP_AUTOIP +#define LWIP_AUTOIP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on + * the same interface at the same time. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP +#define LWIP_DHCP_AUTOIP_COOP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes + * that should be sent before falling back on AUTOIP. This can be set + * as low as 1 to get an AutoIP address very quickly, but you should + * be prepared to handle a changing IP address when DHCP overrides + * AutoIP. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP_TRIES +#define LWIP_DHCP_AUTOIP_COOP_TRIES 9 +#endif + +/* + ---------------------------------- + ---------- SNMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_SNMP==1: Turn on SNMP module. UDP must be available for SNMP + * transport. + */ +#ifndef LWIP_SNMP +#define LWIP_SNMP 0 +#endif + +/** + * SNMP_CONCURRENT_REQUESTS: Number of concurrent requests the module will + * allow. At least one request buffer is required. + */ +#ifndef SNMP_CONCURRENT_REQUESTS +#define SNMP_CONCURRENT_REQUESTS 1 +#endif + +/** + * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap + * destination is required + */ +#ifndef SNMP_TRAP_DESTINATIONS +#define SNMP_TRAP_DESTINATIONS 1 +#endif + +/** + * SNMP_PRIVATE_MIB: + */ +#ifndef SNMP_PRIVATE_MIB +#define SNMP_PRIVATE_MIB 0 +#endif + +/** + * Only allow SNMP write actions that are 'safe' (e.g. disabeling netifs is not + * a safe action and disabled when SNMP_SAFE_REQUESTS = 1). + * Unsafe requests are disabled by default! + */ +#ifndef SNMP_SAFE_REQUESTS +#define SNMP_SAFE_REQUESTS 1 +#endif + +/* + ---------------------------------- + ---------- IGMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_IGMP==1: Turn on IGMP module. + */ +#ifndef LWIP_IGMP +#define LWIP_IGMP 0 +#endif + +/* + ---------------------------------- + ---------- DNS options ----------- + ---------------------------------- +*/ +/** + * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS + * transport. + */ +#ifndef LWIP_DNS +#define LWIP_DNS 0 +#endif + +/** DNS maximum number of entries to maintain locally. */ +#ifndef DNS_TABLE_SIZE +#define DNS_TABLE_SIZE 4 +#endif + +/** DNS maximum host name length supported in the name table. */ +#ifndef DNS_MAX_NAME_LENGTH +#define DNS_MAX_NAME_LENGTH 256 +#endif + +/** The maximum of DNS servers */ +#ifndef DNS_MAX_SERVERS +#define DNS_MAX_SERVERS 2 +#endif + +/** DNS do a name checking between the query and the response. */ +#ifndef DNS_DOES_NAME_CHECK +#define DNS_DOES_NAME_CHECK 1 +#endif + +/** DNS use a local buffer if DNS_USES_STATIC_BUF=0, a static one if + DNS_USES_STATIC_BUF=1, or a dynamic one if DNS_USES_STATIC_BUF=2. + The buffer will be of size DNS_MSG_SIZE */ +#ifndef DNS_USES_STATIC_BUF +#define DNS_USES_STATIC_BUF 1 +#endif + +/** DNS message max. size. Default value is RFC compliant. */ +#ifndef DNS_MSG_SIZE +#define DNS_MSG_SIZE 512 +#endif + +/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled, + * you have to define + * #define DNS_LOCAL_HOSTLIST_INIT {{"host1", 0x123}, {"host2", 0x234}} + * (an array of structs name/address, where address is an u32_t in network + * byte order). + * + * Instead, you can also use an external function: + * #define DNS_LOOKUP_LOCAL_EXTERN(x) extern u32_t my_lookup_function(const char *name) + * that returns the IP address or INADDR_NONE if not found. + */ +#ifndef DNS_LOCAL_HOSTLIST +#define DNS_LOCAL_HOSTLIST 0 +#endif /* DNS_LOCAL_HOSTLIST */ + +/** If this is turned on, the local host-list can be dynamically changed + * at runtime. */ +#ifndef DNS_LOCAL_HOSTLIST_IS_DYNAMIC +#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC 0 +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +/* + --------------------------------- + ---------- UDP options ---------- + --------------------------------- +*/ +/** + * LWIP_UDP==1: Turn on UDP. + */ +#ifndef LWIP_UDP +#define LWIP_UDP 1 +#endif + +/** + * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP) + */ +#ifndef LWIP_UDPLITE +#define LWIP_UDPLITE 0 +#endif + +/** + * UDP_TTL: Default Time-To-Live value. + */ +#ifndef UDP_TTL +#define UDP_TTL (IP_DEFAULT_TTL) +#endif + +/* + --------------------------------- + ---------- TCP options ---------- + --------------------------------- +*/ +/** + * LWIP_TCP==1: Turn on TCP. + */ +#ifndef LWIP_TCP +#define LWIP_TCP 1 +#endif + +/** + * TCP_TTL: Default Time-To-Live value. + */ +#ifndef TCP_TTL +#define TCP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * TCP_WND: The size of a TCP window. This must be at least + * (2 * TCP_MSS) for things to work well + */ +#ifndef TCP_WND +#define TCP_WND 2048 +#endif + +/** + * TCP_MAXRTX: Maximum number of retransmissions of data segments. + */ +#ifndef TCP_MAXRTX +#define TCP_MAXRTX 12 +#endif + +/** + * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments. + */ +#ifndef TCP_SYNMAXRTX +#define TCP_SYNMAXRTX 6 +#endif + +/** + * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order. + * Define to 0 if your device is low on memory. + */ +#ifndef TCP_QUEUE_OOSEQ +#define TCP_QUEUE_OOSEQ (LWIP_TCP) +#endif + +/** + * TCP_MSS: TCP Maximum segment size. (default is 128, a *very* + * conservative default.) + * For the receive side, this MSS is advertised to the remote side + * when opening a connection. For the transmit size, this MSS sets + * an upper limit on the MSS advertised by the remote host. + */ +#ifndef TCP_MSS +#define TCP_MSS 128 +#endif + +/** + * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really + * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which + * reflects the available reassembly buffer size at the remote host) and the + * largest size permitted by the IP layer" (RFC 1122) + * Setting this to 1 enables code that checks TCP_MSS against the MTU of the + * netif used for a connection and limits the MSS if it would be too big otherwise. + */ +#ifndef TCP_CALCULATE_EFF_SEND_MSS +#define TCP_CALCULATE_EFF_SEND_MSS 1 +#endif + + +/** + * TCP_SND_BUF: TCP sender buffer space (bytes). + */ +#ifndef TCP_SND_BUF +#define TCP_SND_BUF 256 +#endif + +/** + * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least + * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. + */ +#ifndef TCP_SND_QUEUELEN +#define TCP_SND_QUEUELEN (4 * (TCP_SND_BUF/TCP_MSS)) +#endif + +/** + * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than or equal + * to TCP_SND_BUF. It is the amount of space which must be available in the + * TCP snd_buf for select to return writable. + */ +#ifndef TCP_SNDLOWAT +#define TCP_SNDLOWAT (TCP_SND_BUF/2) +#endif + +/** + * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb. + */ +#ifndef TCP_LISTEN_BACKLOG +#define TCP_LISTEN_BACKLOG 0 +#endif + +/** + * The maximum allowed backlog for TCP listen netconns. + * This backlog is used unless another is explicitly specified. + * 0xff is the maximum (u8_t). + */ +#ifndef TCP_DEFAULT_LISTEN_BACKLOG +#define TCP_DEFAULT_LISTEN_BACKLOG 0xff +#endif + +/** + * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option. + */ +#ifndef LWIP_TCP_TIMESTAMPS +#define LWIP_TCP_TIMESTAMPS 0 +#endif + +/** + * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an + * explicit window update + */ +#ifndef TCP_WND_UPDATE_THRESHOLD +#define TCP_WND_UPDATE_THRESHOLD (TCP_WND / 4) +#endif + +/** + * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1. + * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all + * events (accept, sent, etc) that happen in the system. + * LWIP_CALLBACK_API==1: The PCB callback function is called directly + * for the event. + */ +#ifndef LWIP_EVENT_API +#define LWIP_EVENT_API 0 +#define LWIP_CALLBACK_API 1 +#else +#define LWIP_EVENT_API 1 +#define LWIP_CALLBACK_API 0 +#endif + + +/* + ---------------------------------- + ---------- Pbuf options ---------- + ---------------------------------- +*/ +/** + * PBUF_LINK_HLEN: the number of bytes that should be allocated for a + * link level header. The default is 14, the standard value for + * Ethernet. + */ +#ifndef PBUF_LINK_HLEN +#define PBUF_LINK_HLEN 14 +#endif + +/** + * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is + * designed to accomodate single full size TCP frame in one pbuf, including + * TCP_MSS, IP header, and link header. + */ +#ifndef PBUF_POOL_BUFSIZE +#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN) +#endif + +/* + ------------------------------------------------ + ---------- Network Interfaces options ---------- + ------------------------------------------------ +*/ +/** + * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname + * field. + */ +#ifndef LWIP_NETIF_HOSTNAME +#define LWIP_NETIF_HOSTNAME 0 +#endif + +/** + * LWIP_NETIF_API==1: Support netif api (in netifapi.c) + */ +#ifndef LWIP_NETIF_API +#define LWIP_NETIF_API 0 +#endif + +/** + * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface + * changes its up/down status (i.e., due to DHCP IP acquistion) + */ +#ifndef LWIP_NETIF_STATUS_CALLBACK +#define LWIP_NETIF_STATUS_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface + * whenever the link changes (i.e., link down) + */ +#ifndef LWIP_NETIF_LINK_CALLBACK +#define LWIP_NETIF_LINK_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table + * indices) in struct netif. TCP and UDP can make use of this to prevent + * scanning the ARP table for every sent packet. While this is faster for big + * ARP tables or many concurrent connections, it might be counterproductive + * if you have a tiny ARP table or if there never are concurrent connections. + */ +#ifndef LWIP_NETIF_HWADDRHINT +#define LWIP_NETIF_HWADDRHINT 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP + * address equal to the netif IP address, looping them back up the stack. + */ +#ifndef LWIP_NETIF_LOOPBACK +#define LWIP_NETIF_LOOPBACK 0 +#endif + +/** + * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback + * sending for each netif (0 = disabled) + */ +#ifndef LWIP_LOOPBACK_MAX_PBUFS +#define LWIP_LOOPBACK_MAX_PBUFS 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in + * the system, as netifs must change how they behave depending on this setting + * for the LWIP_NETIF_LOOPBACK option to work. + * Setting this is needed to avoid reentering non-reentrant functions like + * tcp_input(). + * LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a + * multithreaded environment like tcpip.c. In this case, netif->input() + * is called directly. + * LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup. + * The packets are put on a list and netif_poll() must be called in + * the main application loop. + */ +#ifndef LWIP_NETIF_LOOPBACK_MULTITHREADING +#define LWIP_NETIF_LOOPBACK_MULTITHREADING (!NO_SYS) +#endif + +/** + * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data + * to be sent into one single pbuf. This is for compatibility with DMA-enabled + * MACs that do not support scatter-gather. + * Beware that this might involve CPU-memcpy before transmitting that would not + * be needed without this flag! Use this only if you need to! + * + * @todo: TCP and IP-frag do not work with this, yet: + */ +#ifndef LWIP_NETIF_TX_SINGLE_PBUF +#define LWIP_NETIF_TX_SINGLE_PBUF 0 +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + +/* + ------------------------------------ + ---------- LOOPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c + */ +#ifndef LWIP_HAVE_LOOPIF +#define LWIP_HAVE_LOOPIF 0 +#endif + +/* + ------------------------------------ + ---------- SLIPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_SLIPIF==1: Support slip interface and slipif.c + */ +#ifndef LWIP_HAVE_SLIPIF +#define LWIP_HAVE_SLIPIF 0 +#endif + +/* + ------------------------------------ + ---------- Thread options ---------- + ------------------------------------ +*/ +/** + * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread. + */ +#ifndef TCPIP_THREAD_NAME +#define TCPIP_THREAD_NAME "tcpip_thread" +#endif + +/** + * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_STACKSIZE +#define TCPIP_THREAD_STACKSIZE 0 +#endif + +/** + * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_PRIO +#define TCPIP_THREAD_PRIO 1 +#endif + +/** + * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when tcpip_init is called. + */ +#ifndef TCPIP_MBOX_SIZE +#define TCPIP_MBOX_SIZE 0 +#endif + +/** + * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread. + */ +#ifndef SLIPIF_THREAD_NAME +#define SLIPIF_THREAD_NAME "slipif_loop" +#endif + +/** + * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_STACKSIZE +#define SLIPIF_THREAD_STACKSIZE 0 +#endif + +/** + * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_PRIO +#define SLIPIF_THREAD_PRIO 1 +#endif + +/** + * PPP_THREAD_NAME: The name assigned to the pppMain thread. + */ +#ifndef PPP_THREAD_NAME +#define PPP_THREAD_NAME "pppMain" +#endif + +/** + * PPP_THREAD_STACKSIZE: The stack size used by the pppMain thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_STACKSIZE +#define PPP_THREAD_STACKSIZE 0 +#endif + +/** + * PPP_THREAD_PRIO: The priority assigned to the pppMain thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_PRIO +#define PPP_THREAD_PRIO 1 +#endif + +/** + * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread. + */ +#ifndef DEFAULT_THREAD_NAME +#define DEFAULT_THREAD_NAME "lwIP" +#endif + +/** + * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_STACKSIZE +#define DEFAULT_THREAD_STACKSIZE 0 +#endif + +/** + * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_PRIO +#define DEFAULT_THREAD_PRIO 1 +#endif + +/** + * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_RAW_RECVMBOX_SIZE +#define DEFAULT_RAW_RECVMBOX_SIZE 0 +#endif + +/** + * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_UDP_RECVMBOX_SIZE +#define DEFAULT_UDP_RECVMBOX_SIZE 0 +#endif + +/** + * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_TCP_RECVMBOX_SIZE +#define DEFAULT_TCP_RECVMBOX_SIZE 0 +#endif + +/** + * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections. + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when the acceptmbox is created. + */ +#ifndef DEFAULT_ACCEPTMBOX_SIZE +#define DEFAULT_ACCEPTMBOX_SIZE 0 +#endif + +/* + ---------------------------------------------- + ---------- Sequential layer options ---------- + ---------------------------------------------- +*/ +/** + * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING +#define LWIP_TCPIP_CORE_LOCKING 0 +#endif + +/** + * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) + */ +#ifndef LWIP_NETCONN +#define LWIP_NETCONN 1 +#endif + +/* + ------------------------------------ + ---------- Socket options ---------- + ------------------------------------ +*/ +/** + * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) + */ +#ifndef LWIP_SOCKET +#define LWIP_SOCKET 1 +#endif + +/** + * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names. + * (only used if you use sockets.c) + */ +#ifndef LWIP_COMPAT_SOCKETS +#define LWIP_COMPAT_SOCKETS 1 +#endif + +/** + * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names. + * Disable this option if you use a POSIX operating system that uses the same + * names (read, write & close). (only used if you use sockets.c) + */ +#ifndef LWIP_POSIX_SOCKETS_IO_NAMES +#define LWIP_POSIX_SOCKETS_IO_NAMES 1 +#endif + +/** + * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT + * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set + * in seconds. (does not require sockets.c, and will affect tcp.c) + */ +#ifndef LWIP_TCP_KEEPALIVE +#define LWIP_TCP_KEEPALIVE 0 +#endif + +/** + * LWIP_SO_RCVTIMEO==1: Enable SO_RCVTIMEO processing. + */ +#ifndef LWIP_SO_RCVTIMEO +#define LWIP_SO_RCVTIMEO 0 +#endif + +/** + * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing. + */ +#ifndef LWIP_SO_RCVBUF +#define LWIP_SO_RCVBUF 0 +#endif + +/** + * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize. + */ +#ifndef RECV_BUFSIZE_DEFAULT +#define RECV_BUFSIZE_DEFAULT INT_MAX +#endif + +/** + * SO_REUSE==1: Enable SO_REUSEADDR and SO_REUSEPORT options. DO NOT USE! + */ +#ifndef SO_REUSE +#define SO_REUSE 0 +#endif + +/* + ---------------------------------------- + ---------- Statistics options ---------- + ---------------------------------------- +*/ +/** + * LWIP_STATS==1: Enable statistics collection in lwip_stats. + */ +#ifndef LWIP_STATS +#define LWIP_STATS 1 +#endif + +#if LWIP_STATS + +/** + * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions. + */ +#ifndef LWIP_STATS_DISPLAY +#define LWIP_STATS_DISPLAY 0 +#endif + +/** + * LINK_STATS==1: Enable link stats. + */ +#ifndef LINK_STATS +#define LINK_STATS 1 +#endif + +/** + * ETHARP_STATS==1: Enable etharp stats. + */ +#ifndef ETHARP_STATS +#define ETHARP_STATS (LWIP_ARP) +#endif + +/** + * IP_STATS==1: Enable IP stats. + */ +#ifndef IP_STATS +#define IP_STATS 1 +#endif + +/** + * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is + * on if using either frag or reass. + */ +#ifndef IPFRAG_STATS +#define IPFRAG_STATS (IP_REASSEMBLY || IP_FRAG) +#endif + +/** + * ICMP_STATS==1: Enable ICMP stats. + */ +#ifndef ICMP_STATS +#define ICMP_STATS 1 +#endif + +/** + * IGMP_STATS==1: Enable IGMP stats. + */ +#ifndef IGMP_STATS +#define IGMP_STATS (LWIP_IGMP) +#endif + +/** + * UDP_STATS==1: Enable UDP stats. Default is on if + * UDP enabled, otherwise off. + */ +#ifndef UDP_STATS +#define UDP_STATS (LWIP_UDP) +#endif + +/** + * TCP_STATS==1: Enable TCP stats. Default is on if TCP + * enabled, otherwise off. + */ +#ifndef TCP_STATS +#define TCP_STATS (LWIP_TCP) +#endif + +/** + * MEM_STATS==1: Enable mem.c stats. + */ +#ifndef MEM_STATS +#define MEM_STATS 1 +#endif + +/** + * MEMP_STATS==1: Enable memp.c pool stats. + */ +#ifndef MEMP_STATS +#define MEMP_STATS 1 +#endif + +/** + * SYS_STATS==1: Enable system stats (sem and mbox counts, etc). + */ +#ifndef SYS_STATS +#define SYS_STATS 1 +#endif + +#else + +#define LINK_STATS 0 +#define IP_STATS 0 +#define IPFRAG_STATS 0 +#define ICMP_STATS 0 +#define IGMP_STATS 0 +#define UDP_STATS 0 +#define TCP_STATS 0 +#define MEM_STATS 0 +#define MEMP_STATS 0 +#define SYS_STATS 0 +#define LWIP_STATS_DISPLAY 0 + +#endif /* LWIP_STATS */ + +/* + --------------------------------- + ---------- PPP options ---------- + --------------------------------- +*/ +/** + * PPP_SUPPORT==1: Enable PPP. + */ +#ifndef PPP_SUPPORT +#define PPP_SUPPORT 0 +#endif + +/** + * PPPOE_SUPPORT==1: Enable PPP Over Ethernet + */ +#ifndef PPPOE_SUPPORT +#define PPPOE_SUPPORT 0 +#endif + +/** + * PPPOS_SUPPORT==1: Enable PPP Over Serial + */ +#ifndef PPPOS_SUPPORT +#define PPPOS_SUPPORT PPP_SUPPORT +#endif + +#if PPP_SUPPORT + +/** + * NUM_PPP: Max PPP sessions. + */ +#ifndef NUM_PPP +#define NUM_PPP 1 +#endif + +/** + * PAP_SUPPORT==1: Support PAP. + */ +#ifndef PAP_SUPPORT +#define PAP_SUPPORT 0 +#endif + +/** + * CHAP_SUPPORT==1: Support CHAP. + */ +#ifndef CHAP_SUPPORT +#define CHAP_SUPPORT 0 +#endif + +/** + * MSCHAP_SUPPORT==1: Support MSCHAP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef MSCHAP_SUPPORT +#define MSCHAP_SUPPORT 0 +#endif + +/** + * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CBCP_SUPPORT +#define CBCP_SUPPORT 0 +#endif + +/** + * CCP_SUPPORT==1: Support CCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CCP_SUPPORT +#define CCP_SUPPORT 0 +#endif + +/** + * VJ_SUPPORT==1: Support VJ header compression. + */ +#ifndef VJ_SUPPORT +#define VJ_SUPPORT 0 +#endif + +/** + * MD5_SUPPORT==1: Support MD5 (see also CHAP). + */ +#ifndef MD5_SUPPORT +#define MD5_SUPPORT 0 +#endif + +/* + * Timeouts + */ +#ifndef FSM_DEFTIMEOUT +#define FSM_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef FSM_DEFMAXTERMREQS +#define FSM_DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXCONFREQS +#define FSM_DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXNAKLOOPS +#define FSM_DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */ +#endif + +#ifndef UPAP_DEFTIMEOUT +#define UPAP_DEFTIMEOUT 6 /* Timeout (seconds) for retransmitting req */ +#endif + +#ifndef UPAP_DEFREQTIME +#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */ +#endif + +#ifndef CHAP_DEFTIMEOUT +#define CHAP_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef CHAP_DEFTRANSMITS +#define CHAP_DEFTRANSMITS 10 /* max # times to send challenge */ +#endif + +/* Interval in seconds between keepalive echo requests, 0 to disable. */ +#ifndef LCP_ECHOINTERVAL +#define LCP_ECHOINTERVAL 0 +#endif + +/* Number of unanswered echo requests before failure. */ +#ifndef LCP_MAXECHOFAILS +#define LCP_MAXECHOFAILS 3 +#endif + +/* Max Xmit idle time (in jiffies) before resend flag char. */ +#ifndef PPP_MAXIDLEFLAG +#define PPP_MAXIDLEFLAG 100 +#endif + +/* + * Packet sizes + * + * Note - lcp shouldn't be allowed to negotiate stuff outside these + * limits. See lcp.h in the pppd directory. + * (XXX - these constants should simply be shared by lcp.c instead + * of living in lcp.h) + */ +#define PPP_MTU 1500 /* Default MTU (size of Info field) */ +#ifndef PPP_MAXMTU +/* #define PPP_MAXMTU 65535 - (PPP_HDRLEN + PPP_FCSLEN) */ +#define PPP_MAXMTU 1500 /* Largest MTU we allow */ +#endif +#define PPP_MINMTU 64 +#define PPP_MRU 1500 /* default MRU = max length of info field */ +#define PPP_MAXMRU 1500 /* Largest MRU we allow */ +#ifndef PPP_DEFMRU +#define PPP_DEFMRU 296 /* Try for this */ +#endif +#define PPP_MINMRU 128 /* No MRUs below this */ + + +#define MAXNAMELEN 256 /* max length of hostname or name for auth */ +#define MAXSECRETLEN 256 /* max length of password or secret */ + +#endif /* PPP_SUPPORT */ + +/* + -------------------------------------- + ---------- Checksum options ---------- + -------------------------------------- +*/ +/** + * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets. + */ +#ifndef CHECKSUM_GEN_IP +#define CHECKSUM_GEN_IP 1 +#endif + +/** + * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets. + */ +#ifndef CHECKSUM_GEN_UDP +#define CHECKSUM_GEN_UDP 1 +#endif + +/** + * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets. + */ +#ifndef CHECKSUM_GEN_TCP +#define CHECKSUM_GEN_TCP 1 +#endif + +/** + * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets. + */ +#ifndef CHECKSUM_CHECK_IP +#define CHECKSUM_CHECK_IP 1 +#endif + +/** + * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets. + */ +#ifndef CHECKSUM_CHECK_UDP +#define CHECKSUM_CHECK_UDP 1 +#endif + +/** + * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets. + */ +#ifndef CHECKSUM_CHECK_TCP +#define CHECKSUM_CHECK_TCP 1 +#endif + +/* + --------------------------------------- + ---------- Debugging options ---------- + --------------------------------------- +*/ +/** + * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is + * compared against this value. If it is smaller, then debugging + * messages are written. + */ +#ifndef LWIP_DBG_MIN_LEVEL +#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_OFF +#endif + +/** + * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable + * debug messages of certain types. + */ +#ifndef LWIP_DBG_TYPES_ON +#define LWIP_DBG_TYPES_ON LWIP_DBG_ON +#endif + +/** + * ETHARP_DEBUG: Enable debugging in etharp.c. + */ +#ifndef ETHARP_DEBUG +#define ETHARP_DEBUG LWIP_DBG_OFF +#endif + +/** + * NETIF_DEBUG: Enable debugging in netif.c. + */ +#ifndef NETIF_DEBUG +#define NETIF_DEBUG LWIP_DBG_OFF +#endif + +/** + * PBUF_DEBUG: Enable debugging in pbuf.c. + */ +#ifndef PBUF_DEBUG +#define PBUF_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_LIB_DEBUG: Enable debugging in api_lib.c. + */ +#ifndef API_LIB_DEBUG +#define API_LIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_MSG_DEBUG: Enable debugging in api_msg.c. + */ +#ifndef API_MSG_DEBUG +#define API_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SOCKETS_DEBUG: Enable debugging in sockets.c. + */ +#ifndef SOCKETS_DEBUG +#define SOCKETS_DEBUG LWIP_DBG_OFF +#endif + +/** + * ICMP_DEBUG: Enable debugging in icmp.c. + */ +#ifndef ICMP_DEBUG +#define ICMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IGMP_DEBUG: Enable debugging in igmp.c. + */ +#ifndef IGMP_DEBUG +#define IGMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * INET_DEBUG: Enable debugging in inet.c. + */ +#ifndef INET_DEBUG +#define INET_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_DEBUG: Enable debugging for IP. + */ +#ifndef IP_DEBUG +#define IP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass. + */ +#ifndef IP_REASS_DEBUG +#define IP_REASS_DEBUG LWIP_DBG_OFF +#endif + +/** + * RAW_DEBUG: Enable debugging in raw.c. + */ +#ifndef RAW_DEBUG +#define RAW_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEM_DEBUG: Enable debugging in mem.c. + */ +#ifndef MEM_DEBUG +#define MEM_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEMP_DEBUG: Enable debugging in memp.c. + */ +#ifndef MEMP_DEBUG +#define MEMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SYS_DEBUG: Enable debugging in sys.c. + */ +#ifndef SYS_DEBUG +#define SYS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_DEBUG: Enable debugging for TCP. + */ +#ifndef TCP_DEBUG +#define TCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug. + */ +#ifndef TCP_INPUT_DEBUG +#define TCP_INPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit. + */ +#ifndef TCP_FR_DEBUG +#define TCP_FR_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit + * timeout. + */ +#ifndef TCP_RTO_DEBUG +#define TCP_RTO_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_CWND_DEBUG: Enable debugging for TCP congestion window. + */ +#ifndef TCP_CWND_DEBUG +#define TCP_CWND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating. + */ +#ifndef TCP_WND_DEBUG +#define TCP_WND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions. + */ +#ifndef TCP_OUTPUT_DEBUG +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RST_DEBUG: Enable debugging for TCP with the RST message. + */ +#ifndef TCP_RST_DEBUG +#define TCP_RST_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths. + */ +#ifndef TCP_QLEN_DEBUG +#define TCP_QLEN_DEBUG LWIP_DBG_OFF +#endif + +/** + * UDP_DEBUG: Enable debugging in UDP. + */ +#ifndef UDP_DEBUG +#define UDP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCPIP_DEBUG: Enable debugging in tcpip.c. + */ +#ifndef TCPIP_DEBUG +#define TCPIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * PPP_DEBUG: Enable debugging for PPP. + */ +#ifndef PPP_DEBUG +#define PPP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SLIP_DEBUG: Enable debugging in slipif.c. + */ +#ifndef SLIP_DEBUG +#define SLIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * DHCP_DEBUG: Enable debugging in dhcp.c. + */ +#ifndef DHCP_DEBUG +#define DHCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * AUTOIP_DEBUG: Enable debugging in autoip.c. + */ +#ifndef AUTOIP_DEBUG +#define AUTOIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MSG_DEBUG: Enable debugging for SNMP messages. + */ +#ifndef SNMP_MSG_DEBUG +#define SNMP_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs. + */ +#ifndef SNMP_MIB_DEBUG +#define SNMP_MIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * DNS_DEBUG: Enable debugging for DNS. + */ +#ifndef DNS_DEBUG +#define DNS_DEBUG LWIP_DBG_OFF +#endif + +#endif /* __LWIP_OPT_H__ */ diff --git a/firmware/octoclock/include/lwip/pbuf.h b/firmware/octoclock/include/lwip/pbuf.h new file mode 100644 index 000000000..8380f65da --- /dev/null +++ b/firmware/octoclock/include/lwip/pbuf.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ + +#ifndef __LWIP_PBUF_H__ +#define __LWIP_PBUF_H__ + +#include "lwip/opt.h" +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define PBUF_TRANSPORT_HLEN 20 +#define PBUF_IP_HLEN 20 + +typedef enum { + PBUF_TRANSPORT, + PBUF_IP, + PBUF_LINK, + PBUF_RAW +} pbuf_layer; + +typedef enum { + PBUF_RAM, /* pbuf data is stored in RAM */ + PBUF_ROM, /* pbuf data is stored in ROM */ + PBUF_REF, /* pbuf comes from the pbuf pool */ + PBUF_POOL /* pbuf payload refers to RAM */ +} pbuf_type; + + +/** indicates this packet's data should be immediately passed to the application */ +#define PBUF_FLAG_PUSH 0x01U + +struct pbuf { + /** next pbuf in singly linked pbuf chain */ + struct pbuf *next; + + /** pointer to the actual data in the buffer */ + void *payload; + + /** + * total length of this buffer and all next buffers in chain + * belonging to the same packet. + * + * For non-queue packet chains this is the invariant: + * p->tot_len == p->len + (p->next? p->next->tot_len: 0) + */ + u16_t tot_len; + + /** length of this buffer */ + u16_t len; + + /** pbuf_type as u8_t instead of enum to save space */ + u8_t /*pbuf_type*/ type; + + /** misc flags */ + u8_t flags; + + /** + * the reference count always equals the number of pointers + * that refer to this pbuf. This can be pointers from an application, + * the stack itself, or pbuf->next pointers from a chain. + */ + u16_t ref; + +}; + +/* Initializes the pbuf module. This call is empty for now, but may not be in future. */ +#define pbuf_init() + +struct pbuf *pbuf_alloc(pbuf_layer l, u16_t size, pbuf_type type); +void pbuf_realloc(struct pbuf *p, u16_t size); +u8_t pbuf_header(struct pbuf *p, s16_t header_size); +void pbuf_ref(struct pbuf *p); +void pbuf_ref_chain(struct pbuf *p); +u8_t pbuf_free(struct pbuf *p); +u8_t pbuf_clen(struct pbuf *p); +void pbuf_cat(struct pbuf *head, struct pbuf *tail); +void pbuf_chain(struct pbuf *head, struct pbuf *tail); +struct pbuf *pbuf_dechain(struct pbuf *p); +err_t pbuf_copy(struct pbuf *p_to, struct pbuf *p_from); +u16_t pbuf_copy_partial(struct pbuf *p, void *dataptr, u16_t len, u16_t offset); +err_t pbuf_take(struct pbuf *buf, const void *dataptr, u16_t len); +struct pbuf *pbuf_coalesce(struct pbuf *p, pbuf_layer layer); + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_PBUF_H__ */ diff --git a/firmware/octoclock/include/lwip/raw.h b/firmware/octoclock/include/lwip/raw.h new file mode 100644 index 000000000..20b0a11bb --- /dev/null +++ b/firmware/octoclock/include/lwip/raw.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __LWIP_RAW_H__ +#define __LWIP_RAW_H__ + +#include "lwip/opt.h" + +#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/pbuf.h" +#include "lwip/inet.h" +#include "lwip/ip.h" +#include "lwip/ip_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct raw_pcb { +/* Common members of all PCB types */ + IP_PCB; + + struct raw_pcb *next; + + u8_t protocol; + + /* receive callback function + * @param arg user supplied argument (raw_pcb.recv_arg) + * @param pcb the raw_pcb which received data + * @param p the packet buffer that was received + * @param addr the remote IP address from which the packet was received + * @return 1 if the packet was 'eaten' (aka. deleted), + * 0 if the packet lives on + * If returning 1, the callback is responsible for freeing the pbuf + * if it's not used any more. + */ + u8_t (* recv)(void *arg, struct raw_pcb *pcb, struct pbuf *p, + struct ip_addr *addr); + /* user-supplied argument for the recv callback */ + void *recv_arg; +}; + +/* The following functions is the application layer interface to the + RAW code. */ +struct raw_pcb * raw_new (u8_t proto); +void raw_remove (struct raw_pcb *pcb); +err_t raw_bind (struct raw_pcb *pcb, struct ip_addr *ipaddr); +err_t raw_connect (struct raw_pcb *pcb, struct ip_addr *ipaddr); + +void raw_recv (struct raw_pcb *pcb, + u8_t (* recv)(void *arg, struct raw_pcb *pcb, + struct pbuf *p, + struct ip_addr *addr), + void *recv_arg); +err_t raw_sendto (struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr); +err_t raw_send (struct raw_pcb *pcb, struct pbuf *p); + +/* The following functions are the lower layer interface to RAW. */ +u8_t raw_input (struct pbuf *p, struct netif *inp); +#define raw_init() /* Compatibility define, not init needed. */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_RAW */ + +#endif /* __LWIP_RAW_H__ */ diff --git a/firmware/octoclock/include/lwip/sio.h b/firmware/octoclock/include/lwip/sio.h new file mode 100644 index 000000000..7d9162e49 --- /dev/null +++ b/firmware/octoclock/include/lwip/sio.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + */ + +/* + * This is the interface to the platform specific serial IO module + * It needs to be implemented by those platforms which need SLIP or PPP + */ + +#ifndef __SIO_H__ +#define __SIO_H__ + +#include "lwip/arch.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* If you want to define sio_fd_t elsewhere or differently, + define this in your cc.h file. */ +#ifndef __sio_fd_t_defined +typedef void * sio_fd_t; +#endif + +/* The following functions can be defined to something else in your cc.h file + or be implemented in your custom sio.c file. */ + +#ifndef sio_open +sio_fd_t sio_open(u8_t); +#endif + +#ifndef sio_send +void sio_send(u8_t, sio_fd_t); +#endif + +#ifndef sio_recv +u8_t sio_recv(sio_fd_t); +#endif + +#ifndef sio_read +u32_t sio_read(sio_fd_t, u8_t *, u32_t); +#endif + +#ifndef sio_write +u32_t sio_write(sio_fd_t, u8_t *, u32_t); +#endif + +#ifndef sio_read_abort +void sio_read_abort(sio_fd_t); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __SIO_H__ */ diff --git a/firmware/octoclock/include/lwip/snmp.h b/firmware/octoclock/include/lwip/snmp.h new file mode 100644 index 000000000..dd03d5d70 --- /dev/null +++ b/firmware/octoclock/include/lwip/snmp.h @@ -0,0 +1,364 @@ +/* + * Copyright (c) 2001, 2002 Leon Woestenberg <leon.woestenberg@axon.tv> + * Copyright (c) 2001, 2002 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Leon Woestenberg <leon.woestenberg@axon.tv> + * + */ +#ifndef __LWIP_SNMP_H__ +#define __LWIP_SNMP_H__ + +#include "lwip/opt.h" +#include "lwip/netif.h" +#include "lwip/udp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @see RFC1213, "MIB-II, 6. Definitions" + */ +enum snmp_ifType { + snmp_ifType_other=1, /* none of the following */ + snmp_ifType_regular1822, + snmp_ifType_hdh1822, + snmp_ifType_ddn_x25, + snmp_ifType_rfc877_x25, + snmp_ifType_ethernet_csmacd, + snmp_ifType_iso88023_csmacd, + snmp_ifType_iso88024_tokenBus, + snmp_ifType_iso88025_tokenRing, + snmp_ifType_iso88026_man, + snmp_ifType_starLan, + snmp_ifType_proteon_10Mbit, + snmp_ifType_proteon_80Mbit, + snmp_ifType_hyperchannel, + snmp_ifType_fddi, + snmp_ifType_lapb, + snmp_ifType_sdlc, + snmp_ifType_ds1, /* T-1 */ + snmp_ifType_e1, /* european equiv. of T-1 */ + snmp_ifType_basicISDN, + snmp_ifType_primaryISDN, /* proprietary serial */ + snmp_ifType_propPointToPointSerial, + snmp_ifType_ppp, + snmp_ifType_softwareLoopback, + snmp_ifType_eon, /* CLNP over IP [11] */ + snmp_ifType_ethernet_3Mbit, + snmp_ifType_nsip, /* XNS over IP */ + snmp_ifType_slip, /* generic SLIP */ + snmp_ifType_ultra, /* ULTRA technologies */ + snmp_ifType_ds3, /* T-3 */ + snmp_ifType_sip, /* SMDS */ + snmp_ifType_frame_relay +}; + +#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ + +/** SNMP "sysuptime" Interval */ +#define SNMP_SYSUPTIME_INTERVAL 10 + +/** fixed maximum length for object identifier type */ +#define LWIP_SNMP_OBJ_ID_LEN 32 + +/** internal object identifier representation */ +struct snmp_obj_id +{ + u8_t len; + s32_t id[LWIP_SNMP_OBJ_ID_LEN]; +}; + +/* system */ +void snmp_set_sysdesr(u8_t* str, u8_t* len); +void snmp_set_sysobjid(struct snmp_obj_id *oid); +void snmp_get_sysobjid_ptr(struct snmp_obj_id **oid); +void snmp_inc_sysuptime(void); +void snmp_add_sysuptime(u32_t value); +void snmp_get_sysuptime(u32_t *value); +void snmp_set_syscontact(u8_t *ocstr, u8_t *ocstrlen); +void snmp_set_sysname(u8_t *ocstr, u8_t *ocstrlen); +void snmp_set_syslocation(u8_t *ocstr, u8_t *ocstrlen); + +/* network interface */ +void snmp_add_ifinoctets(struct netif *ni, u32_t value); +void snmp_inc_ifinucastpkts(struct netif *ni); +void snmp_inc_ifinnucastpkts(struct netif *ni); +void snmp_inc_ifindiscards(struct netif *ni); +void snmp_add_ifoutoctets(struct netif *ni, u32_t value); +void snmp_inc_ifoutucastpkts(struct netif *ni); +void snmp_inc_ifoutnucastpkts(struct netif *ni); +void snmp_inc_ifoutdiscards(struct netif *ni); +void snmp_inc_iflist(void); +void snmp_dec_iflist(void); + +/* ARP (for atTable and ipNetToMediaTable) */ +void snmp_insert_arpidx_tree(struct netif *ni, struct ip_addr *ip); +void snmp_delete_arpidx_tree(struct netif *ni, struct ip_addr *ip); + +/* IP */ +void snmp_inc_ipinreceives(void); +void snmp_inc_ipinhdrerrors(void); +void snmp_inc_ipinaddrerrors(void); +void snmp_inc_ipforwdatagrams(void); +void snmp_inc_ipinunknownprotos(void); +void snmp_inc_ipindiscards(void); +void snmp_inc_ipindelivers(void); +void snmp_inc_ipoutrequests(void); +void snmp_inc_ipoutdiscards(void); +void snmp_inc_ipoutnoroutes(void); +void snmp_inc_ipreasmreqds(void); +void snmp_inc_ipreasmoks(void); +void snmp_inc_ipreasmfails(void); +void snmp_inc_ipfragoks(void); +void snmp_inc_ipfragfails(void); +void snmp_inc_ipfragcreates(void); +void snmp_inc_iproutingdiscards(void); +void snmp_insert_ipaddridx_tree(struct netif *ni); +void snmp_delete_ipaddridx_tree(struct netif *ni); +void snmp_insert_iprteidx_tree(u8_t dflt, struct netif *ni); +void snmp_delete_iprteidx_tree(u8_t dflt, struct netif *ni); + +/* ICMP */ +void snmp_inc_icmpinmsgs(void); +void snmp_inc_icmpinerrors(void); +void snmp_inc_icmpindestunreachs(void); +void snmp_inc_icmpintimeexcds(void); +void snmp_inc_icmpinparmprobs(void); +void snmp_inc_icmpinsrcquenchs(void); +void snmp_inc_icmpinredirects(void); +void snmp_inc_icmpinechos(void); +void snmp_inc_icmpinechoreps(void); +void snmp_inc_icmpintimestamps(void); +void snmp_inc_icmpintimestampreps(void); +void snmp_inc_icmpinaddrmasks(void); +void snmp_inc_icmpinaddrmaskreps(void); +void snmp_inc_icmpoutmsgs(void); +void snmp_inc_icmpouterrors(void); +void snmp_inc_icmpoutdestunreachs(void); +void snmp_inc_icmpouttimeexcds(void); +void snmp_inc_icmpoutparmprobs(void); +void snmp_inc_icmpoutsrcquenchs(void); +void snmp_inc_icmpoutredirects(void); +void snmp_inc_icmpoutechos(void); +void snmp_inc_icmpoutechoreps(void); +void snmp_inc_icmpouttimestamps(void); +void snmp_inc_icmpouttimestampreps(void); +void snmp_inc_icmpoutaddrmasks(void); +void snmp_inc_icmpoutaddrmaskreps(void); + +/* TCP */ +void snmp_inc_tcpactiveopens(void); +void snmp_inc_tcppassiveopens(void); +void snmp_inc_tcpattemptfails(void); +void snmp_inc_tcpestabresets(void); +void snmp_inc_tcpinsegs(void); +void snmp_inc_tcpoutsegs(void); +void snmp_inc_tcpretranssegs(void); +void snmp_inc_tcpinerrs(void); +void snmp_inc_tcpoutrsts(void); + +/* UDP */ +void snmp_inc_udpindatagrams(void); +void snmp_inc_udpnoports(void); +void snmp_inc_udpinerrors(void); +void snmp_inc_udpoutdatagrams(void); +void snmp_insert_udpidx_tree(struct udp_pcb *pcb); +void snmp_delete_udpidx_tree(struct udp_pcb *pcb); + +/* SNMP */ +void snmp_inc_snmpinpkts(void); +void snmp_inc_snmpoutpkts(void); +void snmp_inc_snmpinbadversions(void); +void snmp_inc_snmpinbadcommunitynames(void); +void snmp_inc_snmpinbadcommunityuses(void); +void snmp_inc_snmpinasnparseerrs(void); +void snmp_inc_snmpintoobigs(void); +void snmp_inc_snmpinnosuchnames(void); +void snmp_inc_snmpinbadvalues(void); +void snmp_inc_snmpinreadonlys(void); +void snmp_inc_snmpingenerrs(void); +void snmp_add_snmpintotalreqvars(u8_t value); +void snmp_add_snmpintotalsetvars(u8_t value); +void snmp_inc_snmpingetrequests(void); +void snmp_inc_snmpingetnexts(void); +void snmp_inc_snmpinsetrequests(void); +void snmp_inc_snmpingetresponses(void); +void snmp_inc_snmpintraps(void); +void snmp_inc_snmpouttoobigs(void); +void snmp_inc_snmpoutnosuchnames(void); +void snmp_inc_snmpoutbadvalues(void); +void snmp_inc_snmpoutgenerrs(void); +void snmp_inc_snmpoutgetrequests(void); +void snmp_inc_snmpoutgetnexts(void); +void snmp_inc_snmpoutsetrequests(void); +void snmp_inc_snmpoutgetresponses(void); +void snmp_inc_snmpouttraps(void); +void snmp_get_snmpgrpid_ptr(struct snmp_obj_id **oid); +void snmp_set_snmpenableauthentraps(u8_t *value); +void snmp_get_snmpenableauthentraps(u8_t *value); + +/* LWIP_SNMP support not available */ +/* define everything to be empty */ +#else + +/* system */ +#define snmp_set_sysdesr(str, len) +#define snmp_set_sysobjid(oid); +#define snmp_get_sysobjid_ptr(oid) +#define snmp_inc_sysuptime() +#define snmp_add_sysuptime(value) +#define snmp_get_sysuptime(value) +#define snmp_set_syscontact(ocstr, ocstrlen); +#define snmp_set_sysname(ocstr, ocstrlen); +#define snmp_set_syslocation(ocstr, ocstrlen); + +/* network interface */ +#define snmp_add_ifinoctets(ni,value) +#define snmp_inc_ifinucastpkts(ni) +#define snmp_inc_ifinnucastpkts(ni) +#define snmp_inc_ifindiscards(ni) +#define snmp_add_ifoutoctets(ni,value) +#define snmp_inc_ifoutucastpkts(ni) +#define snmp_inc_ifoutnucastpkts(ni) +#define snmp_inc_ifoutdiscards(ni) +#define snmp_inc_iflist() +#define snmp_dec_iflist() + +/* ARP */ +#define snmp_insert_arpidx_tree(ni,ip) +#define snmp_delete_arpidx_tree(ni,ip) + +/* IP */ +#define snmp_inc_ipinreceives() +#define snmp_inc_ipinhdrerrors() +#define snmp_inc_ipinaddrerrors() +#define snmp_inc_ipforwdatagrams() +#define snmp_inc_ipinunknownprotos() +#define snmp_inc_ipindiscards() +#define snmp_inc_ipindelivers() +#define snmp_inc_ipoutrequests() +#define snmp_inc_ipoutdiscards() +#define snmp_inc_ipoutnoroutes() +#define snmp_inc_ipreasmreqds() +#define snmp_inc_ipreasmoks() +#define snmp_inc_ipreasmfails() +#define snmp_inc_ipfragoks() +#define snmp_inc_ipfragfails() +#define snmp_inc_ipfragcreates() +#define snmp_inc_iproutingdiscards() +#define snmp_insert_ipaddridx_tree(ni) +#define snmp_delete_ipaddridx_tree(ni) +#define snmp_insert_iprteidx_tree(dflt, ni) +#define snmp_delete_iprteidx_tree(dflt, ni) + +/* ICMP */ +#define snmp_inc_icmpinmsgs() +#define snmp_inc_icmpinerrors() +#define snmp_inc_icmpindestunreachs() +#define snmp_inc_icmpintimeexcds() +#define snmp_inc_icmpinparmprobs() +#define snmp_inc_icmpinsrcquenchs() +#define snmp_inc_icmpinredirects() +#define snmp_inc_icmpinechos() +#define snmp_inc_icmpinechoreps() +#define snmp_inc_icmpintimestamps() +#define snmp_inc_icmpintimestampreps() +#define snmp_inc_icmpinaddrmasks() +#define snmp_inc_icmpinaddrmaskreps() +#define snmp_inc_icmpoutmsgs() +#define snmp_inc_icmpouterrors() +#define snmp_inc_icmpoutdestunreachs() +#define snmp_inc_icmpouttimeexcds() +#define snmp_inc_icmpoutparmprobs() +#define snmp_inc_icmpoutsrcquenchs() +#define snmp_inc_icmpoutredirects() +#define snmp_inc_icmpoutechos() +#define snmp_inc_icmpoutechoreps() +#define snmp_inc_icmpouttimestamps() +#define snmp_inc_icmpouttimestampreps() +#define snmp_inc_icmpoutaddrmasks() +#define snmp_inc_icmpoutaddrmaskreps() +/* TCP */ +#define snmp_inc_tcpactiveopens() +#define snmp_inc_tcppassiveopens() +#define snmp_inc_tcpattemptfails() +#define snmp_inc_tcpestabresets() +#define snmp_inc_tcpinsegs() +#define snmp_inc_tcpoutsegs() +#define snmp_inc_tcpretranssegs() +#define snmp_inc_tcpinerrs() +#define snmp_inc_tcpoutrsts() + +/* UDP */ +#define snmp_inc_udpindatagrams() +#define snmp_inc_udpnoports() +#define snmp_inc_udpinerrors() +#define snmp_inc_udpoutdatagrams() +#define snmp_insert_udpidx_tree(pcb) +#define snmp_delete_udpidx_tree(pcb) + +/* SNMP */ +#define snmp_inc_snmpinpkts() +#define snmp_inc_snmpoutpkts() +#define snmp_inc_snmpinbadversions() +#define snmp_inc_snmpinbadcommunitynames() +#define snmp_inc_snmpinbadcommunityuses() +#define snmp_inc_snmpinasnparseerrs() +#define snmp_inc_snmpintoobigs() +#define snmp_inc_snmpinnosuchnames() +#define snmp_inc_snmpinbadvalues() +#define snmp_inc_snmpinreadonlys() +#define snmp_inc_snmpingenerrs() +#define snmp_add_snmpintotalreqvars(value) +#define snmp_add_snmpintotalsetvars(value) +#define snmp_inc_snmpingetrequests() +#define snmp_inc_snmpingetnexts() +#define snmp_inc_snmpinsetrequests() +#define snmp_inc_snmpingetresponses() +#define snmp_inc_snmpintraps() +#define snmp_inc_snmpouttoobigs() +#define snmp_inc_snmpoutnosuchnames() +#define snmp_inc_snmpoutbadvalues() +#define snmp_inc_snmpoutgenerrs() +#define snmp_inc_snmpoutgetrequests() +#define snmp_inc_snmpoutgetnexts() +#define snmp_inc_snmpoutsetrequests() +#define snmp_inc_snmpoutgetresponses() +#define snmp_inc_snmpouttraps() +#define snmp_get_snmpgrpid_ptr(oid) +#define snmp_set_snmpenableauthentraps(value) +#define snmp_get_snmpenableauthentraps(value) + +#endif /* LWIP_SNMP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_SNMP_H__ */ diff --git a/firmware/octoclock/include/lwip/snmp_asn1.h b/firmware/octoclock/include/lwip/snmp_asn1.h new file mode 100644 index 000000000..8a602881f --- /dev/null +++ b/firmware/octoclock/include/lwip/snmp_asn1.h @@ -0,0 +1,101 @@ +/** + * @file + * Abstract Syntax Notation One (ISO 8824, 8825) codec. + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons <christiaan.simons@axon.tv> + */ + +#ifndef __LWIP_SNMP_ASN1_H__ +#define __LWIP_SNMP_ASN1_H__ + +#include "lwip/opt.h" +#include "lwip/err.h" +#include "lwip/pbuf.h" +#include "lwip/snmp.h" + +#if LWIP_SNMP + +#ifdef __cplusplus +extern "C" { +#endif + +#define SNMP_ASN1_UNIV (!0x80 | !0x40) +#define SNMP_ASN1_APPLIC (!0x80 | 0x40) +#define SNMP_ASN1_CONTXT ( 0x80 | !0x40) + +#define SNMP_ASN1_CONSTR (0x20) +#define SNMP_ASN1_PRIMIT (!0x20) + +/* universal tags */ +#define SNMP_ASN1_INTEG 2 +#define SNMP_ASN1_OC_STR 4 +#define SNMP_ASN1_NUL 5 +#define SNMP_ASN1_OBJ_ID 6 +#define SNMP_ASN1_SEQ 16 + +/* application specific (SNMP) tags */ +#define SNMP_ASN1_IPADDR 0 /* octet string size(4) */ +#define SNMP_ASN1_COUNTER 1 /* u32_t */ +#define SNMP_ASN1_GAUGE 2 /* u32_t */ +#define SNMP_ASN1_TIMETICKS 3 /* u32_t */ +#define SNMP_ASN1_OPAQUE 4 /* octet string */ + +/* context specific (SNMP) tags */ +#define SNMP_ASN1_PDU_GET_REQ 0 +#define SNMP_ASN1_PDU_GET_NEXT_REQ 1 +#define SNMP_ASN1_PDU_GET_RESP 2 +#define SNMP_ASN1_PDU_SET_REQ 3 +#define SNMP_ASN1_PDU_TRAP 4 + +err_t snmp_asn1_dec_type(struct pbuf *p, u16_t ofs, u8_t *type); +err_t snmp_asn1_dec_length(struct pbuf *p, u16_t ofs, u8_t *octets_used, u16_t *length); +err_t snmp_asn1_dec_u32t(struct pbuf *p, u16_t ofs, u16_t len, u32_t *value); +err_t snmp_asn1_dec_s32t(struct pbuf *p, u16_t ofs, u16_t len, s32_t *value); +err_t snmp_asn1_dec_oid(struct pbuf *p, u16_t ofs, u16_t len, struct snmp_obj_id *oid); +err_t snmp_asn1_dec_raw(struct pbuf *p, u16_t ofs, u16_t len, u16_t raw_len, u8_t *raw); + +void snmp_asn1_enc_length_cnt(u16_t length, u8_t *octets_needed); +void snmp_asn1_enc_u32t_cnt(u32_t value, u16_t *octets_needed); +void snmp_asn1_enc_s32t_cnt(s32_t value, u16_t *octets_needed); +void snmp_asn1_enc_oid_cnt(u8_t ident_len, s32_t *ident, u16_t *octets_needed); +err_t snmp_asn1_enc_type(struct pbuf *p, u16_t ofs, u8_t type); +err_t snmp_asn1_enc_length(struct pbuf *p, u16_t ofs, u16_t length); +err_t snmp_asn1_enc_u32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, u32_t value); +err_t snmp_asn1_enc_s32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, s32_t value); +err_t snmp_asn1_enc_oid(struct pbuf *p, u16_t ofs, u8_t ident_len, s32_t *ident); +err_t snmp_asn1_enc_raw(struct pbuf *p, u16_t ofs, u8_t raw_len, u8_t *raw); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_SNMP */ + +#endif /* __LWIP_SNMP_ASN1_H__ */ diff --git a/firmware/octoclock/include/lwip/snmp_msg.h b/firmware/octoclock/include/lwip/snmp_msg.h new file mode 100644 index 000000000..b2f69c4be --- /dev/null +++ b/firmware/octoclock/include/lwip/snmp_msg.h @@ -0,0 +1,311 @@ +/** + * @file + * SNMP Agent message handling structures. + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons <christiaan.simons@axon.tv> + */ + +#ifndef __LWIP_SNMP_MSG_H__ +#define __LWIP_SNMP_MSG_H__ + +#include "lwip/opt.h" +#include "lwip/snmp.h" +#include "lwip/snmp_structs.h" + +#if LWIP_SNMP + +#if SNMP_PRIVATE_MIB +#include "private_mib.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* The listen port of the SNMP agent. Clients have to make their requests to + this port. Most standard clients won't work if you change this! */ +#ifndef SNMP_IN_PORT +#define SNMP_IN_PORT 161 +#endif +/* The remote port the SNMP agent sends traps to. Most standard trap sinks won't + work if you change this! */ +#ifndef SNMP_TRAP_PORT +#define SNMP_TRAP_PORT 162 +#endif + +#define SNMP_ES_NOERROR 0 +#define SNMP_ES_TOOBIG 1 +#define SNMP_ES_NOSUCHNAME 2 +#define SNMP_ES_BADVALUE 3 +#define SNMP_ES_READONLY 4 +#define SNMP_ES_GENERROR 5 + +#define SNMP_GENTRAP_COLDSTART 0 +#define SNMP_GENTRAP_WARMSTART 1 +#define SNMP_GENTRAP_AUTHFAIL 4 +#define SNMP_GENTRAP_ENTERPRISESPC 6 + +struct snmp_varbind +{ + /* next pointer, NULL for last in list */ + struct snmp_varbind *next; + /* previous pointer, NULL for first in list */ + struct snmp_varbind *prev; + + /* object identifier length (in s32_t) */ + u8_t ident_len; + /* object identifier array */ + s32_t *ident; + + /* object value ASN1 type */ + u8_t value_type; + /* object value length (in u8_t) */ + u8_t value_len; + /* object value */ + void *value; + + /* encoding varbind seq length length */ + u8_t seqlenlen; + /* encoding object identifier length length */ + u8_t olenlen; + /* encoding object value length length */ + u8_t vlenlen; + /* encoding varbind seq length */ + u16_t seqlen; + /* encoding object identifier length */ + u16_t olen; + /* encoding object value length */ + u16_t vlen; +}; + +struct snmp_varbind_root +{ + struct snmp_varbind *head; + struct snmp_varbind *tail; + /* number of variable bindings in list */ + u8_t count; + /* encoding varbind-list seq length length */ + u8_t seqlenlen; + /* encoding varbind-list seq length */ + u16_t seqlen; +}; + +/** output response message header length fields */ +struct snmp_resp_header_lengths +{ + /* encoding error-index length length */ + u8_t erridxlenlen; + /* encoding error-status length length */ + u8_t errstatlenlen; + /* encoding request id length length */ + u8_t ridlenlen; + /* encoding pdu length length */ + u8_t pdulenlen; + /* encoding community length length */ + u8_t comlenlen; + /* encoding version length length */ + u8_t verlenlen; + /* encoding sequence length length */ + u8_t seqlenlen; + + /* encoding error-index length */ + u16_t erridxlen; + /* encoding error-status length */ + u16_t errstatlen; + /* encoding request id length */ + u16_t ridlen; + /* encoding pdu length */ + u16_t pdulen; + /* encoding community length */ + u16_t comlen; + /* encoding version length */ + u16_t verlen; + /* encoding sequence length */ + u16_t seqlen; +}; + +/** output response message header length fields */ +struct snmp_trap_header_lengths +{ + /* encoding timestamp length length */ + u8_t tslenlen; + /* encoding specific-trap length length */ + u8_t strplenlen; + /* encoding generic-trap length length */ + u8_t gtrplenlen; + /* encoding agent-addr length length */ + u8_t aaddrlenlen; + /* encoding enterprise-id length length */ + u8_t eidlenlen; + /* encoding pdu length length */ + u8_t pdulenlen; + /* encoding community length length */ + u8_t comlenlen; + /* encoding version length length */ + u8_t verlenlen; + /* encoding sequence length length */ + u8_t seqlenlen; + + /* encoding timestamp length */ + u16_t tslen; + /* encoding specific-trap length */ + u16_t strplen; + /* encoding generic-trap length */ + u16_t gtrplen; + /* encoding agent-addr length */ + u16_t aaddrlen; + /* encoding enterprise-id length */ + u16_t eidlen; + /* encoding pdu length */ + u16_t pdulen; + /* encoding community length */ + u16_t comlen; + /* encoding version length */ + u16_t verlen; + /* encoding sequence length */ + u16_t seqlen; +}; + +/* Accepting new SNMP messages. */ +#define SNMP_MSG_EMPTY 0 +/* Search for matching object for variable binding. */ +#define SNMP_MSG_SEARCH_OBJ 1 +/* Perform SNMP operation on in-memory object. + Pass-through states, for symmetry only. */ +#define SNMP_MSG_INTERNAL_GET_OBJDEF 2 +#define SNMP_MSG_INTERNAL_GET_VALUE 3 +#define SNMP_MSG_INTERNAL_SET_TEST 4 +#define SNMP_MSG_INTERNAL_GET_OBJDEF_S 5 +#define SNMP_MSG_INTERNAL_SET_VALUE 6 +/* Perform SNMP operation on object located externally. + In theory this could be used for building a proxy agent. + Practical use is for an enterprise spc. app. gateway. */ +#define SNMP_MSG_EXTERNAL_GET_OBJDEF 7 +#define SNMP_MSG_EXTERNAL_GET_VALUE 8 +#define SNMP_MSG_EXTERNAL_SET_TEST 9 +#define SNMP_MSG_EXTERNAL_GET_OBJDEF_S 10 +#define SNMP_MSG_EXTERNAL_SET_VALUE 11 + +#define SNMP_COMMUNITY_STR_LEN 64 +struct snmp_msg_pstat +{ + /* lwIP local port (161) binding */ + struct udp_pcb *pcb; + /* source IP address */ + struct ip_addr sip; + /* source UDP port */ + u16_t sp; + /* request type */ + u8_t rt; + /* request ID */ + s32_t rid; + /* error status */ + s32_t error_status; + /* error index */ + s32_t error_index; + /* community name (zero terminated) */ + u8_t community[SNMP_COMMUNITY_STR_LEN + 1]; + /* community string length (exclusive zero term) */ + u8_t com_strlen; + /* one out of MSG_EMPTY, MSG_DEMUX, MSG_INTERNAL, MSG_EXTERNAL_x */ + u8_t state; + /* saved arguments for MSG_EXTERNAL_x */ + struct mib_external_node *ext_mib_node; + struct snmp_name_ptr ext_name_ptr; + struct obj_def ext_object_def; + struct snmp_obj_id ext_oid; + /* index into input variable binding list */ + u8_t vb_idx; + /* ptr into input variable binding list */ + struct snmp_varbind *vb_ptr; + /* list of variable bindings from input */ + struct snmp_varbind_root invb; + /* list of variable bindings to output */ + struct snmp_varbind_root outvb; + /* output response lengths used in ASN encoding */ + struct snmp_resp_header_lengths rhl; +}; + +struct snmp_msg_trap +{ + /* lwIP local port (161) binding */ + struct udp_pcb *pcb; + /* destination IP address in network order */ + struct ip_addr dip; + + /* source enterprise ID (sysObjectID) */ + struct snmp_obj_id *enterprise; + /* source IP address, raw network order format */ + u8_t sip_raw[4]; + /* generic trap code */ + u32_t gen_trap; + /* specific trap code */ + u32_t spc_trap; + /* timestamp */ + u32_t ts; + /* list of variable bindings to output */ + struct snmp_varbind_root outvb; + /* output trap lengths used in ASN encoding */ + struct snmp_trap_header_lengths thl; +}; + +/** Agent Version constant, 0 = v1 oddity */ +extern const s32_t snmp_version; +/** Agent default "public" community string */ +extern const char snmp_publiccommunity[7]; + +extern struct snmp_msg_trap trap_msg; + +/** Agent setup, start listening to port 161. */ +void snmp_init(void); +void snmp_trap_dst_enable(u8_t dst_idx, u8_t enable); +void snmp_trap_dst_ip_set(u8_t dst_idx, struct ip_addr *dst); + +/** Varbind-list functions. */ +struct snmp_varbind* snmp_varbind_alloc(struct snmp_obj_id *oid, u8_t type, u8_t len); +void snmp_varbind_free(struct snmp_varbind *vb); +void snmp_varbind_list_free(struct snmp_varbind_root *root); +void snmp_varbind_tail_add(struct snmp_varbind_root *root, struct snmp_varbind *vb); +struct snmp_varbind* snmp_varbind_tail_remove(struct snmp_varbind_root *root); + +/** Handle an internal (recv) or external (private response) event. */ +void snmp_msg_event(u8_t request_id); +err_t snmp_send_response(struct snmp_msg_pstat *m_stat); +err_t snmp_send_trap(s8_t generic_trap, struct snmp_obj_id *eoid, s32_t specific_trap); +void snmp_coldstart_trap(void); +void snmp_authfail_trap(void); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_SNMP */ + +#endif /* __LWIP_SNMP_MSG_H__ */ diff --git a/firmware/octoclock/include/lwip/snmp_structs.h b/firmware/octoclock/include/lwip/snmp_structs.h new file mode 100644 index 000000000..9f3f8a94e --- /dev/null +++ b/firmware/octoclock/include/lwip/snmp_structs.h @@ -0,0 +1,262 @@ +/** + * @file + * Generic MIB tree structures. + * + * @todo namespace prefixes + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons <christiaan.simons@axon.tv> + */ + +#ifndef __LWIP_SNMP_STRUCTS_H__ +#define __LWIP_SNMP_STRUCTS_H__ + +#include "lwip/opt.h" + +#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/snmp.h" + +#if SNMP_PRIVATE_MIB +#include "private_mib.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* MIB object instance */ +#define MIB_OBJECT_NONE 0 +#define MIB_OBJECT_SCALAR 1 +#define MIB_OBJECT_TAB 2 + +/* MIB object access */ +#define MIB_OBJECT_READ_ONLY 0 +#define MIB_OBJECT_READ_WRITE 1 +#define MIB_OBJECT_WRITE_ONLY 2 +#define MIB_OBJECT_NOT_ACCESSIBLE 3 + +/** object definition returned by (get_object_def)() */ +struct obj_def +{ + /* MIB_OBJECT_NONE (0), MIB_OBJECT_SCALAR (1), MIB_OBJECT_TAB (2) */ + u8_t instance; + /* 0 read-only, 1 read-write, 2 write-only, 3 not-accessible */ + u8_t access; + /* ASN type for this object */ + u8_t asn_type; + /* value length (host length) */ + u16_t v_len; + /* length of instance part of supplied object identifier */ + u8_t id_inst_len; + /* instance part of supplied object identifier */ + s32_t *id_inst_ptr; +}; + +struct snmp_name_ptr +{ + u8_t ident_len; + s32_t *ident; +}; + +/** MIB const scalar (.0) node */ +#define MIB_NODE_SC 0x01 +/** MIB const array node */ +#define MIB_NODE_AR 0x02 +/** MIB array node (mem_malloced from RAM) */ +#define MIB_NODE_RA 0x03 +/** MIB list root node (mem_malloced from RAM) */ +#define MIB_NODE_LR 0x04 +/** MIB node for external objects */ +#define MIB_NODE_EX 0x05 + +/** node "base class" layout, the mandatory fields for a node */ +struct mib_node +{ + /** returns struct obj_def for the given object identifier */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + /** returns object value for the given object identifier, + @note the caller must allocate at least len bytes for the value */ + void (*get_value)(struct obj_def *od, u16_t len, void *value); + /** tests length and/or range BEFORE setting */ + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + /** sets object value, only to be called when set_test() */ + void (*set_value)(struct obj_def *od, u16_t len, void *value); + /** One out of MIB_NODE_AR, MIB_NODE_LR or MIB_NODE_EX */ + const u8_t node_type; + /* array or max list length */ + const u16_t maxlength; +}; + +/** derived node for scalars .0 index */ +typedef struct mib_node mib_scalar_node; + +/** derived node, points to a fixed size const array + of sub-identifiers plus a 'child' pointer */ +struct mib_array_node +{ + /* inherited "base class" members */ + void (* const get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (* const get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + const u8_t node_type; + const u16_t maxlength; + + /* aditional struct members */ + const s32_t *objid; + struct mib_node* const *nptr; +}; + +/** derived node, points to a fixed size mem_malloced array + of sub-identifiers plus a 'child' pointer */ +struct mib_ram_array_node +{ + /* inherited "base class" members */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + u8_t node_type; + u16_t maxlength; + + /* aditional struct members */ + s32_t *objid; + struct mib_node **nptr; +}; + +struct mib_list_node +{ + struct mib_list_node *prev; + struct mib_list_node *next; + s32_t objid; + struct mib_node *nptr; +}; + +/** derived node, points to a doubly linked list + of sub-identifiers plus a 'child' pointer */ +struct mib_list_rootnode +{ + /* inherited "base class" members */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + u8_t node_type; + u16_t maxlength; + + /* aditional struct members */ + struct mib_list_node *head; + struct mib_list_node *tail; + /* counts list nodes in list */ + u16_t count; +}; + +/** derived node, has access functions for mib object in external memory or device + using 'tree_level' and 'idx', with a range 0 .. (level_length() - 1) */ +struct mib_external_node +{ + /* inherited "base class" members */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + u8_t node_type; + u16_t maxlength; + + /* aditional struct members */ + /** points to an extenal (in memory) record of some sort of addressing + information, passed to and interpreted by the funtions below */ + void* addr_inf; + /** tree levels under this node */ + u8_t tree_levels; + /** number of objects at this level */ + u16_t (*level_length)(void* addr_inf, u8_t level); + /** compares object sub identifier with external id + return zero when equal, nonzero when unequal */ + s32_t (*ident_cmp)(void* addr_inf, u8_t level, u16_t idx, s32_t sub_id); + void (*get_objid)(void* addr_inf, u8_t level, u16_t idx, s32_t *sub_id); + + /** async Questions */ + void (*get_object_def_q)(void* addr_inf, u8_t rid, u8_t ident_len, s32_t *ident); + void (*get_value_q)(u8_t rid, struct obj_def *od); + void (*set_test_q)(u8_t rid, struct obj_def *od); + void (*set_value_q)(u8_t rid, struct obj_def *od, u16_t len, void *value); + /** async Answers */ + void (*get_object_def_a)(u8_t rid, u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value_a)(u8_t rid, struct obj_def *od, u16_t len, void *value); + u8_t (*set_test_a)(u8_t rid, struct obj_def *od, u16_t len, void *value); + void (*set_value_a)(u8_t rid, struct obj_def *od, u16_t len, void *value); + /** async Panic Close (agent returns error reply, + e.g. used for external transaction cleanup) */ + void (*get_object_def_pc)(u8_t rid, u8_t ident_len, s32_t *ident); + void (*get_value_pc)(u8_t rid, struct obj_def *od); + void (*set_test_pc)(u8_t rid, struct obj_def *od); + void (*set_value_pc)(u8_t rid, struct obj_def *od); +}; + +/** export MIB tree from mib2.c */ +extern const struct mib_array_node internet; + +/** dummy function pointers for non-leaf MIB nodes from mib2.c */ +void noleafs_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +void noleafs_get_value(struct obj_def *od, u16_t len, void *value); +u8_t noleafs_set_test(struct obj_def *od, u16_t len, void *value); +void noleafs_set_value(struct obj_def *od, u16_t len, void *value); + +void snmp_oidtoip(s32_t *ident, struct ip_addr *ip); +void snmp_iptooid(struct ip_addr *ip, s32_t *ident); +void snmp_ifindextonetif(s32_t ifindex, struct netif **netif); +void snmp_netiftoifindex(struct netif *netif, s32_t *ifidx); + +struct mib_list_node* snmp_mib_ln_alloc(s32_t id); +void snmp_mib_ln_free(struct mib_list_node *ln); +struct mib_list_rootnode* snmp_mib_lrn_alloc(void); +void snmp_mib_lrn_free(struct mib_list_rootnode *lrn); + +s8_t snmp_mib_node_insert(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **insn); +s8_t snmp_mib_node_find(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **fn); +struct mib_list_rootnode *snmp_mib_node_delete(struct mib_list_rootnode *rn, struct mib_list_node *n); + +struct mib_node* snmp_search_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_name_ptr *np); +struct mib_node* snmp_expand_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret); +u8_t snmp_iso_prefix_tst(u8_t ident_len, s32_t *ident); +u8_t snmp_iso_prefix_expand(u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_SNMP */ + +#endif /* __LWIP_SNMP_STRUCTS_H__ */ diff --git a/firmware/octoclock/include/lwip/sockets.h b/firmware/octoclock/include/lwip/sockets.h new file mode 100644 index 000000000..7b52e151c --- /dev/null +++ b/firmware/octoclock/include/lwip/sockets.h @@ -0,0 +1,357 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ + + +#ifndef __LWIP_SOCKETS_H__ +#define __LWIP_SOCKETS_H__ + +#include "lwip/opt.h" + +#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */ + +#include <stddef.h> /* for size_t */ + +#include "lwip/ip_addr.h" +#include "lwip/inet.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* members are in network byte order */ +struct sockaddr_in { + u8_t sin_len; + u8_t sin_family; + u16_t sin_port; + struct in_addr sin_addr; + char sin_zero[8]; +}; + +struct sockaddr { + u8_t sa_len; + u8_t sa_family; + char sa_data[14]; +}; + +#ifndef socklen_t +# define socklen_t u32_t +#endif + +/* Socket protocol types (TCP/UDP/RAW) */ +#define SOCK_STREAM 1 +#define SOCK_DGRAM 2 +#define SOCK_RAW 3 + +/* + * Option flags per-socket. These must match the SOF_ flags in ip.h! + */ +#define SO_DEBUG 0x0001 /* Unimplemented: turn on debugging info recording */ +#define SO_ACCEPTCONN 0x0002 /* socket has had listen() */ +#define SO_REUSEADDR 0x0004 /* Unimplemented: allow local address reuse */ +#define SO_KEEPALIVE 0x0008 /* keep connections alive */ +#define SO_DONTROUTE 0x0010 /* Unimplemented: just use interface addresses */ +#define SO_BROADCAST 0x0020 /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */ +#define SO_USELOOPBACK 0x0040 /* Unimplemented: bypass hardware when possible */ +#define SO_LINGER 0x0080 /* linger on close if data present */ +#define SO_OOBINLINE 0x0100 /* Unimplemented: leave received OOB data in line */ +#define SO_REUSEPORT 0x0200 /* Unimplemented: allow local address & port reuse */ + +#define SO_DONTLINGER ((int)(~SO_LINGER)) + +/* + * Additional options, not kept in so_options. + */ +#define SO_SNDBUF 0x1001 /* Unimplemented: send buffer size */ +#define SO_RCVBUF 0x1002 /* receive buffer size */ +#define SO_SNDLOWAT 0x1003 /* Unimplemented: send low-water mark */ +#define SO_RCVLOWAT 0x1004 /* Unimplemented: receive low-water mark */ +#define SO_SNDTIMEO 0x1005 /* Unimplemented: send timeout */ +#define SO_RCVTIMEO 0x1006 /* receive timeout */ +#define SO_ERROR 0x1007 /* get error status and clear */ +#define SO_TYPE 0x1008 /* get socket type */ +#define SO_CONTIMEO 0x1009 /* Unimplemented: connect timeout */ +#define SO_NO_CHECK 0x100a /* don't create UDP checksum */ + + +/* + * Structure used for manipulating linger option. + */ +struct linger { + int l_onoff; /* option on/off */ + int l_linger; /* linger time */ +}; + +/* + * Level number for (get/set)sockopt() to apply to socket itself. + */ +#define SOL_SOCKET 0xfff /* options for socket level */ + + +#define AF_UNSPEC 0 +#define AF_INET 2 +#define PF_INET AF_INET +#define PF_UNSPEC AF_UNSPEC + +#define IPPROTO_IP 0 +#define IPPROTO_TCP 6 +#define IPPROTO_UDP 17 +#define IPPROTO_UDPLITE 136 + +/* Flags we can use with send and recv. */ +#define MSG_PEEK 0x01 /* Peeks at an incoming message */ +#define MSG_WAITALL 0x02 /* Unimplemented: Requests that the function block until the full amount of data requested can be returned */ +#define MSG_OOB 0x04 /* Unimplemented: Requests out-of-band data. The significance and semantics of out-of-band data are protocol-specific */ +#define MSG_DONTWAIT 0x08 /* Nonblocking i/o for this operation only */ +#define MSG_MORE 0x10 /* Sender will send more */ + + +/* + * Options for level IPPROTO_IP + */ +#define IP_TOS 1 +#define IP_TTL 2 + +#if LWIP_TCP +/* + * Options for level IPPROTO_TCP + */ +#define TCP_NODELAY 0x01 /* don't delay send to coalesce packets */ +#define TCP_KEEPALIVE 0x02 /* send KEEPALIVE probes when idle for pcb->keep_idle milliseconds */ +#define TCP_KEEPIDLE 0x03 /* set pcb->keep_idle - Same as TCP_KEEPALIVE, but use seconds for get/setsockopt */ +#define TCP_KEEPINTVL 0x04 /* set pcb->keep_intvl - Use seconds for get/setsockopt */ +#define TCP_KEEPCNT 0x05 /* set pcb->keep_cnt - Use number of probes sent for get/setsockopt */ +#endif /* LWIP_TCP */ + +#if LWIP_UDP && LWIP_UDPLITE +/* + * Options for level IPPROTO_UDPLITE + */ +#define UDPLITE_SEND_CSCOV 0x01 /* sender checksum coverage */ +#define UDPLITE_RECV_CSCOV 0x02 /* minimal receiver checksum coverage */ +#endif /* LWIP_UDP && LWIP_UDPLITE*/ + + +#if LWIP_IGMP +/* + * Options and types for UDP multicast traffic handling + */ +#define IP_ADD_MEMBERSHIP 3 +#define IP_DROP_MEMBERSHIP 4 +#define IP_MULTICAST_TTL 5 +#define IP_MULTICAST_IF 6 +#define IP_MULTICAST_LOOP 7 + +typedef struct ip_mreq { + struct in_addr imr_multiaddr; /* IP multicast address of group */ + struct in_addr imr_interface; /* local IP address of interface */ +} ip_mreq; +#endif /* LWIP_IGMP */ + +/* + * The Type of Service provides an indication of the abstract + * parameters of the quality of service desired. These parameters are + * to be used to guide the selection of the actual service parameters + * when transmitting a datagram through a particular network. Several + * networks offer service precedence, which somehow treats high + * precedence traffic as more important than other traffic (generally + * by accepting only traffic above a certain precedence at time of high + * load). The major choice is a three way tradeoff between low-delay, + * high-reliability, and high-throughput. + * The use of the Delay, Throughput, and Reliability indications may + * increase the cost (in some sense) of the service. In many networks + * better performance for one of these parameters is coupled with worse + * performance on another. Except for very unusual cases at most two + * of these three indications should be set. + */ +#define IPTOS_TOS_MASK 0x1E +#define IPTOS_TOS(tos) ((tos) & IPTOS_TOS_MASK) +#define IPTOS_LOWDELAY 0x10 +#define IPTOS_THROUGHPUT 0x08 +#define IPTOS_RELIABILITY 0x04 +#define IPTOS_LOWCOST 0x02 +#define IPTOS_MINCOST IPTOS_LOWCOST + +/* + * The Network Control precedence designation is intended to be used + * within a network only. The actual use and control of that + * designation is up to each network. The Internetwork Control + * designation is intended for use by gateway control originators only. + * If the actual use of these precedence designations is of concern to + * a particular network, it is the responsibility of that network to + * control the access to, and use of, those precedence designations. + */ +#define IPTOS_PREC_MASK 0xe0 +#define IPTOS_PREC(tos) ((tos) & IPTOS_PREC_MASK) +#define IPTOS_PREC_NETCONTROL 0xe0 +#define IPTOS_PREC_INTERNETCONTROL 0xc0 +#define IPTOS_PREC_CRITIC_ECP 0xa0 +#define IPTOS_PREC_FLASHOVERRIDE 0x80 +#define IPTOS_PREC_FLASH 0x60 +#define IPTOS_PREC_IMMEDIATE 0x40 +#define IPTOS_PREC_PRIORITY 0x20 +#define IPTOS_PREC_ROUTINE 0x00 + + +/* + * Commands for ioctlsocket(), taken from the BSD file fcntl.h. + * lwip_ioctl only supports FIONREAD and FIONBIO, for now + * + * Ioctl's have the command encoded in the lower word, + * and the size of any in or out parameters in the upper + * word. The high 2 bits of the upper word are used + * to encode the in/out status of the parameter; for now + * we restrict parameters to at most 128 bytes. + */ +#if !defined(FIONREAD) || !defined(FIONBIO) +#define IOCPARM_MASK 0x7fU /* parameters must be < 128 bytes */ +#define IOC_VOID 0x20000000UL /* no parameters */ +#define IOC_OUT 0x40000000UL /* copy out parameters */ +#define IOC_IN 0x80000000UL /* copy in parameters */ +#define IOC_INOUT (IOC_IN|IOC_OUT) + /* 0x20000000 distinguishes new & + old ioctl's */ +#define _IO(x,y) (IOC_VOID|((x)<<8)|(y)) + +#define _IOR(x,y,t) (IOC_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) + +#define _IOW(x,y,t) (IOC_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) +#endif /* !defined(FIONREAD) || !defined(FIONBIO) */ + +#ifndef FIONREAD +#define FIONREAD _IOR('f', 127, unsigned long) /* get # bytes to read */ +#endif +#ifndef FIONBIO +#define FIONBIO _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */ +#endif + +/* Socket I/O Controls: unimplemented */ +#ifndef SIOCSHIWAT +#define SIOCSHIWAT _IOW('s', 0, unsigned long) /* set high watermark */ +#define SIOCGHIWAT _IOR('s', 1, unsigned long) /* get high watermark */ +#define SIOCSLOWAT _IOW('s', 2, unsigned long) /* set low watermark */ +#define SIOCGLOWAT _IOR('s', 3, unsigned long) /* get low watermark */ +#define SIOCATMARK _IOR('s', 7, unsigned long) /* at oob mark? */ +#endif + +/* Socket flags: */ +#ifndef O_NONBLOCK +#define O_NONBLOCK 04000U +#endif + +/* FD_SET used for lwip_select */ +#ifndef FD_SET + #undef FD_SETSIZE + /* Make FD_SETSIZE match NUM_SOCKETS in socket.c */ + #define FD_SETSIZE MEMP_NUM_NETCONN + #define FD_SET(n, p) ((p)->fd_bits[(n)/8] |= (1 << ((n) & 7))) + #define FD_CLR(n, p) ((p)->fd_bits[(n)/8] &= ~(1 << ((n) & 7))) + #define FD_ISSET(n,p) ((p)->fd_bits[(n)/8] & (1 << ((n) & 7))) + #define FD_ZERO(p) memset((void*)(p),0,sizeof(*(p))) + + typedef struct fd_set { + unsigned char fd_bits [(FD_SETSIZE+7)/8]; + } fd_set; + +#endif /* FD_SET */ + +/** LWIP_TIMEVAL_PRIVATE: if you want to use the struct timeval provided + * by your system, set this to 0 and include <sys/time.h> in cc.h */ +#ifndef LWIP_TIMEVAL_PRIVATE +#define LWIP_TIMEVAL_PRIVATE 1 +#endif + +#if LWIP_TIMEVAL_PRIVATE +struct timeval { + long tv_sec; /* seconds */ + long tv_usec; /* and microseconds */ +}; +#endif /* LWIP_TIMEVAL_PRIVATE */ + +void lwip_socket_init(void); + +int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen); +int lwip_bind(int s, const struct sockaddr *name, socklen_t namelen); +int lwip_shutdown(int s, int how); +int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen); +int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen); +int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen); +int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen); +int lwip_close(int s); +int lwip_connect(int s, const struct sockaddr *name, socklen_t namelen); +int lwip_listen(int s, int backlog); +int lwip_recv(int s, void *mem, size_t len, int flags); +int lwip_read(int s, void *mem, size_t len); +int lwip_recvfrom(int s, void *mem, size_t len, int flags, + struct sockaddr *from, socklen_t *fromlen); +int lwip_send(int s, const void *dataptr, size_t size, int flags); +int lwip_sendto(int s, const void *dataptr, size_t size, int flags, + const struct sockaddr *to, socklen_t tolen); +int lwip_socket(int domain, int type, int protocol); +int lwip_write(int s, const void *dataptr, size_t size); +int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset, + struct timeval *timeout); +int lwip_ioctl(int s, long cmd, void *argp); + +#if LWIP_COMPAT_SOCKETS +#define accept(a,b,c) lwip_accept(a,b,c) +#define bind(a,b,c) lwip_bind(a,b,c) +#define shutdown(a,b) lwip_shutdown(a,b) +#define closesocket(s) lwip_close(s) +#define connect(a,b,c) lwip_connect(a,b,c) +#define getsockname(a,b,c) lwip_getsockname(a,b,c) +#define getpeername(a,b,c) lwip_getpeername(a,b,c) +#define setsockopt(a,b,c,d,e) lwip_setsockopt(a,b,c,d,e) +#define getsockopt(a,b,c,d,e) lwip_getsockopt(a,b,c,d,e) +#define listen(a,b) lwip_listen(a,b) +#define recv(a,b,c,d) lwip_recv(a,b,c,d) +#define recvfrom(a,b,c,d,e,f) lwip_recvfrom(a,b,c,d,e,f) +#define send(a,b,c,d) lwip_send(a,b,c,d) +#define sendto(a,b,c,d,e,f) lwip_sendto(a,b,c,d,e,f) +#define socket(a,b,c) lwip_socket(a,b,c) +#define select(a,b,c,d,e) lwip_select(a,b,c,d,e) +#define ioctlsocket(a,b,c) lwip_ioctl(a,b,c) + +#if LWIP_POSIX_SOCKETS_IO_NAMES +#define read(a,b,c) lwip_read(a,b,c) +#define write(a,b,c) lwip_write(a,b,c) +#define close(s) lwip_close(s) +#endif /* LWIP_POSIX_SOCKETS_IO_NAMES */ + +#endif /* LWIP_COMPAT_SOCKETS */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_SOCKET */ + +#endif /* __LWIP_SOCKETS_H__ */ diff --git a/firmware/octoclock/include/lwip/stats.h b/firmware/octoclock/include/lwip/stats.h new file mode 100644 index 000000000..aa179f5c0 --- /dev/null +++ b/firmware/octoclock/include/lwip/stats.h @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __LWIP_STATS_H__ +#define __LWIP_STATS_H__ + +#include "lwip/opt.h" + +#include "lwip/mem.h" +#include "lwip/memp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if LWIP_STATS + +#ifndef LWIP_STATS_LARGE +#define LWIP_STATS_LARGE 0 +#endif + +#if LWIP_STATS_LARGE +#define STAT_COUNTER u32_t +#define STAT_COUNTER_F U32_F +#else +#define STAT_COUNTER u16_t +#define STAT_COUNTER_F U16_F +#endif + +struct stats_proto { + STAT_COUNTER xmit; /* Transmitted packets. */ + STAT_COUNTER recv; /* Received packets. */ + STAT_COUNTER fw; /* Forwarded packets. */ + STAT_COUNTER drop; /* Dropped packets. */ + STAT_COUNTER chkerr; /* Checksum error. */ + STAT_COUNTER lenerr; /* Invalid length error. */ + STAT_COUNTER memerr; /* Out of memory error. */ + STAT_COUNTER rterr; /* Routing error. */ + STAT_COUNTER proterr; /* Protocol error. */ + STAT_COUNTER opterr; /* Error in options. */ + STAT_COUNTER err; /* Misc error. */ + STAT_COUNTER cachehit; +}; + +struct stats_igmp { + STAT_COUNTER lenerr; /* Invalid length error. */ + STAT_COUNTER chkerr; /* Checksum error. */ + STAT_COUNTER v1_rxed; /* */ + STAT_COUNTER join_sent; /* */ + STAT_COUNTER leave_sent; /* */ + STAT_COUNTER unicast_query; /* */ + STAT_COUNTER report_sent; /* */ + STAT_COUNTER report_rxed; /* */ + STAT_COUNTER group_query_rxed; /* */ +}; + +struct stats_mem { + mem_size_t avail; + mem_size_t used; + mem_size_t max; + STAT_COUNTER err; + STAT_COUNTER illegal; +}; + +struct stats_syselem { + STAT_COUNTER used; + STAT_COUNTER max; + STAT_COUNTER err; +}; + +struct stats_sys { + struct stats_syselem sem; + struct stats_syselem mbox; +}; + +struct stats_ { +#if LINK_STATS + struct stats_proto link; +#endif +#if ETHARP_STATS + struct stats_proto etharp; +#endif +#if IPFRAG_STATS + struct stats_proto ip_frag; +#endif +#if IP_STATS + struct stats_proto ip; +#endif +#if ICMP_STATS + struct stats_proto icmp; +#endif +#if IGMP_STATS + struct stats_igmp igmp; +#endif +#if UDP_STATS + struct stats_proto udp; +#endif +#if TCP_STATS + struct stats_proto tcp; +#endif +#if MEM_STATS + struct stats_mem mem; +#endif +#if MEMP_STATS + struct stats_mem memp[MEMP_MAX]; +#endif +#if SYS_STATS + struct stats_sys sys; +#endif +}; + +extern struct stats_ lwip_stats; + +#define stats_init() /* Compatibility define, not init needed. */ + +#define STATS_INC(x) ++lwip_stats.x +#define STATS_DEC(x) --lwip_stats.x +#else +#define stats_init() +#define STATS_INC(x) +#define STATS_DEC(x) +#endif /* LWIP_STATS */ + +#if TCP_STATS +#define TCP_STATS_INC(x) STATS_INC(x) +#define TCP_STATS_DISPLAY() stats_display_proto(&lwip_stats.tcp, "TCP") +#else +#define TCP_STATS_INC(x) +#define TCP_STATS_DISPLAY() +#endif + +#if UDP_STATS +#define UDP_STATS_INC(x) STATS_INC(x) +#define UDP_STATS_DISPLAY() stats_display_proto(&lwip_stats.udp, "UDP") +#else +#define UDP_STATS_INC(x) +#define UDP_STATS_DISPLAY() +#endif + +#if ICMP_STATS +#define ICMP_STATS_INC(x) STATS_INC(x) +#define ICMP_STATS_DISPLAY() stats_display_proto(&lwip_stats.icmp, "ICMP") +#else +#define ICMP_STATS_INC(x) +#define ICMP_STATS_DISPLAY() +#endif + +#if IGMP_STATS +#define IGMP_STATS_INC(x) STATS_INC(x) +#define IGMP_STATS_DISPLAY() stats_display_igmp(&lwip_stats.igmp) +#else +#define IGMP_STATS_INC(x) +#define IGMP_STATS_DISPLAY() +#endif + +#if IP_STATS +#define IP_STATS_INC(x) STATS_INC(x) +#define IP_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip, "IP") +#else +#define IP_STATS_INC(x) +#define IP_STATS_DISPLAY() +#endif + +#if IPFRAG_STATS +#define IPFRAG_STATS_INC(x) STATS_INC(x) +#define IPFRAG_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG") +#else +#define IPFRAG_STATS_INC(x) +#define IPFRAG_STATS_DISPLAY() +#endif + +#if ETHARP_STATS +#define ETHARP_STATS_INC(x) STATS_INC(x) +#define ETHARP_STATS_DISPLAY() stats_display_proto(&lwip_stats.etharp, "ETHARP") +#else +#define ETHARP_STATS_INC(x) +#define ETHARP_STATS_DISPLAY() +#endif + +#if LINK_STATS +#define LINK_STATS_INC(x) STATS_INC(x) +#define LINK_STATS_DISPLAY() stats_display_proto(&lwip_stats.link, "LINK") +#else +#define LINK_STATS_INC(x) +#define LINK_STATS_DISPLAY() +#endif + +#if MEM_STATS +#define MEM_STATS_AVAIL(x, y) lwip_stats.mem.x = y +#define MEM_STATS_INC(x) STATS_INC(mem.x) +#define MEM_STATS_INC_USED(x, y) do { lwip_stats.mem.used += y; \ + if (lwip_stats.mem.max < lwip_stats.mem.used) { \ + lwip_stats.mem.max = lwip_stats.mem.used; \ + } \ + } while(0) +#define MEM_STATS_DEC_USED(x, y) lwip_stats.mem.x -= y +#define MEM_STATS_DISPLAY() stats_display_mem(&lwip_stats.mem, "HEAP") +#else +#define MEM_STATS_AVAIL(x, y) +#define MEM_STATS_INC(x) +#define MEM_STATS_INC_USED(x, y) +#define MEM_STATS_DEC_USED(x, y) +#define MEM_STATS_DISPLAY() +#endif + +#if MEMP_STATS +#define MEMP_STATS_AVAIL(x, i, y) lwip_stats.memp[i].x = y +#define MEMP_STATS_INC(x, i) STATS_INC(memp[i].x) +#define MEMP_STATS_DEC(x, i) STATS_DEC(memp[i].x) +#define MEMP_STATS_INC_USED(x, i) do { ++lwip_stats.memp[i].used; \ + if (lwip_stats.memp[i].max < lwip_stats.memp[i].used) { \ + lwip_stats.memp[i].max = lwip_stats.memp[i].used; \ + } \ + } while(0) +#define MEMP_STATS_DISPLAY(i) stats_display_memp(&lwip_stats.memp[i], i) +#else +#define MEMP_STATS_AVAIL(x, i, y) +#define MEMP_STATS_INC(x, i) +#define MEMP_STATS_DEC(x, i) +#define MEMP_STATS_INC_USED(x, i) +#define MEMP_STATS_DISPLAY(i) +#endif + +#if SYS_STATS +#define SYS_STATS_INC(x) STATS_INC(sys.x) +#define SYS_STATS_DEC(x) STATS_DEC(sys.x) +#define SYS_STATS_DISPLAY() stats_display_sys(&lwip_stats.sys) +#else +#define SYS_STATS_INC(x) +#define SYS_STATS_DEC(x) +#define SYS_STATS_DISPLAY() +#endif + +/* Display of statistics */ +#if LWIP_STATS_DISPLAY +void stats_display(void); +void stats_display_proto(struct stats_proto *proto, char *name); +void stats_display_igmp(struct stats_igmp *igmp); +void stats_display_mem(struct stats_mem *mem, char *name); +void stats_display_memp(struct stats_mem *mem, int index); +void stats_display_sys(struct stats_sys *sys); +#else +#define stats_display() +#define stats_display_proto(proto, name) +#define stats_display_igmp(igmp) +#define stats_display_mem(mem, name) +#define stats_display_memp(mem, index) +#define stats_display_sys(sys) +#endif /* LWIP_STATS_DISPLAY */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_STATS_H__ */ diff --git a/firmware/octoclock/include/lwip/sys.h b/firmware/octoclock/include/lwip/sys.h new file mode 100644 index 000000000..0cc84ddf1 --- /dev/null +++ b/firmware/octoclock/include/lwip/sys.h @@ -0,0 +1,243 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __LWIP_SYS_H__ +#define __LWIP_SYS_H__ + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if NO_SYS + +/* For a totally minimal and standalone system, we provide null + definitions of the sys_ functions. */ +typedef u8_t sys_sem_t; +typedef u8_t sys_mbox_t; +struct sys_timeo {u8_t dummy;}; + +#define sys_init() +#define sys_timeout(m,h,a) +#define sys_untimeout(m,a) +#define sys_sem_new(c) c +#define sys_sem_signal(s) +#define sys_sem_wait(s) +#define sys_sem_wait_timeout(s,t) +#define sys_arch_sem_wait(s,t) +#define sys_sem_free(s) +#define sys_mbox_new(s) 0 +#define sys_mbox_fetch(m,d) +#define sys_mbox_tryfetch(m,d) +#define sys_mbox_post(m,d) +#define sys_mbox_trypost(m,d) +#define sys_mbox_free(m) + +#define sys_thread_new(n,t,a,s,p) + +#else /* NO_SYS */ + +/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */ +#define SYS_ARCH_TIMEOUT 0xffffffffUL + +/* sys_mbox_tryfetch returns SYS_MBOX_EMPTY if appropriate. + * For now we use the same magic value, but we allow this to change in future. + */ +#define SYS_MBOX_EMPTY SYS_ARCH_TIMEOUT + +#include "lwip/err.h" +#include "arch/sys_arch.h" + +typedef void (* sys_timeout_handler)(void *arg); + +struct sys_timeo { + struct sys_timeo *next; + u32_t time; + sys_timeout_handler h; + void *arg; +}; + +struct sys_timeouts { + struct sys_timeo *next; +}; + +/* sys_init() must be called before anthing else. */ +void sys_init(void); + +/* + * sys_timeout(): + * + * Schedule a timeout a specified amount of milliseconds in the + * future. When the timeout occurs, the specified timeout handler will + * be called. The handler will be passed the "arg" argument when + * called. + * + */ +void sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg); +void sys_untimeout(sys_timeout_handler h, void *arg); +struct sys_timeouts *sys_arch_timeouts(void); + +/* Semaphore functions. */ +sys_sem_t sys_sem_new(u8_t count); +void sys_sem_signal(sys_sem_t sem); +u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout); +void sys_sem_free(sys_sem_t sem); +void sys_sem_wait(sys_sem_t sem); +int sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout); + +/* Time functions. */ +#ifndef sys_msleep +void sys_msleep(u32_t ms); /* only has a (close to) 1 jiffy resolution. */ +#endif +#ifndef sys_jiffies +u32_t sys_jiffies(void); /* since power up. */ +#endif + +/* Mailbox functions. */ +sys_mbox_t sys_mbox_new(int size); +void sys_mbox_post(sys_mbox_t mbox, void *msg); +err_t sys_mbox_trypost(sys_mbox_t mbox, void *msg); +u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout); +#ifndef sys_arch_mbox_tryfetch /* Allow port to override with a macro */ +u32_t sys_arch_mbox_tryfetch(sys_mbox_t mbox, void **msg); +#endif +/* For now, we map straight to sys_arch implementation. */ +#define sys_mbox_tryfetch(mbox, msg) sys_arch_mbox_tryfetch(mbox, msg) +void sys_mbox_free(sys_mbox_t mbox); +void sys_mbox_fetch(sys_mbox_t mbox, void **msg); + +/* Thread functions. */ +sys_thread_t sys_thread_new(char *name, void (* thread)(void *arg), void *arg, int stacksize, int prio); + +#endif /* NO_SYS */ + +/** Returns the current time in milliseconds. */ +u32_t sys_now(void); + +/* Critical Region Protection */ +/* These functions must be implemented in the sys_arch.c file. + In some implementations they can provide a more light-weight protection + mechanism than using semaphores. Otherwise semaphores can be used for + implementation */ +#ifndef SYS_ARCH_PROTECT +/** SYS_LIGHTWEIGHT_PROT + * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection + * for certain critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#if SYS_LIGHTWEIGHT_PROT + +/** SYS_ARCH_DECL_PROTECT + * declare a protection variable. This macro will default to defining a variable of + * type sys_prot_t. If a particular port needs a different implementation, then + * this macro may be defined in sys_arch.h. + */ +#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev +/** SYS_ARCH_PROTECT + * Perform a "fast" protect. This could be implemented by + * disabling interrupts for an embedded system or by using a semaphore or + * mutex. The implementation should allow calling SYS_ARCH_PROTECT when + * already protected. The old protection level is returned in the variable + * "lev". This macro will default to calling the sys_arch_protect() function + * which should be implemented in sys_arch.c. If a particular port needs a + * different implementation, then this macro may be defined in sys_arch.h + */ +#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect() +/** SYS_ARCH_UNPROTECT + * Perform a "fast" set of the protection level to "lev". This could be + * implemented by setting the interrupt level to "lev" within the MACRO or by + * using a semaphore or mutex. This macro will default to calling the + * sys_arch_unprotect() function which should be implemented in + * sys_arch.c. If a particular port needs a different implementation, then + * this macro may be defined in sys_arch.h + */ +#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev) +sys_prot_t sys_arch_protect(void); +void sys_arch_unprotect(sys_prot_t pval); + +#else + +#define SYS_ARCH_DECL_PROTECT(lev) +#define SYS_ARCH_PROTECT(lev) +#define SYS_ARCH_UNPROTECT(lev) + +#endif /* SYS_LIGHTWEIGHT_PROT */ + +#endif /* SYS_ARCH_PROTECT */ + +/* + * Macros to set/get and increase/decrease variables in a thread-safe way. + * Use these for accessing variable that are used from more than one thread. + */ + +#ifndef SYS_ARCH_INC +#define SYS_ARCH_INC(var, val) do { \ + SYS_ARCH_DECL_PROTECT(old_level); \ + SYS_ARCH_PROTECT(old_level); \ + var += val; \ + SYS_ARCH_UNPROTECT(old_level); \ + } while(0) +#endif /* SYS_ARCH_INC */ + +#ifndef SYS_ARCH_DEC +#define SYS_ARCH_DEC(var, val) do { \ + SYS_ARCH_DECL_PROTECT(old_level); \ + SYS_ARCH_PROTECT(old_level); \ + var -= val; \ + SYS_ARCH_UNPROTECT(old_level); \ + } while(0) +#endif /* SYS_ARCH_DEC */ + +#ifndef SYS_ARCH_GET +#define SYS_ARCH_GET(var, ret) do { \ + SYS_ARCH_DECL_PROTECT(old_level); \ + SYS_ARCH_PROTECT(old_level); \ + ret = var; \ + SYS_ARCH_UNPROTECT(old_level); \ + } while(0) +#endif /* SYS_ARCH_GET */ + +#ifndef SYS_ARCH_SET +#define SYS_ARCH_SET(var, val) do { \ + SYS_ARCH_DECL_PROTECT(old_level); \ + SYS_ARCH_PROTECT(old_level); \ + var = val; \ + SYS_ARCH_UNPROTECT(old_level); \ + } while(0) +#endif /* SYS_ARCH_SET */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __LWIP_SYS_H__ */ diff --git a/firmware/octoclock/include/lwip/tcp.h b/firmware/octoclock/include/lwip/tcp.h new file mode 100644 index 000000000..8f6b9d3c1 --- /dev/null +++ b/firmware/octoclock/include/lwip/tcp.h @@ -0,0 +1,699 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __LWIP_TCP_H__ +#define __LWIP_TCP_H__ + +#include "lwip/opt.h" + +#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/sys.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/ip.h" +#include "lwip/icmp.h" +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct tcp_pcb; + +/* Functions for interfacing with TCP: */ + +/* Lower layer interface to TCP: */ +#define tcp_init() /* Compatibility define, not init needed. */ +void tcp_tmr (void); /* Must be called every + TCP_TMR_INTERVAL + ms. (Typically 250 ms). */ +/* Application program's interface: */ +struct tcp_pcb * tcp_new (void); +struct tcp_pcb * tcp_alloc (u8_t prio); + +void tcp_arg (struct tcp_pcb *pcb, void *arg); +void tcp_accept (struct tcp_pcb *pcb, + err_t (* accept)(void *arg, struct tcp_pcb *newpcb, + err_t err)); +void tcp_recv (struct tcp_pcb *pcb, + err_t (* recv)(void *arg, struct tcp_pcb *tpcb, + struct pbuf *p, err_t err)); +void tcp_sent (struct tcp_pcb *pcb, + err_t (* sent)(void *arg, struct tcp_pcb *tpcb, + u16_t len)); +void tcp_poll (struct tcp_pcb *pcb, + err_t (* poll)(void *arg, struct tcp_pcb *tpcb), + u8_t interval); +void tcp_err (struct tcp_pcb *pcb, + void (* err)(void *arg, err_t err)); + +#define tcp_mss(pcb) ((pcb)->mss) +#define tcp_sndbuf(pcb) ((pcb)->snd_buf) + +#if TCP_LISTEN_BACKLOG +#define tcp_accepted(pcb) (((struct tcp_pcb_listen *)(pcb))->accepts_pending--) +#else /* TCP_LISTEN_BACKLOG */ +#define tcp_accepted(pcb) +#endif /* TCP_LISTEN_BACKLOG */ + +void tcp_recved (struct tcp_pcb *pcb, u16_t len); +err_t tcp_bind (struct tcp_pcb *pcb, struct ip_addr *ipaddr, + u16_t port); +err_t tcp_connect (struct tcp_pcb *pcb, struct ip_addr *ipaddr, + u16_t port, err_t (* connected)(void *arg, + struct tcp_pcb *tpcb, + err_t err)); + +struct tcp_pcb * tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog); +#define tcp_listen(pcb) tcp_listen_with_backlog(pcb, TCP_DEFAULT_LISTEN_BACKLOG) + +void tcp_abandon (struct tcp_pcb *pcb, int reset); +#define tcp_abort(pcb) tcp_abandon((pcb), 1) +err_t tcp_close (struct tcp_pcb *pcb); + +/* Flags for "apiflags" parameter in tcp_write and tcp_enqueue */ +#define TCP_WRITE_FLAG_COPY 0x01 +#define TCP_WRITE_FLAG_MORE 0x02 + +err_t tcp_write (struct tcp_pcb *pcb, const void *dataptr, u16_t len, + u8_t apiflags); + +void tcp_setprio (struct tcp_pcb *pcb, u8_t prio); + +#define TCP_PRIO_MIN 1 +#define TCP_PRIO_NORMAL 64 +#define TCP_PRIO_MAX 127 + +/* It is also possible to call these two functions at the right + intervals (instead of calling tcp_tmr()). */ +void tcp_slowtmr (void); +void tcp_fasttmr (void); + + +/* Only used by IP to pass a TCP segment to TCP: */ +void tcp_input (struct pbuf *p, struct netif *inp); +/* Used within the TCP code only: */ +err_t tcp_output (struct tcp_pcb *pcb); +void tcp_rexmit (struct tcp_pcb *pcb); +void tcp_rexmit_rto (struct tcp_pcb *pcb); +u32_t tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb); + +/** + * This is the Nagle algorithm: try to combine user data to send as few TCP + * segments as possible. Only send if + * - no previously transmitted data on the connection remains unacknowledged or + * - the TF_NODELAY flag is set (nagle algorithm turned off for this pcb) or + * - the only unsent segment is at least pcb->mss bytes long (or there is more + * than one unsent segment - with lwIP, this can happen although unsent->len < mss) + */ +#define tcp_do_output_nagle(tpcb) ((((tpcb)->unacked == NULL) || \ + ((tpcb)->flags & TF_NODELAY) || \ + (((tpcb)->unsent != NULL) && (((tpcb)->unsent->next != NULL) || \ + ((tpcb)->unsent->len >= (tpcb)->mss))) \ + ) ? 1 : 0) +#define tcp_output_nagle(tpcb) (tcp_do_output_nagle(tpcb) ? tcp_output(tpcb) : ERR_OK) + + +#define TCP_SEQ_LT(a,b) ((s32_t)((a)-(b)) < 0) +#define TCP_SEQ_LEQ(a,b) ((s32_t)((a)-(b)) <= 0) +#define TCP_SEQ_GT(a,b) ((s32_t)((a)-(b)) > 0) +#define TCP_SEQ_GEQ(a,b) ((s32_t)((a)-(b)) >= 0) +/* is b<=a<=c? */ +#if 0 /* see bug #10548 */ +#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b)) +#endif +#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c)) +#define TCP_FIN 0x01U +#define TCP_SYN 0x02U +#define TCP_RST 0x04U +#define TCP_PSH 0x08U +#define TCP_ACK 0x10U +#define TCP_URG 0x20U +#define TCP_ECE 0x40U +#define TCP_CWR 0x80U + +#define TCP_FLAGS 0x3fU + +/* Length of the TCP header, excluding options. */ +#define TCP_HLEN 20 + +#ifndef TCP_TMR_INTERVAL +#define TCP_TMR_INTERVAL 250 /* The TCP timer interval in milliseconds. */ +#endif /* TCP_TMR_INTERVAL */ + +#ifndef TCP_FAST_INTERVAL +#define TCP_FAST_INTERVAL TCP_TMR_INTERVAL /* the fine grained timeout in milliseconds */ +#endif /* TCP_FAST_INTERVAL */ + +#ifndef TCP_SLOW_INTERVAL +#define TCP_SLOW_INTERVAL (2*TCP_TMR_INTERVAL) /* the coarse grained timeout in milliseconds */ +#endif /* TCP_SLOW_INTERVAL */ + +#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */ +#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */ + +#define TCP_OOSEQ_TIMEOUT 6U /* x RTO */ + +#ifndef TCP_MSL +#define TCP_MSL 60000UL /* The maximum segment lifetime in milliseconds */ +#endif + +/* Keepalive values, compliant with RFC 1122. Don't change this unless you know what you're doing */ +#ifndef TCP_KEEPIDLE_DEFAULT +#define TCP_KEEPIDLE_DEFAULT 7200000UL /* Default KEEPALIVE timer in milliseconds */ +#endif + +#ifndef TCP_KEEPINTVL_DEFAULT +#define TCP_KEEPINTVL_DEFAULT 75000UL /* Default Time between KEEPALIVE probes in milliseconds */ +#endif + +#ifndef TCP_KEEPCNT_DEFAULT +#define TCP_KEEPCNT_DEFAULT 9U /* Default Counter for KEEPALIVE probes */ +#endif + +#define TCP_MAXIDLE TCP_KEEPCNT_DEFAULT * TCP_KEEPINTVL_DEFAULT /* Maximum KEEPALIVE probe time */ + +/* Fields are (of course) in network byte order. + * Some fields are converted to host byte order in tcp_input(). + */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct tcp_hdr { + PACK_STRUCT_FIELD(u16_t src); + PACK_STRUCT_FIELD(u16_t dest); + PACK_STRUCT_FIELD(u32_t seqno); + PACK_STRUCT_FIELD(u32_t ackno); + PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags); + PACK_STRUCT_FIELD(u16_t wnd); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u16_t urgp); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define TCPH_OFFSET(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 8) +#define TCPH_HDRLEN(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 12) +#define TCPH_FLAGS(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS) + +#define TCPH_OFFSET_SET(phdr, offset) (phdr)->_hdrlen_rsvd_flags = htons(((offset) << 8) | TCPH_FLAGS(phdr)) +#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | TCPH_FLAGS(phdr)) +#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons((ntohs((phdr)->_hdrlen_rsvd_flags) & ~TCP_FLAGS) | (flags)) +#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (flags)) +#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (TCPH_FLAGS(phdr) & ~(flags)) ) + +#define TCP_TCPLEN(seg) ((seg)->len + ((TCPH_FLAGS((seg)->tcphdr) & TCP_FIN || \ + TCPH_FLAGS((seg)->tcphdr) & TCP_SYN)? 1: 0)) + +enum tcp_state { + CLOSED = 0, + LISTEN = 1, + SYN_SENT = 2, + SYN_RCVD = 3, + ESTABLISHED = 4, + FIN_WAIT_1 = 5, + FIN_WAIT_2 = 6, + CLOSE_WAIT = 7, + CLOSING = 8, + LAST_ACK = 9, + TIME_WAIT = 10 +}; + +/** Flags used on input processing, not on pcb->flags +*/ +#define TF_RESET (u8_t)0x08U /* Connection was reset. */ +#define TF_CLOSED (u8_t)0x10U /* Connection was sucessfully closed. */ +#define TF_GOT_FIN (u8_t)0x20U /* Connection was closed by the remote end. */ + + +#if LWIP_CALLBACK_API + /* Function to call when a listener has been connected. + * @param arg user-supplied argument (tcp_pcb.callback_arg) + * @param pcb a new tcp_pcb that now is connected + * @param err an error argument (TODO: that is current always ERR_OK?) + * @return ERR_OK: accept the new connection, + * any other err_t abortsthe new connection + */ +#define DEF_ACCEPT_CALLBACK err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err) +#else /* LWIP_CALLBACK_API */ +#define DEF_ACCEPT_CALLBACK +#endif /* LWIP_CALLBACK_API */ + +/** + * members common to struct tcp_pcb and struct tcp_listen_pcb + */ +#define TCP_PCB_COMMON(type) \ + type *next; /* for the linked list */ \ + enum tcp_state state; /* TCP state */ \ + u8_t prio; \ + void *callback_arg; \ + /* ports are in host byte order */ \ + u16_t local_port; \ + /* the accept callback for listen- and normal pcbs, if LWIP_CALLBACK_API */ \ + DEF_ACCEPT_CALLBACK + + +/* the TCP protocol control block */ +struct tcp_pcb { +/** common PCB members */ + IP_PCB; +/** protocol specific PCB members */ + TCP_PCB_COMMON(struct tcp_pcb); + + /* ports are in host byte order */ + u16_t remote_port; + + u8_t flags; +#define TF_ACK_DELAY ((u8_t)0x01U) /* Delayed ACK. */ +#define TF_ACK_NOW ((u8_t)0x02U) /* Immediate ACK. */ +#define TF_INFR ((u8_t)0x04U) /* In fast recovery. */ +#define TF_TIMESTAMP ((u8_t)0x08U) /* Timestamp option enabled */ +#define TF_FIN ((u8_t)0x20U) /* Connection was closed locally (FIN segment enqueued). */ +#define TF_NODELAY ((u8_t)0x40U) /* Disable Nagle algorithm */ +#define TF_NAGLEMEMERR ((u8_t)0x80U) /* nagle enabled, memerr, try to output to prevent delayed ACK to happen */ + + /* the rest of the fields are in host byte order + as we have to do some math with them */ + /* receiver variables */ + u32_t rcv_nxt; /* next seqno expected */ + u16_t rcv_wnd; /* receiver window available */ + u16_t rcv_ann_wnd; /* receiver window to announce */ + u32_t rcv_ann_right_edge; /* announced right edge of window */ + + /* Timers */ + u32_t tmr; + u8_t polltmr, pollinterval; + + /* Retransmission timer. */ + s16_t rtime; + + u16_t mss; /* maximum segment size */ + + /* RTT (round trip time) estimation variables */ + u32_t rttest; /* RTT estimate in 500ms ticks */ + u32_t rtseq; /* sequence number being timed */ + s16_t sa, sv; /* @todo document this */ + + s16_t rto; /* retransmission time-out */ + u8_t nrtx; /* number of retransmissions */ + + /* fast retransmit/recovery */ + u32_t lastack; /* Highest acknowledged seqno. */ + u8_t dupacks; + + /* congestion avoidance/control variables */ + u16_t cwnd; + u16_t ssthresh; + + /* sender variables */ + u32_t snd_nxt; /* next new seqno to be sent */ + u16_t snd_wnd; /* sender window */ + u32_t snd_wl1, snd_wl2; /* Sequence and acknowledgement numbers of last + window update. */ + u32_t snd_lbb; /* Sequence number of next byte to be buffered. */ + + u16_t acked; + + u16_t snd_buf; /* Available buffer space for sending (in bytes). */ +#define TCP_SNDQUEUELEN_OVERFLOW (0xffff-3) + u16_t snd_queuelen; /* Available buffer space for sending (in tcp_segs). */ + + + /* These are ordered by sequence number: */ + struct tcp_seg *unsent; /* Unsent (queued) segments. */ + struct tcp_seg *unacked; /* Sent but unacknowledged segments. */ +#if TCP_QUEUE_OOSEQ + struct tcp_seg *ooseq; /* Received out of sequence segments. */ +#endif /* TCP_QUEUE_OOSEQ */ + + struct pbuf *refused_data; /* Data previously received but not yet taken by upper layer */ + +#if LWIP_CALLBACK_API + /* Function to be called when more send buffer space is available. + * @param arg user-supplied argument (tcp_pcb.callback_arg) + * @param pcb the tcp_pcb which has send buffer space available + * @param space the amount of bytes available + * @return ERR_OK: try to send some data by calling tcp_output + */ + err_t (* sent)(void *arg, struct tcp_pcb *pcb, u16_t space); + + /* Function to be called when (in-sequence) data has arrived. + * @param arg user-supplied argument (tcp_pcb.callback_arg) + * @param pcb the tcp_pcb for which data has arrived + * @param p the packet buffer which arrived + * @param err an error argument (TODO: that is current always ERR_OK?) + * @return ERR_OK: try to send some data by calling tcp_output + */ + err_t (* recv)(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err); + + /* Function to be called when a connection has been set up. + * @param arg user-supplied argument (tcp_pcb.callback_arg) + * @param pcb the tcp_pcb that now is connected + * @param err an error argument (TODO: that is current always ERR_OK?) + * @return value is currently ignored + */ + err_t (* connected)(void *arg, struct tcp_pcb *pcb, err_t err); + + /* Function which is called periodically. + * The period can be adjusted in multiples of the TCP slow timer interval + * by changing tcp_pcb.polltmr. + * @param arg user-supplied argument (tcp_pcb.callback_arg) + * @param pcb the tcp_pcb to poll for + * @return ERR_OK: try to send some data by calling tcp_output + */ + err_t (* poll)(void *arg, struct tcp_pcb *pcb); + + /* Function to be called whenever a fatal error occurs. + * There is no pcb parameter since most of the times, the pcb is + * already deallocated (or there is no pcb) when this function is called. + * @param arg user-supplied argument (tcp_pcb.callback_arg) + * @param err an indication why the error callback is called: + * ERR_ABRT: aborted through tcp_abort or by a TCP timer + * ERR_RST: the connection was reset by the remote host + */ + void (* errf)(void *arg, err_t err); +#endif /* LWIP_CALLBACK_API */ + +#if LWIP_TCP_TIMESTAMPS + u32_t ts_lastacksent; + u32_t ts_recent; +#endif /* LWIP_TCP_TIMESTAMPS */ + + /* idle time before KEEPALIVE is sent */ + u32_t keep_idle; +#if LWIP_TCP_KEEPALIVE + u32_t keep_intvl; + u32_t keep_cnt; +#endif /* LWIP_TCP_KEEPALIVE */ + + /* Persist timer counter */ + u32_t persist_cnt; + /* Persist timer back-off */ + u8_t persist_backoff; + + /* KEEPALIVE counter */ + u8_t keep_cnt_sent; +}; + +struct tcp_pcb_listen { +/* Common members of all PCB types */ + IP_PCB; +/* Protocol specific PCB members */ + TCP_PCB_COMMON(struct tcp_pcb_listen); + +#if TCP_LISTEN_BACKLOG + u8_t backlog; + u8_t accepts_pending; +#endif /* TCP_LISTEN_BACKLOG */ +}; + +#if LWIP_EVENT_API + +enum lwip_event { + LWIP_EVENT_ACCEPT, + LWIP_EVENT_SENT, + LWIP_EVENT_RECV, + LWIP_EVENT_CONNECTED, + LWIP_EVENT_POLL, + LWIP_EVENT_ERR +}; + +err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb, + enum lwip_event, + struct pbuf *p, + u16_t size, + err_t err); + +#define TCP_EVENT_ACCEPT(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_ACCEPT, NULL, 0, err) +#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_SENT, NULL, space, ERR_OK) +#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_RECV, (p), 0, (err)) +#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_CONNECTED, NULL, 0, (err)) +#define TCP_EVENT_POLL(pcb,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_POLL, NULL, 0, ERR_OK) +#define TCP_EVENT_ERR(errf,arg,err) lwip_tcp_event((arg), NULL, \ + LWIP_EVENT_ERR, NULL, 0, (err)) +#else /* LWIP_EVENT_API */ + +#define TCP_EVENT_ACCEPT(pcb,err,ret) \ + do { \ + if((pcb)->accept != NULL) \ + (ret) = (pcb)->accept((pcb)->callback_arg,(pcb),(err)); \ + else (ret) = ERR_OK; \ + } while (0) + +#define TCP_EVENT_SENT(pcb,space,ret) \ + do { \ + if((pcb)->sent != NULL) \ + (ret) = (pcb)->sent((pcb)->callback_arg,(pcb),(space)); \ + else (ret) = ERR_OK; \ + } while (0) + +#define TCP_EVENT_RECV(pcb,p,err,ret) \ + do { \ + if((pcb)->recv != NULL) { \ + (ret) = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err)); \ + } else { \ + (ret) = ERR_OK; \ + if (p != NULL) \ + pbuf_free(p); \ + } \ + } while (0) + +#define TCP_EVENT_CONNECTED(pcb,err,ret) \ + do { \ + if((pcb)->connected != NULL) \ + (ret) = (pcb)->connected((pcb)->callback_arg,(pcb),(err)); \ + else (ret) = ERR_OK; \ + } while (0) + +#define TCP_EVENT_POLL(pcb,ret) \ + do { \ + if((pcb)->poll != NULL) \ + (ret) = (pcb)->poll((pcb)->callback_arg,(pcb)); \ + else (ret) = ERR_OK; \ + } while (0) + +#define TCP_EVENT_ERR(errf,arg,err) \ + do { \ + if((errf) != NULL) \ + (errf)((arg),(err)); \ + } while (0) + +#endif /* LWIP_EVENT_API */ + +/* This structure represents a TCP segment on the unsent and unacked queues */ +struct tcp_seg { + struct tcp_seg *next; /* used when putting segements on a queue */ + struct pbuf *p; /* buffer containing data + TCP header */ + void *dataptr; /* pointer to the TCP data in the pbuf */ + u16_t len; /* the TCP length of this segment */ + u8_t flags; +#define TF_SEG_OPTS_MSS (u8_t)0x01U /* Include MSS option. */ +#define TF_SEG_OPTS_TS (u8_t)0x02U /* Include timestamp option. */ + struct tcp_hdr *tcphdr; /* the TCP header */ +}; + +#define LWIP_TCP_OPT_LENGTH(flags) \ + (flags & TF_SEG_OPTS_MSS ? 4 : 0) + \ + (flags & TF_SEG_OPTS_TS ? 12 : 0) + +/** This returns a TCP header option for MSS in an u32_t */ +#define TCP_BUILD_MSS_OPTION(x) (x) = htonl(((u32_t)2 << 24) | \ + ((u32_t)4 << 16) | \ + (((u32_t)TCP_MSS / 256) << 8) | \ + (TCP_MSS & 255)) + +/* Internal functions and global variables: */ +struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb); +void tcp_pcb_purge(struct tcp_pcb *pcb); +void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb); + +u8_t tcp_segs_free(struct tcp_seg *seg); +u8_t tcp_seg_free(struct tcp_seg *seg); +struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg); + +#define tcp_ack(pcb) \ + do { \ + if((pcb)->flags & TF_ACK_DELAY) { \ + (pcb)->flags &= ~TF_ACK_DELAY; \ + (pcb)->flags |= TF_ACK_NOW; \ + tcp_output(pcb); \ + } \ + else { \ + (pcb)->flags |= TF_ACK_DELAY; \ + } \ + } while (0) + +#define tcp_ack_now(pcb) \ + do { \ + (pcb)->flags |= TF_ACK_NOW; \ + tcp_output(pcb); \ + } while (0) + +err_t tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags); +err_t tcp_enqueue(struct tcp_pcb *pcb, void *dataptr, u16_t len, + u8_t flags, u8_t apiflags, u8_t optflags); + +void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg); + +void tcp_rst(u32_t seqno, u32_t ackno, + struct ip_addr *local_ip, struct ip_addr *remote_ip, + u16_t local_port, u16_t remote_port); + +u32_t tcp_next_iss(void); + +void tcp_keepalive(struct tcp_pcb *pcb); +void tcp_zero_window_probe(struct tcp_pcb *pcb); + +#if TCP_CALCULATE_EFF_SEND_MSS +u16_t tcp_eff_send_mss(u16_t sendmss, struct ip_addr *addr); +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + +extern struct tcp_pcb *tcp_input_pcb; +extern u32_t tcp_ticks; + +#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG +void tcp_debug_print(struct tcp_hdr *tcphdr); +void tcp_debug_print_flags(u8_t flags); +void tcp_debug_print_state(enum tcp_state s); +void tcp_debug_print_pcbs(void); +s16_t tcp_pcbs_sane(void); +#else +# define tcp_debug_print(tcphdr) +# define tcp_debug_print_flags(flags) +# define tcp_debug_print_state(s) +# define tcp_debug_print_pcbs() +# define tcp_pcbs_sane() 1 +#endif /* TCP_DEBUG */ + +#if NO_SYS +#define tcp_timer_needed() +#else +void tcp_timer_needed(void); +#endif + +/* The TCP PCB lists. */ +union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */ + struct tcp_pcb_listen *listen_pcbs; + struct tcp_pcb *pcbs; +}; +extern union tcp_listen_pcbs_t tcp_listen_pcbs; +extern struct tcp_pcb *tcp_active_pcbs; /* List of all TCP PCBs that are in a + state in which they accept or send + data. */ +extern struct tcp_pcb *tcp_tw_pcbs; /* List of all TCP PCBs in TIME-WAIT. */ + +extern struct tcp_pcb *tcp_tmp_pcb; /* Only used for temporary storage. */ + +/* Axioms about the above lists: + 1) Every TCP PCB that is not CLOSED is in one of the lists. + 2) A PCB is only in one of the lists. + 3) All PCBs in the tcp_listen_pcbs list is in LISTEN state. + 4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state. +*/ + +/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB + with a PCB list or removes a PCB from a list, respectively. */ +#if 0 +#define TCP_REG(pcbs, npcb) do {\ + LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %d\n", npcb, npcb->local_port)); \ + for(tcp_tmp_pcb = *pcbs; \ + tcp_tmp_pcb != NULL; \ + tcp_tmp_pcb = tcp_tmp_pcb->next) { \ + LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != npcb); \ + } \ + LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", npcb->state != CLOSED); \ + npcb->next = *pcbs; \ + LWIP_ASSERT("TCP_REG: npcb->next != npcb", npcb->next != npcb); \ + *(pcbs) = npcb; \ + LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \ + tcp_timer_needed(); \ + } while(0) +#define TCP_RMV(pcbs, npcb) do { \ + LWIP_ASSERT("TCP_RMV: pcbs != NULL", *pcbs != NULL); \ + LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", npcb, *pcbs)); \ + if(*pcbs == npcb) { \ + *pcbs = (*pcbs)->next; \ + } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \ + if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \ + tcp_tmp_pcb->next = npcb->next; \ + break; \ + } \ + } \ + npcb->next = NULL; \ + LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \ + LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", npcb, *pcbs)); \ + } while(0) + +#else /* LWIP_DEBUG */ + +#define TCP_REG(pcbs, npcb) \ + do { \ + npcb->next = *pcbs; \ + *(pcbs) = npcb; \ + tcp_timer_needed(); \ + } while (0) + +#define TCP_RMV(pcbs, npcb) \ + do { \ + if(*(pcbs) == npcb) { \ + (*(pcbs)) = (*pcbs)->next; \ + } \ + else { \ + for(tcp_tmp_pcb = *pcbs; \ + tcp_tmp_pcb != NULL; \ + tcp_tmp_pcb = tcp_tmp_pcb->next) { \ + if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \ + tcp_tmp_pcb->next = npcb->next; \ + break; \ + } \ + } \ + } \ + npcb->next = NULL; \ + } while(0) + +#endif /* LWIP_DEBUG */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_TCP */ + +#endif /* __LWIP_TCP_H__ */ diff --git a/firmware/octoclock/include/lwip/tcpip.h b/firmware/octoclock/include/lwip/tcpip.h new file mode 100644 index 000000000..75393ee91 --- /dev/null +++ b/firmware/octoclock/include/lwip/tcpip.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __LWIP_TCPIP_H__ +#define __LWIP_TCPIP_H__ + +#include "lwip/opt.h" + +#if !NO_SYS /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/api_msg.h" +#include "lwip/netifapi.h" +#include "lwip/pbuf.h" +#include "lwip/api.h" +#include "lwip/sys.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if LWIP_TCPIP_CORE_LOCKING +/** The global semaphore to lock the stack. */ +extern sys_sem_t lock_tcpip_core; +#define LOCK_TCPIP_CORE() sys_sem_wait(lock_tcpip_core) +#define UNLOCK_TCPIP_CORE() sys_sem_signal(lock_tcpip_core) +#define TCPIP_APIMSG(m) tcpip_apimsg_lock(m) +#define TCPIP_APIMSG_ACK(m) +#define TCPIP_NETIFAPI(m) tcpip_netifapi_lock(m) +#define TCPIP_NETIFAPI_ACK(m) +#else +#define LOCK_TCPIP_CORE() +#define UNLOCK_TCPIP_CORE() +#define TCPIP_APIMSG(m) tcpip_apimsg(m) +#define TCPIP_APIMSG_ACK(m) sys_sem_signal(m->conn->op_completed) +#define TCPIP_NETIFAPI(m) tcpip_netifapi(m) +#define TCPIP_NETIFAPI_ACK(m) sys_sem_signal(m->sem) +#endif /* LWIP_TCPIP_CORE_LOCKING */ + +void tcpip_init(void (* tcpip_init_done)(void *), void *arg); + +#if LWIP_NETCONN +err_t tcpip_apimsg(struct api_msg *apimsg); +#if LWIP_TCPIP_CORE_LOCKING +err_t tcpip_apimsg_lock(struct api_msg *apimsg); +#endif /* LWIP_TCPIP_CORE_LOCKING */ +#endif /* LWIP_NETCONN */ + +err_t tcpip_input(struct pbuf *p, struct netif *inp); + +#if LWIP_NETIF_API +err_t tcpip_netifapi(struct netifapi_msg *netifapimsg); +#if LWIP_TCPIP_CORE_LOCKING +err_t tcpip_netifapi_lock(struct netifapi_msg *netifapimsg); +#endif /* LWIP_TCPIP_CORE_LOCKING */ +#endif /* LWIP_NETIF_API */ + +err_t tcpip_callback_with_block(void (*f)(void *ctx), void *ctx, u8_t block); +#define tcpip_callback(f, ctx) tcpip_callback_with_block(f, ctx, 1) + +/* free pbufs or heap memory from another context without blocking */ +err_t pbuf_free_callback(struct pbuf *p); +err_t mem_free_callback(void *m); + +err_t tcpip_timeout(u32_t msecs, sys_timeout_handler h, void *arg); +err_t tcpip_untimeout(sys_timeout_handler h, void *arg); + +enum tcpip_msg_type { +#if LWIP_NETCONN + TCPIP_MSG_API, +#endif /* LWIP_NETCONN */ + TCPIP_MSG_INPKT, +#if LWIP_NETIF_API + TCPIP_MSG_NETIFAPI, +#endif /* LWIP_NETIF_API */ + TCPIP_MSG_CALLBACK, + TCPIP_MSG_TIMEOUT, + TCPIP_MSG_UNTIMEOUT +}; + +struct tcpip_msg { + enum tcpip_msg_type type; + sys_sem_t *sem; + union { +#if LWIP_NETCONN + struct api_msg *apimsg; +#endif /* LWIP_NETCONN */ +#if LWIP_NETIF_API + struct netifapi_msg *netifapimsg; +#endif /* LWIP_NETIF_API */ + struct { + struct pbuf *p; + struct netif *netif; + } inp; + struct { + void (*f)(void *ctx); + void *ctx; + } cb; + struct { + u32_t msecs; + sys_timeout_handler h; + void *arg; + } tmo; + } msg; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* !NO_SYS */ + +#endif /* __LWIP_TCPIP_H__ */ diff --git a/firmware/octoclock/include/lwip/udp.h b/firmware/octoclock/include/lwip/udp.h new file mode 100644 index 000000000..d7b2a3820 --- /dev/null +++ b/firmware/octoclock/include/lwip/udp.h @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __LWIP_UDP_H__ +#define __LWIP_UDP_H__ + +#include "lwip/opt.h" + +#if LWIP_UDP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/pbuf.h" +#include "lwip/netif.h" +#include "lwip/ip_addr.h" +#include "lwip/ip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define UDP_HLEN 8 + +/* Fields are (of course) in network byte order. */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct udp_hdr { + PACK_STRUCT_FIELD(u16_t src); + PACK_STRUCT_FIELD(u16_t dest); /* src/dest UDP ports */ + PACK_STRUCT_FIELD(u16_t len); + PACK_STRUCT_FIELD(u16_t chksum); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define UDP_FLAGS_NOCHKSUM 0x01U +#define UDP_FLAGS_UDPLITE 0x02U +#define UDP_FLAGS_CONNECTED 0x04U + +struct udp_pcb { +/* Common members of all PCB types */ + IP_PCB; + +/* Protocol specific PCB members */ + + struct udp_pcb *next; + + u8_t flags; + /* ports are in host byte order */ + u16_t local_port, remote_port; + +#if LWIP_IGMP + /* outgoing network interface for multicast packets */ + struct ip_addr multicast_ip; +#endif /* LWIP_IGMP */ + +#if LWIP_UDPLITE + /* used for UDP_LITE only */ + u16_t chksum_len_rx, chksum_len_tx; +#endif /* LWIP_UDPLITE */ + + /* receive callback function + * addr and port are in same byte order as in the pcb + * The callback is responsible for freeing the pbuf + * if it's not used any more. + * + * @param arg user supplied argument (udp_pcb.recv_arg) + * @param pcb the udp_pcb which received data + * @param p the packet buffer that was received + * @param addr the remote IP address from which the packet was received + * @param port the remote port from which the packet was received + */ + void (* recv)(void *arg, struct udp_pcb *pcb, struct pbuf *p, + struct ip_addr *addr, u16_t port); + /* user-supplied argument for the recv callback */ + void *recv_arg; +}; +/* udp_pcbs export for exernal reference (e.g. SNMP agent) */ +extern struct udp_pcb *udp_pcbs; + +/* The following functions is the application layer interface to the + UDP code. */ +struct udp_pcb * udp_new (void); +void udp_remove (struct udp_pcb *pcb); +err_t udp_bind (struct udp_pcb *pcb, struct ip_addr *ipaddr, + u16_t port); +err_t udp_connect (struct udp_pcb *pcb, struct ip_addr *ipaddr, + u16_t port); +void udp_disconnect (struct udp_pcb *pcb); +void udp_recv (struct udp_pcb *pcb, + void (* recv)(void *arg, struct udp_pcb *upcb, + struct pbuf *p, + struct ip_addr *addr, + u16_t port), + void *recv_arg); +err_t udp_sendto_if (struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *dst_ip, u16_t dst_port, struct netif *netif); +err_t udp_sendto (struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *dst_ip, u16_t dst_port); +err_t udp_send (struct udp_pcb *pcb, struct pbuf *p); + +#define udp_flags(pcb) ((pcb)->flags) +#define udp_setflags(pcb, f) ((pcb)->flags = (f)) + +/* The following functions are the lower layer interface to UDP. */ +void udp_input (struct pbuf *p, struct netif *inp); + +#define udp_init() /* Compatibility define, not init needed. */ + +#if UDP_DEBUG +void udp_debug_print(struct udp_hdr *udphdr); +#else +#define udp_debug_print(udphdr) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_UDP */ + +#endif /* __LWIP_UDP_H__ */ diff --git a/firmware/octoclock/include/lwipopts.h b/firmware/octoclock/include/lwipopts.h new file mode 100644 index 000000000..3839eea83 --- /dev/null +++ b/firmware/octoclock/include/lwipopts.h @@ -0,0 +1,196 @@ +/* -*- c++ -*- */ +/* + * Copyright 2009 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* + * Our lwip options + */ + +#define NO_SYS 1 + + +// ---------- Memory options ---------- +/** + * MEM_ALIGNMENT: should be set to the alignment of the CPU + * 4 byte alignment -> #define MEM_ALIGNMENT 4 + * 2 byte alignment -> #define MEM_ALIGNMENT 2 + */ +#define MEM_ALIGNMENT 4 + +/** + * MEM_SIZE: the size of the heap memory. If the application will send + * a lot of data that needs to be copied, this should be set high. + */ +#define MEM_SIZE 256 + +/** + * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set + * of memory pools of various sizes. When mem_malloc is called, an element of + * the smallest pool that can provide the lenght needed is returned. + */ +#define MEM_USE_POOLS 0 + +/** + * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h + * that defines additional pools beyond the "standard" ones required + * by lwIP. If you set this to 1, you must have lwippools.h in your + * inlude path somewhere. + */ +#define MEMP_USE_CUSTOM_POOLS 0 + +// ---------- Internal Memory Pool Sizes ---------- +/** + * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF). + * If the application sends a lot of data out of ROM (or other static memory), + * this should be set high. + */ +#define MEMP_NUM_PBUF 8 + +/** + * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + * per active UDP "connection". + * (requires the LWIP_UDP option) + */ +#define MEMP_NUM_UDP_PCB 4 + +/** + * PBUF_LINK_HLEN: the number of bytes that should be allocated for a + * link level header. The default is 14, the standard value for + * Ethernet. + */ +#define PBUF_LINK_HLEN 16 +#define ETH_PAD_SIZE 2 + +/** + * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. + */ +#define PBUF_POOL_SIZE 8 + +/** + * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is + * designed to accomodate single full size TCP frame in one pbuf, including + * TCP_MSS, IP header, and link header. + */ +//#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN) +#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(128+28+PBUF_LINK_HLEN) + + +// ---------- ARP options ---------- +/** + * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached. + */ +#define ARP_TABLE_SIZE 5 + +/** + * ARP_QUEUEING==1: Outgoing packets are queued during hardware address + * resolution. + */ +#define ARP_QUEUEING 0 + +/** + * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing + * packets (pbufs) that are waiting for an ARP request (to resolve + * their destination address) to finish. + * (requires the ARP_QUEUEING option) + */ +#define MEMP_NUM_ARP_QUEUE 5 + +// ---------- IP options ---------- +/** + * IP_OPTIONS_ALLOWED: Defines the behavior for IP options. + * IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped. + * IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed). + */ +#define IP_OPTIONS_ALLOWED 0 + +/** + * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that + * this option does not affect outgoing packet sizes, which can be controlled + * via IP_FRAG. + */ +#define IP_REASSEMBLY 0 + +/** + * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note + * that this option does not affect incoming packet sizes, which can be + * controlled via IP_REASSEMBLY. + */ +#define IP_FRAG 0 + +/** + * LWIP_DHCP==1: Enable DHCP module. + */ +#define LWIP_DHCP 0 + +/** + * LWIP_IGMP==1: Turn on IGMP module. + */ +#define LWIP_IGMP 0 + +/** + * LWIP_UDP==1: Turn on UDP. + */ +#define LWIP_UDP 1 + +/** + * LWIP_TCP==1: Turn on TCP. + */ +#define LWIP_TCP 0 + +/** + * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) + */ +#define LWIP_NETCONN 0 + +/** + * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) + */ +#define LWIP_SOCKET 0 + +/** + * LWIP_STATS==1: Enable statistics collection in lwip_stats. + */ +#define LWIP_STATS 0 + +/** + * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets. + */ +#define CHECKSUM_GEN_IP 0 + +/** + * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets. + */ +#define CHECKSUM_GEN_UDP 0 + +/** + * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets. + */ +#define CHECKSUM_CHECK_IP 0 + +/** + * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets. + */ +#define CHECKSUM_CHECK_UDP 0 + +/** + * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface + * whenever the link changes (i.e., link down) + */ +#define LWIP_NETIF_LINK_CALLBACK 1 diff --git a/firmware/octoclock/include/lwippools.h b/firmware/octoclock/include/lwippools.h new file mode 100644 index 000000000..caee23c82 --- /dev/null +++ b/firmware/octoclock/include/lwippools.h @@ -0,0 +1,24 @@ +#ifndef INCLUDED_LWIPPOOLS_H +#define INCLUDED_LWIPPOOLS_H + +/* + * from comment at top of mem.c: + * + * To let mem_malloc() use pools (prevents fragmentation and is much faster than + * a heap but might waste some memory), define MEM_USE_POOLS to 1, define + * MEM_USE_CUSTOM_POOLS to 1 and create a file "lwippools.h" that includes a list + * of pools like this (more pools can be added between _START and _END): + * + * Define three pools with sizes 256, 512, and 1512 bytes + * LWIP_MALLOC_MEMPOOL_START + * LWIP_MALLOC_MEMPOOL(20, 256) + * LWIP_MALLOC_MEMPOOL(10, 512) + * LWIP_MALLOC_MEMPOOL(5, 1512) + * LWIP_MALLOC_MEMPOOL_END + */ + +LWIP_MALLOC_MEMPOOL_START +LWIP_MALLOC_MEMPOOL(2, 256) +LWIP_MALLOC_MEMPOOL_END + +#endif /* INCLUDED_LWIPPOOLS_H */ diff --git a/firmware/octoclock/include/net/enc28j60.h b/firmware/octoclock/include/net/enc28j60.h new file mode 100644 index 000000000..463303f3c --- /dev/null +++ b/firmware/octoclock/include/net/enc28j60.h @@ -0,0 +1,299 @@ +/*! \file enc28j60.h \brief Microchip ENC28J60 Ethernet Interface Driver. */ +//***************************************************************************** +// +// File Name : 'enc28j60.h' +// Title : Microchip ENC28J60 Ethernet Interface Driver +// Author : Pascal Stang (c)2005 +// Created : 9/22/2005 +// Revised : 9/22/2005 +// Version : 0.1 +// Target MCU : Atmel AVR series +// Editor Tabs : 4 +// +/// \ingroup network +/// \defgroup enc28j60 Microchip ENC28J60 Ethernet Interface Driver (enc28j60.c) +/// \code #include "net/enc28j60.h" \endcode +/// \par Overview +/// This driver provides initialization and transmit/receive +/// functions for the Microchip ENC28J60 10Mb Ethernet Controller and PHY. +/// This chip is novel in that it is a full MAC+PHY interface all in a 28-pin +/// chip, using an SPI interface to the host processor. +/// +// +//***************************************************************************** +//@{ + +#ifndef ENC28J60_H +#define ENC28J60_H + +#include <avrlibdefs.h> + +#include "enc28j60conf.h" + +// ENC28J60 Control Registers +// Control register definitions are a combination of address, +// bank number, and Ethernet/MAC/PHY indicator bits. +// - Register address (bits 0-4) +// - Bank number (bits 5-6) +// - MAC/PHY indicator (bit 7) +#define ADDR_MASK 0x1F +#define BANK_MASK 0x60 +#define SPRD_MASK 0x80 +// All-bank registers +#define EIE 0x1B +#define EIR 0x1C +#define ESTAT 0x1D +#define ECON2 0x1E +#define ECON1 0x1F +// Bank 0 registers +#define ERDPTL (0x00|0x00) +#define ERDPTH (0x01|0x00) +#define EWRPTL (0x02|0x00) +#define EWRPTH (0x03|0x00) +#define ETXSTL (0x04|0x00) +#define ETXSTH (0x05|0x00) +#define ETXNDL (0x06|0x00) +#define ETXNDH (0x07|0x00) +#define ERXSTL (0x08|0x00) +#define ERXSTH (0x09|0x00) +#define ERXNDL (0x0A|0x00) +#define ERXNDH (0x0B|0x00) +#define ERXRDPTL (0x0C|0x00) +#define ERXRDPTH (0x0D|0x00) +#define ERXWRPTL (0x0E|0x00) +#define ERXWRPTH (0x0F|0x00) +#define EDMASTL (0x10|0x00) +#define EDMASTH (0x11|0x00) +#define EDMANDL (0x12|0x00) +#define EDMANDH (0x13|0x00) +#define EDMADSTL (0x14|0x00) +#define EDMADSTH (0x15|0x00) +#define EDMACSL (0x16|0x00) +#define EDMACSH (0x17|0x00) +// Bank 1 registers +#define EHT0 (0x00|0x20) +#define EHT1 (0x01|0x20) +#define EHT2 (0x02|0x20) +#define EHT3 (0x03|0x20) +#define EHT4 (0x04|0x20) +#define EHT5 (0x05|0x20) +#define EHT6 (0x06|0x20) +#define EHT7 (0x07|0x20) +#define EPMM0 (0x08|0x20) +#define EPMM1 (0x09|0x20) +#define EPMM2 (0x0A|0x20) +#define EPMM3 (0x0B|0x20) +#define EPMM4 (0x0C|0x20) +#define EPMM5 (0x0D|0x20) +#define EPMM6 (0x0E|0x20) +#define EPMM7 (0x0F|0x20) +#define EPMCSL (0x10|0x20) +#define EPMCSH (0x11|0x20) +#define EPMOL (0x14|0x20) +#define EPMOH (0x15|0x20) +#define EWOLIE (0x16|0x20) +#define EWOLIR (0x17|0x20) +#define ERXFCON (0x18|0x20) +#define EPKTCNT (0x19|0x20) +// Bank 2 registers +#define MACON1 (0x00|0x40|0x80) +#define MACON2 (0x01|0x40|0x80) +#define MACON3 (0x02|0x40|0x80) +#define MACON4 (0x03|0x40|0x80) +#define MABBIPG (0x04|0x40|0x80) +#define MAIPGL (0x06|0x40|0x80) +#define MAIPGH (0x07|0x40|0x80) +#define MACLCON1 (0x08|0x40|0x80) +#define MACLCON2 (0x09|0x40|0x80) +#define MAMXFLL (0x0A|0x40|0x80) +#define MAMXFLH (0x0B|0x40|0x80) +#define MAPHSUP (0x0D|0x40|0x80) +#define MICON (0x11|0x40|0x80) +#define MICMD (0x12|0x40|0x80) +#define MIREGADR (0x14|0x40|0x80) +#define MIWRL (0x16|0x40|0x80) +#define MIWRH (0x17|0x40|0x80) +#define MIRDL (0x18|0x40|0x80) +#define MIRDH (0x19|0x40|0x80) +// Bank 3 registers +#define MAADR1 (0x00|0x60|0x80) +#define MAADR0 (0x01|0x60|0x80) +#define MAADR3 (0x02|0x60|0x80) +#define MAADR2 (0x03|0x60|0x80) +#define MAADR5 (0x04|0x60|0x80) +#define MAADR4 (0x05|0x60|0x80) +#define EBSTSD (0x06|0x60) +#define EBSTCON (0x07|0x60) +#define EBSTCSL (0x08|0x60) +#define EBSTCSH (0x09|0x60) +#define MISTAT (0x0A|0x60|0x80) +#define EREVID (0x12|0x60) +#define ECOCON (0x15|0x60) +#define EFLOCON (0x17|0x60) +#define EPAUSL (0x18|0x60) +#define EPAUSH (0x19|0x60) +// PHY registers +#define PHCON1 0x00 +#define PHSTAT1 0x01 +#define PHHID1 0x02 +#define PHHID2 0x03 +#define PHCON2 0x10 +#define PHSTAT2 0x11 +#define PHIE 0x12 +#define PHIR 0x13 +#define PHLCON 0x14 + +// ENC28J60 EIE Register Bit Definitions +#define EIE_INTIE 0x80 +#define EIE_PKTIE 0x40 +#define EIE_DMAIE 0x20 +#define EIE_LINKIE 0x10 +#define EIE_TXIE 0x08 +#define EIE_WOLIE 0x04 +#define EIE_TXERIE 0x02 +#define EIE_RXERIE 0x01 +// ENC28J60 EIR Register Bit Definitions +#define EIR_PKTIF 0x40 +#define EIR_DMAIF 0x20 +#define EIR_LINKIF 0x10 +#define EIR_TXIF 0x08 +#define EIR_WOLIF 0x04 +#define EIR_TXERIF 0x02 +#define EIR_RXERIF 0x01 +// ENC28J60 ESTAT Register Bit Definitions +#define ESTAT_INT 0x80 +#define ESTAT_LATECOL 0x10 +#define ESTAT_RXBUSY 0x04 +#define ESTAT_TXABRT 0x02 +#define ESTAT_CLKRDY 0x01 +// ENC28J60 ECON2 Register Bit Definitions +#define ECON2_AUTOINC 0x80 +#define ECON2_PKTDEC 0x40 +#define ECON2_PWRSV 0x20 +#define ECON2_VRPS 0x08 +// ENC28J60 ECON1 Register Bit Definitions +#define ECON1_TXRST 0x80 +#define ECON1_RXRST 0x40 +#define ECON1_DMAST 0x20 +#define ECON1_CSUMEN 0x10 +#define ECON1_TXRTS 0x08 +#define ECON1_RXEN 0x04 +#define ECON1_BSEL1 0x02 +#define ECON1_BSEL0 0x01 +// ENC28J60 MACON1 Register Bit Definitions +#define MACON1_LOOPBK 0x10 +#define MACON1_TXPAUS 0x08 +#define MACON1_RXPAUS 0x04 +#define MACON1_PASSALL 0x02 +#define MACON1_MARXEN 0x01 +// ENC28J60 MACON2 Register Bit Definitions +#define MACON2_MARST 0x80 +#define MACON2_RNDRST 0x40 +#define MACON2_MARXRST 0x08 +#define MACON2_RFUNRST 0x04 +#define MACON2_MATXRST 0x02 +#define MACON2_TFUNRST 0x01 +// ENC28J60 MACON3 Register Bit Definitions +#define MACON3_PADCFG2 0x80 +#define MACON3_PADCFG1 0x40 +#define MACON3_PADCFG0 0x20 +#define MACON3_TXCRCEN 0x10 +#define MACON3_PHDRLEN 0x08 +#define MACON3_HFRMLEN 0x04 +#define MACON3_FRMLNEN 0x02 +#define MACON3_FULDPX 0x01 +// ENC28J60 MICMD Register Bit Definitions +#define MICMD_MIISCAN 0x02 +#define MICMD_MIIRD 0x01 +// ENC28J60 MISTAT Register Bit Definitions +#define MISTAT_NVALID 0x04 +#define MISTAT_SCAN 0x02 +#define MISTAT_BUSY 0x01 +// ENC28J60 PHY PHCON1 Register Bit Definitions +#define PHCON1_PRST 0x8000 +#define PHCON1_PLOOPBK 0x4000 +#define PHCON1_PPWRSV 0x0800 +#define PHCON1_PDPXMD 0x0100 +// ENC28J60 PHY PHSTAT1 Register Bit Definitions +#define PHSTAT1_PFDPX 0x1000 +#define PHSTAT1_PHDPX 0x0800 +#define PHSTAT1_LLSTAT 0x0004 +#define PHSTAT1_JBSTAT 0x0002 +// ENC28J60 PHY PHCON2 Register Bit Definitions +#define PHCON2_FRCLINK 0x4000 +#define PHCON2_TXDIS 0x2000 +#define PHCON2_JABBER 0x0400 +#define PHCON2_HDLDIS 0x0100 + +// ENC28J60 Packet Control Byte Bit Definitions +#define PKTCTRL_PHUGEEN 0x08 +#define PKTCTRL_PPADEN 0x04 +#define PKTCTRL_PCRCEN 0x02 +#define PKTCTRL_POVERRIDE 0x01 + +// SPI operation codes +#define ENC28J60_READ_CTRL_REG 0x00 +#define ENC28J60_READ_BUF_MEM 0x3A +#define ENC28J60_WRITE_CTRL_REG 0x40 +#define ENC28J60_WRITE_BUF_MEM 0x7A +#define ENC28J60_BIT_FIELD_SET 0x80 +#define ENC28J60_BIT_FIELD_CLR 0xA0 +#define ENC28J60_SOFT_RESET 0xFF + + +// buffer boundaries applied to internal 8K ram +// entire available packet buffer space is allocated +#define TXSTART_INIT 0x0000 // start TX buffer at 0 +#define RXSTART_INIT 0x0600 // give TX buffer space for one full ethernet frame (~1500 bytes) +#define RXSTOP_INIT 0x1FFF // receive buffer gets the rest + +#define MAX_FRAMELEN 1518 // maximum ethernet frame length + +// Ethernet constants +#define ETHERNET_MIN_PACKET_LENGTH 0x3C +//#define ETHERNET_HEADER_LENGTH 0x0E + +// setup ports for I/O +//void ax88796SetupPorts(void); + +//! do a ENC28J60 read operation +u08 enc28j60ReadOp(u08 op, u08 address); +//! do a ENC28J60 write operation +void enc28j60WriteOp(u08 op, u08 address, u08 data); +//! read the packet buffer memory +void enc28j60ReadBuffer(u16 len, u08* data); +//! write the packet buffer memory +void enc28j60WriteBuffer(u16 len, u08* data); +//! set the register bank for register at address +void enc28j60SetBank(u08 address); +//! read ax88796 register +u08 enc28j60Read(u08 address); +//! write ax88796 register +void enc28j60Write(u08 address, u08 data); +//! read a PHY register +u16 enc28j60PhyRead(u08 address); +//! write a PHY register +void enc28j60PhyWrite(u08 address, u16 data); + +//! initialize the ethernet interface for transmit/receive +void enc28j60Init(u08* macaddr); + +//! Packet transmit function. +/// Sends a packet on the network. It is assumed that the packet is headed by a valid ethernet header. +/// \param len Length of packet in bytes. +/// \param packet Pointer to packet data. +/// \param len2 Length of the secound packet in bytes, can be 0. +/// \param packet2 Pointer to the secound packet data, can be NULL. +void enc28j60PacketSend(unsigned int len1, unsigned char* packet1, unsigned int len2, unsigned char* packet2); + +//! Packet receive function. +/// Gets a packet from the network receive buffer, if one is available. +/// The packet will by headed by an ethernet header. +/// \param maxlen The maximum acceptable length of a retrieved packet. +/// \param buf Pointer to buffer. +/// \return Packet length in bytes if a packet was retrieved, zero otherwise. +unsigned int enc28j60PacketReceive(unsigned int maxlen, u08* buf); + +#endif +//@} + diff --git a/firmware/octoclock/include/net/enc28j60conf.h b/firmware/octoclock/include/net/enc28j60conf.h new file mode 100644 index 000000000..0acf5473c --- /dev/null +++ b/firmware/octoclock/include/net/enc28j60conf.h @@ -0,0 +1,49 @@ +/*! \file enc28j60conf.h \brief Microchip ENC28J60 Ethernet Interface Driver Configuration. */ +//***************************************************************************** +// +// File Name : 'enc28j60conf.h' +// Title : Microchip ENC28J60 Ethernet Interface Driver Configuration +// Author : Pascal Stang +// Created : 10/5/2004 +// Revised : 8/22/2005 +// Version : 0.1 +// Target MCU : Atmel AVR series +// Editor Tabs : 4 +// +// Description : This driver provides initialization and transmit/receive +// functions for the ENC28J60 10Mb Ethernet Controller and PHY. +// +// This code is distributed under the GNU Public License +// which can be found at http://www.gnu.org/licenses/gpl.txt +// +//***************************************************************************** + +#ifndef ENC28J60CONF_H +#define ENC28J60CONF_H + +#include <stdint.h> +typedef uint8_t u08; +typedef uint16_t u16; +typedef uint32_t u32; + +// ENC28J60 SPI port +#define ENC28J60_SPI_PORT PORTB +#define ENC28J60_SPI_DDR DDRB +#define ENC28J60_SPI_SCK PORTB1 +#define ENC28J60_SPI_MOSI PORTB2 +#define ENC28J60_SPI_MISO PORTB3 +#define ENC28J60_SPI_SS PORTB0 +// ENC28J60 control port +#define ENC28J60_CONTROL_PORT PORTB +#define ENC28J60_CONTROL_DDR DDRB +#define ENC28J60_CONTROL_CS PORTB0 + +// MAC address for this interface +#define ENC28J60_MAC0 '0' +#define ENC28J60_MAC1 'F' +#define ENC28J60_MAC2 'F' +#define ENC28J60_MAC3 'I' +#define ENC28J60_MAC4 'C' +#define ENC28J60_MAC5 'E' + +#endif /* ENC28J60CONF_H */ diff --git a/firmware/octoclock/include/net/eth_hdr.h b/firmware/octoclock/include/net/eth_hdr.h new file mode 100644 index 000000000..9d5356c66 --- /dev/null +++ b/firmware/octoclock/include/net/eth_hdr.h @@ -0,0 +1,36 @@ +/* -*- c++ -*- */ +/* + * Copyright 2009,2010,2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef INCLUDED_ETH_HDR_H +#define INCLUDED_ETH_HDR_H + +#include <compiler.h> +#include <net/eth_mac_addr.h> + +#define ETH_HLEN 14 + +/*! + * \brief Standard 14-byte ethernet header. + */ + +typedef struct { + eth_mac_addr_t dst; + eth_mac_addr_t src; + uint16_t ethertype; +} _AL2 eth_hdr_t; + +#endif /* INCLUDED_ETH_HDR_H */ diff --git a/firmware/octoclock/include/net/eth_mac_addr.h b/firmware/octoclock/include/net/eth_mac_addr.h new file mode 100644 index 000000000..0c790aa4f --- /dev/null +++ b/firmware/octoclock/include/net/eth_mac_addr.h @@ -0,0 +1,31 @@ +/* + * Copyright 2009-2011,2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef INCLUDED_ETH_MAC_ADDR_H +#define INCLUDED_ETH_MAC_ADDR_H + +#include <stdint.h> + +// Ethernet MAC address + +#pragma pack(push,1) +typedef struct { + uint8_t addr[6]; +} eth_mac_addr_t; +#pragma pack(pop) + +#endif /* INCLUDED_ETH_MAC_ADDR_H */ diff --git a/firmware/octoclock/include/net/ethertype.h b/firmware/octoclock/include/net/ethertype.h new file mode 100644 index 000000000..0cfab8d65 --- /dev/null +++ b/firmware/octoclock/include/net/ethertype.h @@ -0,0 +1,27 @@ +/* -*- c++ -*- */ +/* + * Copyright 2009-2011,2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef INCLUDED_ETHERTYPE_H +#define INCLUDED_ETHERTYPE_H + +// all we care about + +#define ETHERTYPE_IPV4 0x0800 +#define ETHERTYPE_ARP 0x0806 + + +#endif /* INCLUDED_ETHERTYPE_H */ diff --git a/firmware/octoclock/include/net/if_arp.h b/firmware/octoclock/include/net/if_arp.h new file mode 100644 index 000000000..63519c4be --- /dev/null +++ b/firmware/octoclock/include/net/if_arp.h @@ -0,0 +1,153 @@ +/* + * INET An implementation of the TCP/IP protocol suite for the LINUX + * operating system. INET is implemented using the BSD Socket + * interface as the means of communication with the user level. + * + * Global definitions for the ARP (RFC 826) protocol. + * + * Version: @(#)if_arp.h 1.0.1 04/16/93 + * + * Authors: Original taken from Berkeley UNIX 4.3, (c) UCB 1986-1988 + * Portions taken from the KA9Q/NOS (v2.00m PA0GRI) source. + * Ross Biro + * Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG> + * Florian La Roche, + * Jonathan Layes <layes@loran.com> + * Arnaldo Carvalho de Melo <acme@conectiva.com.br> ARPHRD_HWX25 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#ifndef _LINUX_IF_ARP_H +#define _LINUX_IF_ARP_H + +/* ARP protocol HARDWARE identifiers. */ +#define ARPHRD_NETROM 0 /* from KA9Q: NET/ROM pseudo */ +#define ARPHRD_ETHER 1 /* Ethernet 10Mbps */ +#define ARPHRD_EETHER 2 /* Experimental Ethernet */ +#define ARPHRD_AX25 3 /* AX.25 Level 2 */ +#define ARPHRD_PRONET 4 /* PROnet token ring */ +#define ARPHRD_CHAOS 5 /* Chaosnet */ +#define ARPHRD_IEEE802 6 /* IEEE 802.2 Ethernet/TR/TB */ +#define ARPHRD_ARCNET 7 /* ARCnet */ +#define ARPHRD_APPLETLK 8 /* APPLEtalk */ +#define ARPHRD_DLCI 15 /* Frame Relay DLCI */ +#define ARPHRD_ATM 19 /* ATM */ +#define ARPHRD_METRICOM 23 /* Metricom STRIP (new IANA id) */ +#define ARPHRD_IEEE1394 24 /* IEEE 1394 IPv4 - RFC 2734 */ +#define ARPHRD_EUI64 27 /* EUI-64 */ +#define ARPHRD_INFINIBAND 32 /* InfiniBand */ + +/* Dummy types for non ARP hardware */ +#define ARPHRD_SLIP 256 +#define ARPHRD_CSLIP 257 +#define ARPHRD_SLIP6 258 +#define ARPHRD_CSLIP6 259 +#define ARPHRD_RSRVD 260 /* Notional KISS type */ +#define ARPHRD_ADAPT 264 +#define ARPHRD_ROSE 270 +#define ARPHRD_X25 271 /* CCITT X.25 */ +#define ARPHRD_HWX25 272 /* Boards with X.25 in firmware */ +#define ARPHRD_CAN 280 /* Controller Area Network */ +#define ARPHRD_PPP 512 +#define ARPHRD_CISCO 513 /* Cisco HDLC */ +#define ARPHRD_HDLC ARPHRD_CISCO +#define ARPHRD_LAPB 516 /* LAPB */ +#define ARPHRD_DDCMP 517 /* Digital's DDCMP protocol */ +#define ARPHRD_RAWHDLC 518 /* Raw HDLC */ + +#define ARPHRD_TUNNEL 768 /* IPIP tunnel */ +#define ARPHRD_TUNNEL6 769 /* IP6IP6 tunnel */ +#define ARPHRD_FRAD 770 /* Frame Relay Access Device */ +#define ARPHRD_SKIP 771 /* SKIP vif */ +#define ARPHRD_LOOPBACK 772 /* Loopback device */ +#define ARPHRD_LOCALTLK 773 /* Localtalk device */ +#define ARPHRD_FDDI 774 /* Fiber Distributed Data Interface */ +#define ARPHRD_BIF 775 /* AP1000 BIF */ +#define ARPHRD_SIT 776 /* sit0 device - IPv6-in-IPv4 */ +#define ARPHRD_IPDDP 777 /* IP over DDP tunneller */ +#define ARPHRD_IPGRE 778 /* GRE over IP */ +#define ARPHRD_PIMREG 779 /* PIMSM register interface */ +#define ARPHRD_HIPPI 780 /* High Performance Parallel Interface */ +#define ARPHRD_ASH 781 /* Nexus 64Mbps Ash */ +#define ARPHRD_ECONET 782 /* Acorn Econet */ +#define ARPHRD_IRDA 783 /* Linux-IrDA */ +/* ARP works differently on different FC media .. so */ +#define ARPHRD_FCPP 784 /* Point to point fibrechannel */ +#define ARPHRD_FCAL 785 /* Fibrechannel arbitrated loop */ +#define ARPHRD_FCPL 786 /* Fibrechannel public loop */ +#define ARPHRD_FCFABRIC 787 /* Fibrechannel fabric */ + /* 787->799 reserved for fibrechannel media types */ +#define ARPHRD_IEEE802_TR 800 /* Magic type ident for TR */ +#define ARPHRD_IEEE80211 801 /* IEEE 802.11 */ +#define ARPHRD_IEEE80211_PRISM 802 /* IEEE 802.11 + Prism2 header */ +#define ARPHRD_IEEE80211_RADIOTAP 803 /* IEEE 802.11 + radiotap header */ + +#define ARPHRD_VOID 0xFFFF /* Void type, nothing is known */ +#define ARPHRD_NONE 0xFFFE /* zero header length */ + +/* ARP protocol opcodes. */ +#define ARPOP_REQUEST 1 /* ARP request */ +#define ARPOP_REPLY 2 /* ARP reply */ +#define ARPOP_RREQUEST 3 /* RARP request */ +#define ARPOP_RREPLY 4 /* RARP reply */ +#define ARPOP_InREQUEST 8 /* InARP request */ +#define ARPOP_InREPLY 9 /* InARP reply */ +#define ARPOP_NAK 10 /* (ATM)ARP NAK */ + + +/* ARP Flag values. */ +#define ATF_COM 0x02 /* completed entry (ha valid) */ +#define ATF_PERM 0x04 /* permanent entry */ +#define ATF_PUBL 0x08 /* publish entry */ +#define ATF_USETRAILERS 0x10 /* has requested trailers */ +#define ATF_NETMASK 0x20 /* want to use a netmask (only + for proxy entries) */ +#define ATF_DONTPUB 0x40 /* don't answer this addresses */ + +typedef unsigned short __be16; + +/* + * This structure defines an ethernet arp header. + */ +struct arphdr +{ + __be16 ar_hrd; /* format of hardware address */ + __be16 ar_pro; /* format of protocol address */ + unsigned char ar_hln; /* length of hardware address */ + unsigned char ar_pln; /* length of protocol address */ + __be16 ar_op; /* ARP opcode (command) */ + +#if 0 + /* + * Ethernet looks like this : This bit is variable sized however... + */ + unsigned char ar_sha[ETH_ALEN]; /* sender hardware address */ + unsigned char ar_sip[4]; /* sender IP address */ + unsigned char ar_tha[ETH_ALEN]; /* target hardware address */ + unsigned char ar_tip[4]; /* target IP address */ +#endif + +}; + +/* + * This structure defines an ethernet arp header. + */ +struct arp_eth_ipv4 +{ + __be16 ar_hrd; /* format of hardware address */ + __be16 ar_pro; /* format of protocol address */ + unsigned char ar_hln; /* length of hardware address */ + unsigned char ar_pln; /* length of protocol address */ + __be16 ar_op; /* ARP opcode (command) */ + + unsigned char ar_sha[6]; /* sender hardware address */ + unsigned char ar_sip[4]; /* sender IP address */ + unsigned char ar_tha[6]; /* target hardware address */ + unsigned char ar_tip[4]; /* target IP address */ +}; + + +#endif /* _LINUX_IF_ARP_H */ diff --git a/firmware/octoclock/include/net/socket_address.h b/firmware/octoclock/include/net/socket_address.h new file mode 100644 index 000000000..9d4b4c5b3 --- /dev/null +++ b/firmware/octoclock/include/net/socket_address.h @@ -0,0 +1,41 @@ +/* -*- c -*- */ +/* + * Copyright 2010,2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef INCLUDED_SOCKET_ADDRESS_H +#define INCLUDED_SOCKET_ADDRESS_H + +#include <lwip/ip_addr.h> + +// port and address are in network byte order + +typedef struct socket_address { + unsigned short port; + struct ip_addr addr; +} socket_address_t; + +static inline struct socket_address +make_socket_address(struct ip_addr addr, int port) +{ + struct socket_address r; + r.port = port; + r.addr = addr; + return r; +} + + + +#endif /* INCLUDED_SOCKET_ADDRESS_H */ diff --git a/firmware/octoclock/include/net/udp_handlers.h b/firmware/octoclock/include/net/udp_handlers.h new file mode 100644 index 000000000..3abc26a24 --- /dev/null +++ b/firmware/octoclock/include/net/udp_handlers.h @@ -0,0 +1,34 @@ +/* + * Copyright 2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _NET_UDP_HANDLERS_H_ +#define _NET_UDP_HANDLERS_H_ + +#include <network.h> +#include <net/socket_address.h> + +void handle_udp_ctrl_packet( + struct socket_address src, struct socket_address dst, + unsigned char *payload, int payload_len +); + +void handle_udp_gpsdo_packet( + struct socket_address src, struct socket_address dst, + unsigned char *payload, int payload_len +); + +#endif /* _NET_UDP_HANDLERS_H */ diff --git a/firmware/octoclock/include/network.h b/firmware/octoclock/include/network.h new file mode 100644 index 000000000..83e398bc5 --- /dev/null +++ b/firmware/octoclock/include/network.h @@ -0,0 +1,102 @@ +/* + * Copyright 2009-2012,2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef INCLUDED_NETWORK_H +#define INCLUDED_NETWORK_H + +#include <stdint.h> +#include <stddef.h> + +#include <octoclock.h> +#include <net/socket_address.h> +#include <net/eth_mac_addr.h> + +#include "octoclock/common.h" + +/* + * Without its own HTON[LS] included in this build, + * some of lwIP's #defines do nothing. + * These are substitutions with our own HTON[LS]. + */ +#define htons(n) (((((uint16_t)(n) & 0xFF)) << 8) | (((uint16_t)(n) & 0xFF00) >> 8)) +#define ntohs(n) htons(n) + +#define htonl(n) (((((uint32_t)(n) & 0xFF)) << 24) | \ + ((((uint32_t)(n) & 0xFF00)) << 8) | \ + ((((uint32_t)(n) & 0xFF0000)) >> 8) | \ + ((((uint32_t)(n) & 0xFF000000)) >> 24)) + +#define ntohl(n) htonl(n) + +#define _MAC_ADDR(mac_addr,a,b,c,d,e,f) mac_addr[0] = a; \ + mac_addr[1] = b; \ + mac_addr[2] = c; \ + mac_addr[3] = d; \ + mac_addr[4] = e; \ + mac_addr[5] = f; + +#define _MAC_SET_EQUAL(mac_addr1,mac_addr2) for(uint8_t i = 0; i < 6; i++) mac_addr1[i] = mac_addr2[i]; + +#define _IP(a,b,c,d) (((uint32_t)a << 24) | ((uint32_t)b << 16) | ((uint32_t)c << 8) | ((uint32_t)d << 0)) +#define _IPH_V(hdr) (ntohs((hdr)->_v_hl_tos) >> 12) +#define _IPH_HL(hdr) ((ntohs((hdr)->_v_hl_tos) >> 8) & 0x0f) +#define _IPH_TOS(hdr) (ntohs((hdr)->_v_hl_tos) & 0xff) +#define _IPH_LEN(hdr) (ntohs((hdr)->_len)) +#define _IPH_ID(hdr) (ntohs((hdr)->_id)) +#define _IPH_OFFSET(hdr) (ntohs((hdr)->_offset)) +#define _IPH_TTL(hdr) (ntohs((hdr)->_ttl_proto) >> 8) +#define _IPH_PROTO(hdr) (ntohs((hdr)->_ttl_proto) & 0xff) +#define _IPH_CHKSUM(hdr) (ntohs((hdr)->_chksum)) + +#define _IPH_VHLTOS_SET(hdr, v, hl, tos) (hdr)->_v_hl_tos = (htons(((v) << 12) | ((hl) << 8) | (tos))) +#define _IPH_LEN_SET(hdr, len) (hdr)->_len = (htons(len)) +#define _IPH_ID_SET(hdr, id) (hdr)->_id = (id) +#define _IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off) +#define _IPH_TTL_SET(hdr, ttl) (hdr)->_ttl_proto = (htons(_IPH_PROTO(hdr) | ((u16_t)(ttl) << 8))) +#define _IPH_PROTO_SET(hdr, proto) (hdr)->_ttl_proto = (htons((proto) | (_IPH_TTL(hdr) << 8))) +#define _IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum) + +bool using_network_defaults; + +// Ethernet I/O buffers +uint8_t buf_in[512]; +uint8_t buf_out[512]; + +// Default values loaded if EEPROM is incomplete +static const uint32_t blank_eeprom_ip = _IP(255,255,255,255); +static const uint32_t default_ip = _IP(192,168,10,3); +static const uint32_t default_dr = _IP(192,168,10,1); +static const uint32_t default_netmask = _IP(255,255,255,0); + +typedef void (*udp_receiver_t)(struct socket_address src, struct socket_address dst, + unsigned char *payload, int payload_len); + +void init_udp_listeners(void); + +void register_addrs(const eth_mac_addr_t *mac_addr, const struct ip_addr *ip_addr); + +void register_udp_listener(int port, udp_receiver_t rcvr); + +void send_udp_pkt(int src_port, struct socket_address dst, + const void *buf, size_t len); + +void handle_eth_packet(size_t recv_len); + +void network_check(void); + +void network_init(void); + +#endif /* INCLUDED_NETWORK_H */ diff --git a/firmware/octoclock/include/octoclock.h b/firmware/octoclock/include/octoclock.h new file mode 100644 index 000000000..849ab7f96 --- /dev/null +++ b/firmware/octoclock/include/octoclock.h @@ -0,0 +1,105 @@ +/* + * Copyright 2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _OCTOCLOCK_H_ +#define _OCTOCLOCK_H_ + +#include "octoclock/common.h" + +#include <stdbool.h> +#include <stdint.h> + +// Define frequency +#define F_CPU 12500000UL + +/* + * Timer 0 (8-bit) + * * Set prescaler to 8 + * * Enable overflow interrupt + * * Set timer to 0 + */ +#define TIMER0_INIT() TCCR0 = (1 << CS01); \ + TIMSK |= (1 << TOIE0); \ + TCNT0 = 0; +/* + * Timer 1 (16-bit) + * * Set prescaler to 1024 + * * Enable overflow interrupt + * * Set timer to 0 + */ +#define TIMER1_INIT() TCCR1B = (1 << CS12) | (1 << CS10); \ + TIMSK |= (1<<TOIE1); \ + TCNT1 = 0; + +#define TIMER1_ONE_SECOND ((uint32_t)(12207)) + +// Locations of OctoClock information in EEPROM +#define OCTOCLOCK_EEPROM_MAC_ADDR 0 +#define OCTOCLOCK_EEPROM_IP_ADDR 6 +#define OCTOCLOCK_EEPROM_DR_ADDR 10 +#define OCTOCLOCK_EEPROM_NETMASK 14 +#define OCTOCLOCK_EEPROM_SERIAL 18 +#define OCTOCLOCK_EEPROM_NAME 28 +#define OCTOCLOCK_EEPROM_REVISION 38 + +#define OCTOCLOCK_EEPROM_APP_LEN 100 +#define OCTOCLOCK_EEPROM_APP_CRC 102 + +/* turn a numeric literal into a hex constant + * (avoids problems with leading zeros) + * 8-bit constants max value 0x11111111, always fits in unsigned long + */ +#define HEX__(n) 0x##n##LU + +/* 8-bit conversion function */ +#define B8__(x) ((x&0x0000000FLU)?1:0) \ + +((x&0x000000F0LU)?2:0) \ + +((x&0x00000F00LU)?4:0) \ + +((x&0x0000F000LU)?8:0) \ + +((x&0x000F0000LU)?16:0) \ + +((x&0x00F00000LU)?32:0) \ + +((x&0x0F000000LU)?64:0) \ + +((x&0xF0000000LU)?128:0) + +/* for up to 8-bit binary constants */ +#define Bits_8(d) ((unsigned char)B8__(HEX__(d))) + +/* for up to 16-bit binary constants, MSB first */ +#define Bits_16(dmsb,dlsb) (((unsigned short)Bits_8(dmsb)<<8) \ + + Bits_8(dlsb)) + +/* for up to 32-bit binary constants, MSB first */ +#define Bits_32(dmsb,db2,db3,dlsb) (((unsigned long)Bits_8(dmsb)<<24) \ + + ((unsigned long)Bits_8(db2)<<16) \ + + ((unsigned long)Bits_8(db3)<<8) \ + + Bits_8(dlsb)) + +/* Sample usage: + * Bits_8(01010101) = 85 + * Bits_16(10101010,01010101) = 43605 + * Bits_32(10000000,11111111,10101010,01010101) = 2164238933 + */ + +typedef enum { + Top, + Middle, + Bottom +} LEDs; + +void setup_atmel_io_ports(void); + +#endif /* _OCTOCLOCK_H_ */ diff --git a/firmware/octoclock/include/serial.h b/firmware/octoclock/include/serial.h new file mode 100644 index 000000000..48a065dc5 --- /dev/null +++ b/firmware/octoclock/include/serial.h @@ -0,0 +1,37 @@ +/* + * Copyright 2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _SERIAL_H_ +#define _SERIAL_H_ + +#include <stdint.h> +#include <stdbool.h> + +#include <octoclock.h> + +#define BAUD_DELAY(baud) ((1.0 / (double)baud) * ((double)F_CPU / 8.0)) +#define BAUD_115200_DELAY BAUD_DELAY(115200) + +void serial_init(volatile uint8_t* port, uint8_t index); +void serial_tx_P(const char* message, volatile uint8_t* port, uint8_t index, bool newline); +void serial_tx(const char* message, volatile uint8_t* port, uint8_t index, bool newline); +void serial_tx_byte(uint8_t byte, volatile uint8_t* port, uint8_t index, bool newline); +void serial_tx_hex(uint8_t byte, volatile uint8_t* port, uint8_t index, bool newline); +char serial_rx_char(volatile uint8_t* port, uint8_t index); +char serial_rx_char_nowait(volatile uint8_t* port, uint8_t index); + +#endif /* _SERIAL_H_ */ diff --git a/firmware/octoclock/include/state.h b/firmware/octoclock/include/state.h new file mode 100644 index 000000000..9734948cf --- /dev/null +++ b/firmware/octoclock/include/state.h @@ -0,0 +1,44 @@ +/* + * Copyright 2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _STATE_H_ +#define _STATE_H_ + +#include <stdbool.h> + +#include <octoclock.h> + +// NOT PRESENT unless proven so... +static ref_t global_which_ref = NO_REF; +static bool global_gps_present = false; +static bool global_ext_ref_is_present = false; + +void led(LEDs which, int turn_it_on); + +void LEDs_off(void); + +void force_internal(void); + +void prefer_internal(void); + +void prefer_external(void); + +ref_t which_ref(void); + +switch_pos_t get_switch_pos(void); + +#endif /* _STATE_H_ */ diff --git a/firmware/octoclock/include/usart.h b/firmware/octoclock/include/usart.h new file mode 100644 index 000000000..35ee9eb95 --- /dev/null +++ b/firmware/octoclock/include/usart.h @@ -0,0 +1,34 @@ +/* + * Copyright 2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _USART_H_ +#define _USART_H_ + +#define USART_BAUDRATE 115200 +#define BAUD_PRESCALE 3 + +void usart_init(void); + +char usart_getc(void); + +char usart_getc_noblock(void); + +void usart_putc(char ch); + +void usart_putc_nowait(char ch); + +#endif /* _USART_H_ */ diff --git a/firmware/octoclock/lib/CMakeLists.txt b/firmware/octoclock/lib/CMakeLists.txt new file mode 100644 index 000000000..3c992399e --- /dev/null +++ b/firmware/octoclock/lib/CMakeLists.txt @@ -0,0 +1,37 @@ +# +# Copyright 2014 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +SET(lib_files + arp_cache.c + clkdist.c + enc28j60.c + gpsdo.c + init.c + network.c + state.c + udp_handlers.c + usart.c +) + +IF(OCTOCLOCK_DEBUG) + LIST(APPEND lib_files serial.c) +ENDIF(OCTOCLOCK_DEBUG) + +ADD_LIBRARY(octoclock ${lib_files}) +SET_TARGET_PROPERTIES(octoclock + PROPERTIES COMPILE_FLAGS "${CMAKE_C_FLAGS} -O2 -g" +) diff --git a/firmware/octoclock/lib/arp_cache.c b/firmware/octoclock/lib/arp_cache.c new file mode 100644 index 000000000..558632d7f --- /dev/null +++ b/firmware/octoclock/lib/arp_cache.c @@ -0,0 +1,87 @@ +/* -*- c++ -*- */ +/* + * Copyright 2009-2011,2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#include "arp_cache.h" +#include <stddef.h> + +typedef struct { + struct ip_addr ip; + eth_mac_addr_t mac; +} arp_cache_t; + +#define NENTRIES 8 // power-of-2 + +static size_t nentries; +static size_t victim; +static arp_cache_t cache[NENTRIES]; + +void +arp_cache_init(void) +{ + nentries = 0; + victim = 0; +} + +// returns non-negative index if found, else -1 +static int +arp_cache_lookup(const struct ip_addr *ip) +{ + int i; + for (i = 0; i < nentries; i++) + if (cache[i].ip.addr == ip->addr) + return i; + + return -1; +} + +static int +arp_cache_alloc(void) +{ + if (nentries < NENTRIES) + return nentries++; + + int i = victim; + victim = (victim + 1) % NENTRIES; + return i; +} + +void +arp_cache_update(const struct ip_addr *ip, + const eth_mac_addr_t *mac) +{ + int i = arp_cache_lookup(ip); + if (i < 0){ + i = arp_cache_alloc(); + cache[i].ip = *ip; + cache[i].mac = *mac; + } + else { + cache[i].mac = *mac; + } +} + +bool +arp_cache_lookup_mac(const struct ip_addr *ip, + eth_mac_addr_t *mac) +{ + int i = arp_cache_lookup(ip); + if (i < 0) + return false; + + *mac = cache[i].mac; + return true; +} diff --git a/firmware/octoclock/lib/arp_cache.h b/firmware/octoclock/lib/arp_cache.h new file mode 100644 index 000000000..38ac0a198 --- /dev/null +++ b/firmware/octoclock/lib/arp_cache.h @@ -0,0 +1,33 @@ +/* -*- c++ -*- */ +/* + * Copyright 2009-2011,2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef INCLUDED_ARP_CACHE_H +#define INCLUDED_ARP_CACHE_H + +#include <lwip/ip_addr.h> +#include <net/eth_mac_addr.h> +#include <stdbool.h> + +void arp_cache_init(void); + +void arp_cache_update(const struct ip_addr *ip, + const eth_mac_addr_t *mac); + +bool arp_cache_lookup_mac(const struct ip_addr *ip, + eth_mac_addr_t *mac); + +#endif /* INCLUDED_ARP_CACHE_H */ diff --git a/firmware/octoclock/lib/clkdist.c b/firmware/octoclock/lib/clkdist.c new file mode 100644 index 000000000..ed29510b6 --- /dev/null +++ b/firmware/octoclock/lib/clkdist.c @@ -0,0 +1,182 @@ +/* + * Copyright 2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <avr/io.h> + +#include <octoclock.h> +#include <clkdist.h> +#include <state.h> + +#define wait() for(uint16_t u=14000; u; u--) asm("nop"); + +#define CLK (PA0) // Shift by 0 bits +#define CE_ (PA1) // Is really the "Chip Disable" signal, as Hi disables SPI +#define MOSI (PA2) +#define MISO (PA3) +#define PD_ (PA4) +#define SYNC_ (PA5) + +// Table of 32-bit constants to be written to the TI chip's registers. These are +// from the "Special Settings" on Page 35 of the datasheet. +// For the GPS's 10 MHz output +static uint32_t table_Pri_Ref[] = { + Bits_32(1,01010100,0,0), // Reg 0 + Bits_32(1,01010100,0,0), // Outputs LVCMOS Positive&Negative Active - Non-inverted + Bits_32(1,01010100,0,0), + Bits_32(1,01010100,0,0), + Bits_32(1,01010100,0,0), // All have output divide ratio to be 1; Aux Output is OFF + Bits_32(0,0,1001,11010100), // Reg 5 LVCMOS in; p31 of TI datasheet + Bits_32(1,0,0010000,0), // Reg 6 // SCAS863A <96> NOVEMBER 2008 <96> REVISED JUNE 2011 + Bits_32(1,01000000,0,0), // Reg 7 + Bits_32(0,0,1,10000000) // Reg8 Status/Control +}; + +// For the External 10 MHz input LVDS with external termination, +// Effectively DC coupled +static uint32_t table_Sec_Ref[] = { + Bits_32(0001,01010100,0,100000), // Reg 0 -- use Secondary Reference for all channels + Bits_32(0001,01010100,0,100000), // Outputs LVCMOS Positive&Negative Active - Non-inverted + Bits_32(0001,01010100,0,100000), + Bits_32(0001,01010100,0,100000), + Bits_32(0001,01010100,0,100000), + Bits_32(0,0,1,10011011), // Reg 5, Failsafe OFF b5.11 = 0 + Bits_32(1,0,10000,0), // Reg 6; try again + Bits_32(1,01000000,0,0), + Bits_32(0,0,1,10000000) // Reg8 Status/Control +}; + +// Table 19 conflicts with Tables 5 thru 9 - in how LVCMOS outputs are defined +// extra error in Table 9, for bits 24 and 25 +static int table_size = sizeof (table_Pri_Ref) / sizeof(uint32_t); + +static void set_bit(uint8_t bit_number, Levels bit_value) { + + if(bit_value == Hi) + PORTA |= 1<<bit_number; + else + PORTA &= ~ (1<<bit_number); +} + +static bool get_bit(uint8_t bit_number) { + asm("nop"); + + uint8_t portA = PINA; + return (portA & 1<< bit_number) > 0 ? true : false; +} + +// Send 32 bits to TI chip, LSB first. +// Don't worry about reading any bits back at this time +static void send_SPI(uint32_t bits) { + + // Basically, when the clock is low, one can set MOSI to anything, as it's + // ignored. + set_bit(CE_, Lo); // Start SPI transaction with TI chip + + // Send each bit, LSB first, add a bit of delay before the clock, and then + // toggle the clock line. + for (uint8_t i=0; i<32; i++) { + set_bit(MOSI, ((bits & (1UL<<i)) ? Hi : Lo) ); + asm("nop"); + set_bit(CLK, Hi); + set_bit(CLK, Lo); + } + + // OK, transaction is over + set_bit(CE_, Hi); +} + +static uint32_t receive_SPI() { + uint32_t bits = 0; + + set_bit(CE_, Hi); // Make sure we're inactive + set_bit(CLK, Lo); // and clk line is inactive, too + set_bit(MOSI,Lo); // Make our bit output zero, for good measure + set_bit(CE_, Lo); // Start SPI transaction with TI chip; MOSI is don't care + + // For each bit we are receiving, prep, clock in the bit LSB first + for (uint8_t i=0; i<32; i++){ + bits >>= 1; + set_bit(CLK, Hi); + if( get_bit(MISO) ) bits |= 0x80000000; + set_bit(CLK, Lo); + } + + // OK, transaction is over + set_bit(CE_, Hi); + + // Ditch the lower 4 bits, which only contain the address + return (uint32_t)(bits >> 4); +} + +void setup_TI_CDCE18005(TI_Input_10_MHz which_input) { + // Send the table of data to init the clock distribution chip. Uses SPI. + uint32_t temp; + + if(which_input == Primary_GPS) { + for(uint8_t i=0; i<table_size; i++){ + temp = table_Pri_Ref[i]<<4; + temp |= i; + send_SPI(temp); // Make sure the register's address is in the LSBs + } + } else { + // is Secondary_Ext -- External 10 MHz input from SMA connector + for(uint8_t i=0; i<table_size; i++){ + temp = table_Sec_Ref[i]<<4; + temp |= i; + // Make sure the register's address is in the LSBs + send_SPI(temp); + } + } +} + +void reset_TI_CDCE18005(void) { + // First, reset the chip. Or, if you will, pull /SYNC low then high + set_bit(CE_, Hi); + set_bit(PD_, Lo); + wait(); + + // Out of Power Down state + set_bit(PD_, Hi); + wait(); + + set_bit(SYNC_, Lo); + wait(); + set_bit(SYNC_, Hi); + + wait(); +} + +uint32_t get_TI_CDCE18005(CDCE18005 which_register){ + uint32_t get_reg_value = 0; + get_reg_value = (0xf0 & (which_register << 4)) | Read_Command; + + // This tells the TI chip to send us the reg. value requested + send_SPI(get_reg_value); + return receive_SPI(); +} + +bool check_TI_CDCE18005(TI_Input_10_MHz which_input, + CDCE18005 which_register) { + + if(which_input == Primary_GPS){ + uint32_t read_value = get_TI_CDCE18005(which_register); + return read_value == table_Pri_Ref[which_register]; + } else { + uint32_t read_value = get_TI_CDCE18005(which_register); + return read_value == table_Sec_Ref[which_register]; + } +} diff --git a/firmware/octoclock/lib/enc28j60.c b/firmware/octoclock/lib/enc28j60.c new file mode 100644 index 000000000..f0bbee0e7 --- /dev/null +++ b/firmware/octoclock/lib/enc28j60.c @@ -0,0 +1,337 @@ +/*! \file enc28j60.c \brief Microchip ENC28J60 Ethernet Interface Driver. */ +//***************************************************************************** +// +// File Name : 'enc28j60.c' +// Title : Microchip ENC28J60 Ethernet Interface Driver +// Author : Pascal Stang (c)2005 +// Created : 9/22/2005 +// Revised : 5/19/2014 +// Version : 0.1 +// Target MCU : Atmel AVR series +// Editor Tabs : 4 +// +// Description : This driver provides initialization and transmit/receive +// functions for the Microchip ENC28J60 10Mb Ethernet Controller and PHY. +// This chip is novel in that it is a full MAC+PHY interface all in a 28-pin +// chip, using an SPI interface to the host processor. +// +//***************************************************************************** + +#include <octoclock.h> + +#include <net/enc28j60.h> +#include <net/enc28j60conf.h> + +#include <avr/io.h> +#include <util/delay.h> + +u08 Enc28j60Bank; +u16 NextPacketPtr; + +u08 enc28j60ReadOp(u08 op, u08 address) +{ + u08 data; + + // assert CS + ENC28J60_CONTROL_PORT &= ~(1<<ENC28J60_CONTROL_CS); + + // issue read command + SPDR = op | (address & ADDR_MASK); + while(!(SPSR & (1<<SPIF))); + // read data + SPDR = 0x00; + while(!(SPSR & (1<<SPIF))); + // do dummy read if needed + if(address & 0x80) + { + SPDR = 0x00; + while(!(inb(SPSR) & (1<<SPIF))); + } + data = SPDR; + + // release CS + ENC28J60_CONTROL_PORT |= (1<<ENC28J60_CONTROL_CS); + + return data; +} + +void enc28j60WriteOp(u08 op, u08 address, u08 data) +{ + // assert CS + ENC28J60_CONTROL_PORT &= ~(1<<ENC28J60_CONTROL_CS); + + // issue write command + SPDR = op | (address & ADDR_MASK); + while(!(SPSR & (1<<SPIF))); + // write data + SPDR = data; + while(!(SPSR & (1<<SPIF))); + + // release CS + ENC28J60_CONTROL_PORT |= (1<<ENC28J60_CONTROL_CS); +} + +void enc28j60ReadBuffer(u16 len, u08* data) +{ + // assert CS + ENC28J60_CONTROL_PORT &= ~(1<<ENC28J60_CONTROL_CS); + + // issue read command + SPDR = ENC28J60_READ_BUF_MEM; + while(!(SPSR & (1<<SPIF))); + while(len--) + { + // read data + SPDR = 0x00; + while(!(SPSR & (1<<SPIF))); + *data++ = SPDR; + } + // release CS + ENC28J60_CONTROL_PORT |= (1<<ENC28J60_CONTROL_CS); +} + +void enc28j60WriteBuffer(u16 len, u08* data) +{ + // assert CS + ENC28J60_CONTROL_PORT &= ~(1<<ENC28J60_CONTROL_CS); + + // issue write command + SPDR = ENC28J60_WRITE_BUF_MEM; + while(!(SPSR & (1<<SPIF))); + while(len--) + { + // write data + SPDR = *data++; + while(!(SPSR & (1<<SPIF))); + } + // release CS + ENC28J60_CONTROL_PORT |= (1<<ENC28J60_CONTROL_CS); +} + +void enc28j60SetBank(u08 address) +{ + // set the bank (if needed) + if((address & BANK_MASK) != Enc28j60Bank) + { + // set the bank + enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, (ECON1_BSEL1|ECON1_BSEL0)); + enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, (address & BANK_MASK)>>5); + Enc28j60Bank = (address & BANK_MASK); + } +} + +u08 enc28j60Read(u08 address) +{ + // set the bank + enc28j60SetBank(address); + // do the read + return enc28j60ReadOp(ENC28J60_READ_CTRL_REG, address); +} + +void enc28j60Write(u08 address, u08 data) +{ + // set the bank + enc28j60SetBank(address); + // do the write + enc28j60WriteOp(ENC28J60_WRITE_CTRL_REG, address, data); +} + +u16 enc28j60PhyRead(u08 address) +{ + u16 data; + + // Set the right address and start the register read operation + enc28j60Write(MIREGADR, address); + enc28j60Write(MICMD, MICMD_MIIRD); + + // wait until the PHY read completes + while(enc28j60Read(MISTAT) & MISTAT_BUSY); + + // quit reading + enc28j60Write(MICMD, 0x00); + + // get data value + data = enc28j60Read(MIRDL); + data |= enc28j60Read(MIRDH); + // return the data + return data; +} + +void enc28j60PhyWrite(u08 address, u16 data) +{ + // set the PHY register address + enc28j60Write(MIREGADR, address); + + // write the PHY data + enc28j60Write(MIWRL, data); + enc28j60Write(MIWRH, data>>8); + + // wait until the PHY write completes + while(enc28j60Read(MISTAT) & MISTAT_BUSY); +} + +void enc28j60Init(u08* macaddr) +{ + // initialize I/O + sbi(ENC28J60_CONTROL_DDR, ENC28J60_CONTROL_CS); + sbi(ENC28J60_CONTROL_PORT, ENC28J60_CONTROL_CS); + + // setup SPI I/O pins + sbi(ENC28J60_SPI_PORT, ENC28J60_SPI_SCK); // set SCK hi + sbi(ENC28J60_SPI_DDR, ENC28J60_SPI_SCK); // set SCK as output + cbi(ENC28J60_SPI_DDR, ENC28J60_SPI_MISO); // set MISO as input + sbi(ENC28J60_SPI_DDR, ENC28J60_SPI_MOSI); // set MOSI as output + sbi(ENC28J60_SPI_DDR, ENC28J60_SPI_SS); // SS must be output for Master mode to work + // initialize SPI interface + // master mode + sbi(SPCR, MSTR); + // select clock phase positive-going in middle of data + cbi(SPCR, CPOL); + // Data order MSB first + cbi(SPCR,DORD); + // switch to f/4 2X = f/2 bitrate + cbi(SPCR, SPR0); + cbi(SPCR, SPR1); + sbi(SPSR, SPI2X); + // enable SPI + sbi(SPCR, SPE); + + // perform system reset + enc28j60WriteOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET); + + /* + * "After sending an SPI Reset command, the PHY + * clock is stopped but the ESTAT.CLKRDY bit is not + * cleared. Therefore, polling the CLKRDY bit will not + * work to detect if the PHY is ready. + * + * Additionally, the hardware start-up time of 300 us + * may expire before the device is ready to operate. + * + * Work around + * After issuing the Reset command, wait at least + * 1 ms in firmware for the device to be ready." + * + * Source: http://ww1.microchip.com/downloads/en/DeviceDoc/80349c.pdf + */ + _delay_ms(1); + + // do bank 0 stuff + // initialize receive buffer + // 16-bit transfers, must write low byte first + // set receive buffer start address + NextPacketPtr = RXSTART_INIT; + enc28j60Write(ERXSTL, RXSTART_INIT&0xFF); + enc28j60Write(ERXSTH, RXSTART_INIT>>8); + // set receive pointer address + enc28j60Write(ERXRDPTL, RXSTART_INIT&0xFF); + enc28j60Write(ERXRDPTH, RXSTART_INIT>>8); + // set receive buffer end + // ERXND defaults to 0x1FFF (end of ram) + enc28j60Write(ERXNDL, RXSTOP_INIT&0xFF); + enc28j60Write(ERXNDH, RXSTOP_INIT>>8); + // set transmit buffer start + // ETXST defaults to 0x0000 (beginnging of ram) + enc28j60Write(ETXSTL, TXSTART_INIT&0xFF); + enc28j60Write(ETXSTH, TXSTART_INIT>>8); + + // do bank 2 stuff + // enable MAC receive + enc28j60Write(MACON1, MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS); + // bring MAC out of reset + enc28j60Write(MACON2, 0x00); + // enable automatic padding and CRC operations + enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN); + // set inter-frame gap (non-back-to-back) + enc28j60Write(MAIPGL, 0x12); + enc28j60Write(MAIPGH, 0x0C); + // set inter-frame gap (back-to-back) + enc28j60Write(MABBIPG, 0x12); + // Set the maximum packet size which the controller will accept + enc28j60Write(MAMXFLL, MAX_FRAMELEN&0xFF); + enc28j60Write(MAMXFLH, MAX_FRAMELEN>>8); + + // do bank 3 stuff + // write MAC address + // NOTE: MAC address in ENC28J60 is byte-backward + enc28j60Write(MAADR5, macaddr[0]); + enc28j60Write(MAADR4, macaddr[1]); + enc28j60Write(MAADR3, macaddr[2]); + enc28j60Write(MAADR2, macaddr[3]); + enc28j60Write(MAADR1, macaddr[4]); + enc28j60Write(MAADR0, macaddr[5]); + + // no loopback of transmitted frames + enc28j60PhyWrite(PHCON2, PHCON2_HDLDIS); + + // switch to bank 0 + enc28j60SetBank(ECON1); + // enable interrutps + enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE); + // enable packet reception + enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN); +} + +void enc28j60PacketSend(unsigned int len1, unsigned char* packet1, unsigned int len2, unsigned char* packet2) +{ + //Errata: Transmit Logic reset + enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRST); + enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRST); + + // Set the write pointer to start of transmit buffer area + enc28j60Write(EWRPTL, TXSTART_INIT&0xff); + enc28j60Write(EWRPTH, TXSTART_INIT>>8); + // Set the TXND pointer to correspond to the packet size given + enc28j60Write(ETXNDL, (TXSTART_INIT+len1+len2)); + enc28j60Write(ETXNDH, (TXSTART_INIT+len1+len2)>>8); + + // write per-packet control byte + enc28j60WriteOp(ENC28J60_WRITE_BUF_MEM, 0, 0x00); + + // copy the packet into the transmit buffer + enc28j60WriteBuffer(len1, packet1); + if(len2>0) enc28j60WriteBuffer(len2, packet2); + + // send the contents of the transmit buffer onto the network + enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS); +} + +unsigned int enc28j60PacketReceive(unsigned int maxlen, u08* buf) +{ + u16 rxstat; + u16 len; + + // check if a packet has been received and buffered + if( !enc28j60Read(EPKTCNT) ) + return 0; + + // Set the read pointer to the start of the received packet + enc28j60Write(ERDPTL, (NextPacketPtr)); + enc28j60Write(ERDPTH, (NextPacketPtr)>>8); + // read the next packet pointer + NextPacketPtr = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0); + NextPacketPtr |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0)<<8; + // read the packet length + len = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0); + len |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0)<<8; + // read the receive status + rxstat = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0); + rxstat |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0)<<8; + + // limit retrieve length + // (we reduce the MAC-reported length by 4 to remove the CRC) + len = MIN(len, maxlen); + + // copy the packet from the receive buffer + enc28j60ReadBuffer(len, buf); + + // Move the RX read pointer to the start of the next received packet + // This frees the memory we just read out + enc28j60Write(ERXRDPTL, (NextPacketPtr)); + enc28j60Write(ERXRDPTH, (NextPacketPtr)>>8); + + // decrement the packet counter indicate we are done with this packet + enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC); + + return len; +} diff --git a/firmware/octoclock/lib/gpsdo.c b/firmware/octoclock/lib/gpsdo.c new file mode 100644 index 000000000..a6a7daaca --- /dev/null +++ b/firmware/octoclock/lib/gpsdo.c @@ -0,0 +1,37 @@ +/* + * Copyright 2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <avr/interrupt.h> + +#include <octoclock.h> +#include <gpsdo.h> +#include <usart.h> + +void send_gpsdo_cmd(char* buf, uint8_t size){ + for(uint8_t i = 0; i < size; i++) usart_putc(buf[i]); +} + +//Serial out +ISR(USART1_RX_vect){ + gpsdo_buf[gpsdo_state.pos] = UDR1; + + if(gpsdo_state.pos == (POOLSIZE-1)){ + gpsdo_state.num_wraps++; + gpsdo_state.pos = 0; + } + else gpsdo_state.pos++; +} diff --git a/firmware/octoclock/lib/init.c b/firmware/octoclock/lib/init.c new file mode 100644 index 000000000..827ccb376 --- /dev/null +++ b/firmware/octoclock/lib/init.c @@ -0,0 +1,175 @@ +/* + * Copyright 2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* + * Welcome to the firmware code for the USRP Octoclock accessory product! + * + * Notes regarding this firmware: + * NOT in M103 compatibility mode + * CKOPT full rail-to-rail + * xtal osc + * 16K CK (16K clock cycles) + * additional delay 65ms for Crystal Oscillator + * slowly rising power + * + * These settings are very conservative. If a lower power oscillator is + * required, change CKOPT to '1' (UNPROGRAMMED). + * + * M103C = [ ] + * WDTON = [ ] + * OCDEN = [ ] + * JTAGEN = [X] + * SPIEN = [X] + * EESAVE = [X] + * BOOTSZ = 4096W_F000 + * BOOTRST = [X] + * CKOPT = [X] + * BODLEVEL = 2V7 + * BODEN = [ ] + * SUT_CKSEL = EXTHIFXTALRES_16KCK_64MS + * + * EXTENDED = 0xFF (valid) + * HIGH = 0x80 (valid) + * LOW = 0xFF (valid) + * + */ + +#include <avr/io.h> + +#include <octoclock.h> + +void setup_atmel_io_ports(){ +/* + * PORT A + * + * pin# Sig Our Functional Name + * + * p51 PA0 CLK_CDCE to U205 pin 24 -- L-->H edge latches MOSI and MISO in CDCE18005 + * p50 PA1 CE_CDCE Low = Chip Enabled for SPI comm to U205 pin 25 + * p49 PA2 MOSI_CDCE Goes to CDCE18005 - U205 pin 23 + * p48 PA3 MISO_CDCE Input Comes from U205 pin 22 + * p47 PA4 PD_CDCE Low = Chip is in Power-Down state; is Hi for normal operation U205 pin 12 + * p46 PA5 SYNC_CDCE Low = Chip is sync'd with interal dividers; Hi for normal operation U205 pin 14 + * p45 PA6 PPS_SEL Low --> PPS_EXT selected; Hi -> PPS_GPS selected; to U203 pin 1 + * p44 PA7 gps_lock Input Comes from M9107 - U206 pin 3 + * + */ + +// /pd_cdcd, /sync_code, /ce need to be 1 (disabled) to start +// all bits are outputs, except PA7 (gps_lock) and PA3 (MISO_CDCE) are inputs +PORTA = Bits_8(00110010); +DDRA = 1<<DDA6 | 1<<DDA5 | 1<<DDA4 | 1<<DDA2 | 1<<DDA1 | 1<<DDA0; + +/* + * Port B + * + * pin# Sig Our Functional Name + * + * p10 PB0 Ethernet /SEN + * p11 PB1 Ethernet SCLK + * p12 PB2 Ethernet MOSI + * p13 PB3 Ethernet MISO + * p14 PB4 Not connected, set as output with value 0 + * p15 PB5 Ethernet /RESET -- Set to HI for normal use, weak input + * p16 PB6 Ethernet /WOL --- Wake on LAN -- set, weak input + * p17 PB7 Not connected, set as output with value 0 + * + */ + +PORTB = Bits_8(01100001); // Initial Value is all zeros +DDRB = 1<<DDB2 | 1<<DDB4 | 1<<DDB7; // MOSI is an output; the Not Connected pins are also outputs + +/* + * Port C + * + * pin# Sig Our Functional Name + * + * p34 PC0 Not connected, set as output with value 0 + * p35 PC1 Reference Select Switch INPUT + * p36 PC2 Not connected, set as output with value 0 + * p37 PC3 Not connected, set as output with value 0 + * p38 PC4 Not connected, set as output with value 0 + * p40 PC5 "Top LED" of D103 3-stack of green LEDs + * p41 PC6 "Middle LED" + * p43 PC7 "Bottom LED" + * + */ + +PORTC = 0; // Initial Value is all zeros +DDRC = ~( 1<<DDC1 ); // All bits are outputs, except PC1. including the 5 Not Connected bits + +/* + * Port D + * + * pin# Sig Our Functional Name + * + * p25 PD0 Ethernet /INT input + * p26 PD1 GPS NMEA bit, (INT1) INPUT + * p27 PD2 GPS Serial Out (RXD) INPUT + * p28 PD3 GPS Serial In (TXD) OUTPUT + * p29 PD4 GPS Present, INPUT hi = Present + * p30 PD5 Not connected, set as output with value 0 + * p31 PD6 Not connected, set as output with value 0 + * p32 PD7 Not connected, set as output with value 0 + * + */ + +PORTD = 0; // Initial Value is all zeros +DDRD = 1<<DDD3; + +/* + * Port E + * + * pin# Sig Dir Our Functional Name + * + * p2 PE0 In avr_rxd (Also MOSI [PDI] when used for SPI programming of the chip) + * p3 PE1 Out avr_txd (Also MISO [PDO] when used for SPI programming of the chip) + * p4 PE2 In avr_cts + * p5 PE3 Out avr_rts + * p6 PE4 In PPS_GPS + * p7 PE5 In PPS_EXT_n + * p8 PE6 In Not Connected + * p9 PE7 In Not Connected + * + */ + +PORTE = 0; +DDRE = 1<<DDE1; // make outputs, set to zero. PE1 is usart0 TXD + +/* + * Port F + * + * Split into 2 nibbles; goes to Amp/Filter board to select ENABLE and two bits + * to select band one bit per nibble is not connected. + * + * pin Sig Dir Our Functional Name + * + * p61 PF0 Out J117 pin 3 (J117 pins 1 and 2 are GND) + * p60 PF1 Out J117 pin 4 + * p59 PF2 Out J117 pin 5 + * p58 PF3 Out J117 pin 6 + * p57 PF4 Out J118 pin 3 (J118 pins 1 and 2 are GND) + * p56 PF5 Out J118 pin 4 + * p55 PF6 Out J118 pin 5 + * p54 PF7 Out J118 pin 6 + * + */ + +PORTF = 0; // Initial Value is all zeros; be sure ENABLE bits are active high!!!! +DDRF = 0xff; // All bits are outputs + +} diff --git a/firmware/octoclock/lib/network.c b/firmware/octoclock/lib/network.c new file mode 100644 index 000000000..bb49de4f6 --- /dev/null +++ b/firmware/octoclock/lib/network.c @@ -0,0 +1,450 @@ +/* + * Copyright 2009-2012,2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <stdint.h> +#include <string.h> + +#include <avr/eeprom.h> +#include <avr/interrupt.h> + +#include <lwip/ip.h> +#include <lwip/udp.h> +#include <lwip/icmp.h> + +#include <debug.h> +#include <octoclock.h> +#include <network.h> + +#include <net/enc28j60.h> +#include <net/eth_hdr.h> +#include <net/if_arp.h> +#include <net/ethertype.h> + +#include "arp_cache.h" + +/*********************************************************************** + * Constants + Globals + **********************************************************************/ +static const size_t out_buff_size = 512; +static const eth_mac_addr_t BCAST_MAC_ADDR = {{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; +#define MAX_UDP_LISTENERS 10 + +/*********************************************************************** + * 16-bit one's complement sum + **********************************************************************/ +static uint32_t chksum_buffer( + uint16_t *buf, size_t nshorts, + uint32_t initial_chksum +){ + uint32_t chksum = initial_chksum; + for (size_t i = 0; i < nshorts; i++) chksum += buf[i]; + + while (chksum >> 16) chksum = (chksum & 0xffff) + (chksum >> 16); + + return chksum; +} + +/*********************************************************************** + * Listener registry + **********************************************************************/ +static eth_mac_addr_t _local_mac_addr; +static struct ip_addr _local_ip_addr; + +struct listener_entry { + unsigned short port; + udp_receiver_t rcvr; +}; + +static struct listener_entry listeners[MAX_UDP_LISTENERS]; + +void init_udp_listeners(void){ + for (int i = 0; i < MAX_UDP_LISTENERS; i++) + listeners[i].rcvr = NULL; +} + +static struct listener_entry * +find_listener_by_port(unsigned short port) +{ + port = ntohs(port); + + for (int i = 0; i < MAX_UDP_LISTENERS; i++){ + if (port == listeners[i].port) + return &listeners[i]; + } + return 0; +} + +static struct listener_entry * +find_free_listener(void) +{ + for (int i = 0; i < MAX_UDP_LISTENERS; i++){ + if (listeners[i].rcvr == NULL) + return &listeners[i]; + } + abort(); +} + +void +register_udp_listener(int port, udp_receiver_t rcvr) +{ + struct listener_entry *lx = find_listener_by_port(port); + if (lx) + lx->rcvr = rcvr; + else { + lx = find_free_listener(); + lx->port = port; + lx->rcvr = rcvr; + } +} + +/*! + * low level routine to assembly an ethernet frame and send it. + * + * \param dst destination mac address + * \param ethertype ethertype field + * \param buf0 first part of data + * \param len0 length of first part of data + * \param buf1 second part of data + * \param len1 length of second part of data + * \param buf2 third part of data + * \param len2 length of third part of data + */ +static void +send_pkt( + eth_mac_addr_t dst, int ethertype, + const void *buf0, size_t len0, + const void *buf1, size_t len1, + const void *buf2, size_t len2 +){ + //assemble the ethernet header + eth_hdr_t ehdr; + ehdr.dst = dst; + ehdr.src = _local_mac_addr; + ehdr.ethertype = ethertype; + + //grab an out buffer and pointer + //select the output buffer based on type of packet + uint8_t *p; + p = buf_out; + size_t total_len = 0; + + //create a list of all buffers to copy + const void *buffs[] = {&ehdr, buf0, buf1, buf2}; + size_t lens[] = {sizeof(ehdr), len0, len1, len2}; + + //copy each buffer into the out buffer + for (size_t i = 0; i < sizeof(buffs)/sizeof(buffs[0]); i++){ + total_len += lens[i]; //use full length (not clipped) + size_t bytes_remaining = out_buff_size - (size_t)(p - (uint8_t*)buf_out); + if (lens[i] > bytes_remaining) lens[i] = bytes_remaining; + memcpy(p, buffs[i], lens[i]); + p += lens[i]; + } + + //ensure that minimum length requirements are met + if (total_len < 64) total_len = 64; //60 + ctrl word + + //For some reason, the ENC28J60 won't send the CRC + //if you don't tell it to send another byte after + //the given packet + enc28j60PacketSend(total_len+1, buf_out, 0, 0); +} + +static void +send_ip_pkt(struct ip_addr dst, int protocol, + const void *buf0, uint16_t len0, + const void *buf1, uint16_t len1) +{ + struct ip_hdr ip; + _IPH_VHLTOS_SET(&ip, 4, 5, 0); + _IPH_LEN_SET(&ip, (IP_HLEN + len0 + len1)); + _IPH_ID_SET(&ip, 0); + _IPH_OFFSET_SET(&ip, htons(IP_DF)); /* don't fragment */ + _IPH_TTL_SET(&ip, 64); + _IPH_PROTO_SET(&ip, protocol); + _IPH_CHKSUM_SET(&ip, 0); + ip.src.addr = htonl(_local_ip_addr.addr); + ip.dest = dst; + + _IPH_CHKSUM_SET(&ip, ~chksum_buffer( + (uint16_t *) &ip, sizeof(ip)/sizeof(int16_t), 0 + )); + + eth_mac_addr_t dst_mac; + bool found = arp_cache_lookup_mac(&ip.dest, &dst_mac); + if (!found) return; + + send_pkt(dst_mac, htons(ETHERTYPE_IPV4), + &ip, sizeof(ip), buf0, len0, buf1, len1); +} + +void +send_udp_pkt(int src_port, struct socket_address dst, + const void *buf, size_t len) +{ + struct udp_hdr udp _AL2; + udp.src = htons(src_port); + udp.dest = htons(dst.port); + udp.len = htons(UDP_HLEN + len); + udp.chksum = 0; + + send_ip_pkt(dst.addr, IP_PROTO_UDP, + &udp, sizeof(udp), buf, len); +} + +static void +handle_udp_packet(struct ip_addr src_ip, struct ip_addr dst_ip, + struct udp_hdr *udp, size_t len) +{ + unsigned char *payload = ((unsigned char *) udp) + UDP_HLEN; + int payload_len = len - UDP_HLEN; + + struct listener_entry *lx = find_listener_by_port(udp->dest); + if (lx){ + struct socket_address src = make_socket_address(src_ip, ntohs(udp->src)); + struct socket_address dst = make_socket_address(dst_ip, ntohs(udp->dest)); + lx->rcvr(src, dst, payload, payload_len); + } +} + +static void +handle_icmp_packet(struct ip_addr src, struct ip_addr dst, + struct icmp_echo_hdr *icmp, size_t len) +{ + switch (icmp->type){ + case ICMP_DUR: // Destination Unreachable + if (icmp->code == ICMP_DUR_PORT){ // port unreachable + //filter out non udp data response + struct ip_hdr *ip = (struct ip_hdr *)(((uint8_t*)icmp) + sizeof(struct icmp_echo_hdr)); + struct udp_hdr *udp = (struct udp_hdr *)(((char *)ip) + IP_HLEN); + uint8_t protocol = ntohs(ip->_ttl_proto) & 0xff; + if (protocol != IP_PROTO_UDP) break; + + struct listener_entry *lx = find_listener_by_port(udp->src); + if (lx){ + struct socket_address src = make_socket_address(ip->src, udp->src); + struct socket_address dst = make_socket_address(ip->dest, udp->dest); + lx->rcvr(src, dst, NULL, 0); + } + } + break; + + case ICMP_ECHO:{ + const void *icmp_data_buff = ((uint8_t*)icmp) + sizeof(struct icmp_echo_hdr); + uint16_t icmp_data_len = len - sizeof(struct icmp_echo_hdr); + + struct icmp_echo_hdr echo_reply; + echo_reply.type = 0; + echo_reply.code = 0; + echo_reply.chksum = 0; + echo_reply.id = icmp->id; + echo_reply.seqno = icmp->seqno; + echo_reply.chksum = ~chksum_buffer( //data checksum + (uint16_t *)icmp_data_buff, + icmp_data_len/sizeof(int16_t), + chksum_buffer( //header checksum + (uint16_t *)&echo_reply, + sizeof(echo_reply)/sizeof(int16_t), + 0) + ); + + send_ip_pkt( + src, IP_PROTO_ICMP, + &echo_reply, sizeof(echo_reply), + icmp_data_buff, icmp_data_len + ); + break; + } + + default: + break; + } +} + +static void +send_arp_reply(struct arp_eth_ipv4 *req, eth_mac_addr_t our_mac) +{ + struct arp_eth_ipv4 reply _AL4; + reply.ar_hrd = req->ar_hrd; + reply.ar_pro = req->ar_pro; + reply.ar_hln = req->ar_hln; + reply.ar_pln = req->ar_pln; + reply.ar_op = htons(ARPOP_REPLY); + memcpy(reply.ar_sha, &our_mac, 6); + memcpy(reply.ar_sip, req->ar_tip, 4); + memcpy(reply.ar_tha, req->ar_sha, 6); + memcpy(reply.ar_tip, req->ar_sip, 4); + + eth_mac_addr_t t; + memcpy(t.addr, reply.ar_tha, 6); + send_pkt(t, htons(ETHERTYPE_ARP), &reply, sizeof(reply), 0, 0, 0, 0); +} + +static void +handle_arp_packet(struct arp_eth_ipv4 *p, size_t size) +{ + if (size < sizeof(struct arp_eth_ipv4)) + return; + + if (ntohs(p->ar_hrd) != ARPHRD_ETHER + || ntohs(p->ar_pro) != ETHERTYPE_IPV4 + || p->ar_hln != 6 + || p->ar_pln != 4) + return; + + if(ntohs(p->ar_op) == ARPOP_REPLY){ + struct ip_addr ip_addr; + memcpy(&ip_addr, p->ar_sip, sizeof(ip_addr)); + eth_mac_addr_t mac_addr; + memcpy(&mac_addr, p->ar_sha, sizeof(mac_addr)); + arp_cache_update(&ip_addr, &mac_addr); + } + + if (ntohs(p->ar_op) != ARPOP_REQUEST) + return; + + struct ip_addr sip; + struct ip_addr tip; + + memcpy(&(sip.addr), &(p->ar_sip), 4); + memcpy(&(tip.addr), &(p->ar_tip), 4); + sip.addr = ntohl(sip.addr); + tip.addr = ntohl(tip.addr); + + if(memcmp(&tip, &_local_ip_addr, sizeof(_local_ip_addr)) == 0){ //They're looking for us + send_arp_reply(p, _local_mac_addr); + } +} + +void +handle_eth_packet(size_t recv_len) +{ + eth_hdr_t *eth_hdr = (eth_hdr_t *)buf_in; + uint16_t ethertype = htons(eth_hdr->ethertype); + + if (ethertype == ETHERTYPE_ARP){ + struct arp_eth_ipv4 *arp = (struct arp_eth_ipv4 *)(buf_in + sizeof(eth_hdr_t)); + handle_arp_packet(arp, recv_len-ETH_HLEN); + } + else if (ethertype == ETHERTYPE_IPV4){ + struct ip_hdr *ip = (struct ip_hdr *)(buf_in + sizeof(eth_hdr_t)); + + if (_IPH_V(ip) != 4 || _IPH_HL(ip) != 5) // ignore pkts w/ bad version or options + return; + + if (_IPH_OFFSET(ip) & (IP_MF | IP_OFFMASK)) // ignore fragmented packets + return; + + // filter on dest ip addr (should be broadcast or for us) + bool is_bcast = memcmp(ð_hdr->dst, &BCAST_MAC_ADDR, sizeof(BCAST_MAC_ADDR)) == 0; + struct ip_addr htonl_local_ip_addr; + htonl_local_ip_addr.addr = htonl(_local_ip_addr.addr); + + bool is_my_ip = memcmp(&ip->dest, &htonl_local_ip_addr, sizeof(_local_ip_addr)) == 0; + if (!is_bcast && !is_my_ip) return; + + arp_cache_update(&ip->src, (eth_mac_addr_t *)(((char *)buf_in)+6)); + + switch (_IPH_PROTO(ip)){ + case IP_PROTO_UDP: + handle_udp_packet(ip->src, ip->dest, (struct udp_hdr *)(((char *)ip) + IP_HLEN), (recv_len-ETH_HLEN-IP_HLEN)); + break; + + case IP_PROTO_ICMP: + handle_icmp_packet(ip->src, ip->dest, (struct icmp_echo_hdr *)(((char *)ip) + IP_HLEN), (recv_len-ETH_HLEN-IP_HLEN)); + break; + + default: // ignore + break; + } + } + else + return; // Not ARP or IPV4, ignore +} + +/*********************************************************************** + * Timer+GARP stuff + **********************************************************************/ + +static bool send_garp = false; +static bool sent_initial_garp = false; +static uint32_t num_overflows = 0; + +// Six overflows is the closest overflow count to one minute. +ISR(TIMER1_OVF_vect){ + num_overflows++; + if(!(num_overflows % 6)) send_garp = true; +} + +static void +send_gratuitous_arp(){ + send_garp = false; + + //Need to htonl IP address + struct ip_addr htonl_ip_addr; + htonl_ip_addr.addr = htonl(_local_ip_addr.addr); + + struct arp_eth_ipv4 req _AL4; + req.ar_hrd = htons(ARPHRD_ETHER); + req.ar_pro = htons(ETHERTYPE_IPV4); + req.ar_hln = sizeof(eth_mac_addr_t); + req.ar_pln = sizeof(struct ip_addr); + req.ar_op = htons(ARPOP_REQUEST); + memcpy(req.ar_sha, &_local_mac_addr, sizeof(eth_mac_addr_t)); + memcpy(req.ar_sip, &htonl_ip_addr, sizeof(struct ip_addr)); + memset(req.ar_tha, 0x00, sizeof(eth_mac_addr_t)); + memcpy(req.ar_tip, &htonl_ip_addr, sizeof(struct ip_addr)); + + //Send the request with the broadcast MAC address + send_pkt(BCAST_MAC_ADDR, htons(ETHERTYPE_ARP), &req, sizeof(req), 0, 0, 0, 0); +} + +// Executed every loop +void network_check(void){ + size_t recv_len = enc28j60PacketReceive(512, buf_in); + if(recv_len > 0) handle_eth_packet(recv_len); + + /* + * Send a gratuitous ARP packet two seconds after Ethernet + * initialization. + */ + if(!sent_initial_garp && (num_overflows == 0 && TCNT1 > (TIMER1_ONE_SECOND*2))){ + sent_initial_garp = true; + send_garp = true; + } + + if(send_garp) send_gratuitous_arp(); +} + +void network_init(void){ + /* + * Read MAC address from EEPROM and initialize Ethernet driver. If EEPROM is blank, + * use default MAC address instead. + */ + if(eeprom_read_byte(0) == 0xFF){ + _MAC_ADDR(_local_mac_addr.addr, 0x00,0x80,0x2F,0x11,0x22,0x33); + _local_ip_addr.addr = default_ip; + using_network_defaults = true; + } + else{ + eeprom_read_block((void*)&_local_mac_addr, (void*)OCTOCLOCK_EEPROM_MAC_ADDR, 6); + eeprom_read_block((void*)&_local_ip_addr, (void*)OCTOCLOCK_EEPROM_IP_ADDR, 4); + using_network_defaults = false; + } + + enc28j60Init((uint8_t*)&_local_mac_addr); +} diff --git a/firmware/octoclock/lib/serial.c b/firmware/octoclock/lib/serial.c new file mode 100644 index 000000000..298cdff8d --- /dev/null +++ b/firmware/octoclock/lib/serial.c @@ -0,0 +1,156 @@ +/* + * Copyright 2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <stdbool.h> + +#include <octoclock.h> +#include <serial.h> + +#include <avr/pgmspace.h> +#include <util/delay.h> +#include <avr/io.h> +#include <avr/interrupt.h> + +void serial_init(volatile uint8_t* port, uint8_t index){ + *port |= _BV(index); +} + +static void _serial_tx_send(uint8_t* buffer, volatile uint8_t* port, uint8_t index){ + const uint8_t delay = BAUD_115200_DELAY; + uint8_t countdown; + + for(uint8_t i = 0; i < 10; ++i){ + if(buffer[i]) *port |= _BV(index); + else *port &= ~_BV(index); + + countdown = delay; + while(--countdown) asm("nop"); + } +} + +static void _serial_tx_char(char c, volatile uint8_t* port, uint8_t index){ + uint8_t buffer[10]; + uint8_t i = 0; + + buffer[i++] = 0; // START + for (int idx = 0; idx < 8; ++idx) + buffer[i++] = (((uint8_t)(c) & ((uint8_t)1<<((idx)))) ? 0x01 : 0x00); // Endianness: 7- + buffer[i++] = 1; // STOP + + _serial_tx_send(buffer, port, index); +} + +void serial_tx_P(const char* message, volatile uint8_t* port, uint8_t index, bool newline){ + char c = pgm_read_byte(message); + if(c == '\0') return; + + do{ + _serial_tx_char(c, port, index); + c = pgm_read_byte(++message); + } while(c != '\0'); + + if(newline){ + _serial_tx_char('\r', port, index); + _serial_tx_char('\n', port, index); + } + + *port |= _BV(index); +} + +void serial_tx(const char* message, volatile uint8_t* port, uint8_t index, bool newline){ + if (message[0] == '\0') + return; + + do + { + _serial_tx_char(*message, port, index); + } while (*(++message) != '\0'); + + if (newline){ + _serial_tx_char('\r', port, index); + _serial_tx_char('\n', port, index); + } + + *port |= _BV(index); +} + +void serial_tx_byte(uint8_t byte, volatile uint8_t* port, uint8_t index, bool newline){ + char ch[4]; + ch[0] = '0' + (byte / 100); + ch[1] = '0' + ((byte % 100) / 10); + ch[2] = '0' + (byte % 10); + ch[3] = '\0'; + serial_tx(ch, port, index, newline); +} + +void serial_tx_hex(uint8_t byte, volatile uint8_t* port, uint8_t index, bool newline){ + char ch[3]; + uint8_t _byte = byte >> 4; + if (_byte < 10) + ch[0] = '0' + _byte; + else + ch[0] = 'A' + (_byte - 10); + byte &= 0x0F; + if (byte < 10) + ch[1] = '0' + byte; + else + ch[1] = 'A' + (byte - 10); + ch[2] = '\0'; + serial_tx(ch, port, index, newline); +} + +char serial_rx_char(volatile uint8_t* port, uint8_t index){ + char c = 0; + const uint8_t delay = BAUD_115200_DELAY; + uint8_t countdown; + + //Wait for character to appear, 0 will act as start marker + while(*port & _BV(index)); + + //With start marker there, wait for next bit + countdown = delay; + while(--countdown) asm("nop"); + + for(uint8_t i = 0; i < 8; ++i){ + if(*port & _BV(index)) c &= (uint8_t)(1 << i); + + countdown = delay; + while(--countdown) asm("nop"); + } + + return c; +} + +//Assume ready (probably risky) +char serial_rx_char_nowait(volatile uint8_t* port, uint8_t index){ + char c = 0; + const uint8_t delay = BAUD_115200_DELAY; + uint8_t countdown; + + //Wait for start marker to pass + countdown = delay; + while(--countdown) asm("nop"); + + for(uint8_t i = 0; i < 8; ++i){ + if(*port & _BV(index)) c &= (uint8_t)(1 << i); + + countdown = delay; + while(--countdown) asm("nop"); + } + + return c; +} diff --git a/firmware/octoclock/lib/state.c b/firmware/octoclock/lib/state.c new file mode 100644 index 000000000..0dbcc6ece --- /dev/null +++ b/firmware/octoclock/lib/state.c @@ -0,0 +1,124 @@ +/* + * Copyright 2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <avr/interrupt.h> +#include <avr/io.h> + +#include <debug.h> +#include <octoclock.h> +#include <clkdist.h> +#include <state.h> + +void led(LEDs which, int turn_it_on) { + + // selects the proper bit + uint8_t LED = 0x20 << which; + + if(turn_it_on) + PORTC |= LED; + else + PORTC &= ~LED; +} + +void LEDs_Off(void){ + led(Top,false); + led(Middle,false); + led(Bottom,false); +} + +void force_internal(void){ + led(Top,true); + led(Middle,false); + led(Bottom,true); + + setup_TI_CDCE18005(Primary_GPS); + + // Set PPS to Primary (1) n.b.: "1" in general means "Internal" for all + // such signals + PORTA |= (1<<PA6); +} + +void force_external(void){ + led(Top, false); + led(Middle, true); + led(Bottom, true); + + setup_TI_CDCE18005(Secondary_Ext); + + // Set PPS to External + PORTA &= ~(1<<PA6); +} + +void prefer_internal(void){ + // if internal is NOT OK, then force external + if(global_gps_present) + force_internal(); + else if(global_ext_ref_is_present) + force_external(); + else + LEDs_Off(); +} + +void prefer_external(void){ + // if external is NOT OK, then force internal + if(global_ext_ref_is_present) + force_external(); + else if(global_gps_present) + force_internal(); + else + LEDs_Off(); +} + +static uint8_t prev_PE7 = 0; +static uint32_t timer0_num_overflows = 0; + +ISR(TIMER0_OVF_vect){ + global_gps_present = (PIND & (1<<DDD4)); + + // Every ~1/10 second + if(!(timer0_num_overflows % 610)){ + prev_PE7 = (PINE & (1<<DDE7)); + + if(get_switch_pos() == UP) prefer_internal(); + else prefer_external(); + + global_ext_ref_is_present = false; + } + + if(!global_ext_ref_is_present){ + global_ext_ref_is_present = (prev_PE7 != (PINE & (1<<DDE7))); + } + + timer0_num_overflows++; +} + +ref_t which_ref(void){ + if(!global_gps_present && !global_ext_ref_is_present) global_which_ref = NO_REF; + else if(global_gps_present && !global_ext_ref_is_present) global_which_ref = INTERNAL; + else if(!global_gps_present && global_ext_ref_is_present) global_which_ref = EXTERNAL; + else global_which_ref = (get_switch_pos() == UP) ? INTERNAL : EXTERNAL; + + return global_which_ref; +} + +switch_pos_t get_switch_pos(void){ + uint8_t portC = PINC; + + // UP is prefer internal, + // DOWN is prefer external + return (portC & (1<<DDC1)) ? DOWN : UP; +} diff --git a/firmware/octoclock/lib/udp_handlers.c b/firmware/octoclock/lib/udp_handlers.c new file mode 100644 index 000000000..1f20112c9 --- /dev/null +++ b/firmware/octoclock/lib/udp_handlers.c @@ -0,0 +1,165 @@ +/* + * Copyright 2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <string.h> + +#include <avr/eeprom.h> +#include <avr/io.h> +#include <avr/wdt.h> + +#include <octoclock.h> +#include <gpsdo.h> +#include <network.h> +#include <state.h> +#include <net/udp_handlers.h> + +void handle_udp_ctrl_packet( + struct socket_address src, struct socket_address dst, + unsigned char *payload, int payload_len +){ + const octoclock_packet_t *pkt_in = (octoclock_packet_t*)payload; + octoclock_packet_t pkt_out; + pkt_out.proto_ver = OCTOCLOCK_FW_COMPAT_NUM; + pkt_out.sequence = pkt_in->sequence; + + //If the firmware is incompatible, only respond to queries + if(pkt_in->code == OCTOCLOCK_QUERY_CMD){ + pkt_out.code = OCTOCLOCK_QUERY_ACK; + pkt_out.len = 0; + send_udp_pkt(OCTOCLOCK_UDP_CTRL_PORT, src, (void*)&pkt_out, sizeof(octoclock_packet_t)); + } + else if(pkt_in->proto_ver == OCTOCLOCK_FW_COMPAT_NUM){ + switch(pkt_in->code){ + case SEND_EEPROM_CMD: + pkt_out.code = SEND_EEPROM_ACK; + pkt_out.len = sizeof(octoclock_fw_eeprom_t); + + octoclock_fw_eeprom_t *eeprom_info = (octoclock_fw_eeprom_t*)pkt_out.data; + + //Read values from EEPROM into packet + eeprom_read_block(eeprom_info, 0, sizeof(octoclock_fw_eeprom_t)); + + //If EEPROM network fields are not fully populated, copy defaults + if(using_network_defaults){ + _MAC_ADDR(eeprom_info->mac_addr, 0x00,0x80,0x2F,0x11,0x22,0x33); + eeprom_info->ip_addr = default_ip; + eeprom_info->dr_addr = default_dr; + eeprom_info->netmask = default_netmask; + } + + //Check if strings or revision is empty + if(eeprom_info->serial[0] == 0xFF) memset(eeprom_info->serial, 0, 10); + if(eeprom_info->name[0] == 0xFF) memset(eeprom_info->name, 0, 10); + if(eeprom_info->revision == 0xFF) eeprom_info->revision = 0; + break; + + case BURN_EEPROM_CMD:{ + //Confirm length of data + if(pkt_in->len != sizeof(octoclock_fw_eeprom_t)){ + pkt_out.code = BURN_EEPROM_FAILURE_ACK; + break; + } + + /* + * In all cases, a full octoclock_fw_eeprom_t is written to lower the overall + * number of writes due to this EEPROM's smaller amount of safe writes. + * It is up to the host to make sure that the values that should be + * preserved are present in the octoclock_fw_eeprom_t struct. + */ + const octoclock_fw_eeprom_t *eeprom_pkt = (octoclock_fw_eeprom_t*)pkt_in->data; + pkt_out.len = 0; + + //Write EEPROM data from packet + eeprom_write_block(eeprom_pkt, 0, sizeof(octoclock_fw_eeprom_t)); + + //Read back and compare to packet to confirm successful write + uint8_t eeprom_contents[sizeof(octoclock_fw_eeprom_t)]; + eeprom_read_block(eeprom_contents, 0, sizeof(octoclock_fw_eeprom_t)); + uint8_t n = memcmp(eeprom_contents, eeprom_pkt, sizeof(octoclock_fw_eeprom_t)); + pkt_out.code = n ? BURN_EEPROM_FAILURE_ACK + : BURN_EEPROM_SUCCESS_ACK; + break; + } + + case SEND_STATE_CMD: + pkt_out.code = SEND_STATE_ACK; + pkt_out.len = sizeof(octoclock_state_t); + + //Populate octoclock_state_t fields + octoclock_state_t *state = (octoclock_state_t*)pkt_out.data; + state->external_detected = global_ext_ref_is_present ? 1 : 0; + state->gps_detected = (PIND & _BV(DDD4)) ? 1 : 0; + state->which_ref = (uint8_t)which_ref(); + state->switch_pos = (uint8_t)get_switch_pos(); + break; + + case RESET_CMD: + pkt_out.code = RESET_ACK; + send_udp_pkt(OCTOCLOCK_UDP_CTRL_PORT, src, (void*)&pkt_out, sizeof(octoclock_packet_t)); + wdt_enable(WDTO_30MS); + while(1); + return; + + default: + return; + } + + send_udp_pkt(OCTOCLOCK_UDP_CTRL_PORT, src, (void*)&pkt_out, sizeof(octoclock_packet_t)); + } +} + +void handle_udp_gpsdo_packet( + struct socket_address src, struct socket_address dst, + unsigned char *payload, int payload_len +){ + const octoclock_packet_t *pkt_in = (octoclock_packet_t*)payload; + octoclock_packet_t pkt_out; + pkt_out.proto_ver = OCTOCLOCK_FW_COMPAT_NUM; + pkt_out.sequence = pkt_in->sequence; + + if(pkt_in->proto_ver == OCTOCLOCK_FW_COMPAT_NUM){ + switch(pkt_in->code){ + case HOST_SEND_TO_GPSDO_CMD: + send_gpsdo_cmd((char*)pkt_in->data, pkt_in->len); + pkt_out.code = HOST_SEND_TO_GPSDO_ACK; + pkt_out.len = 0; + break; + + case SEND_POOLSIZE_CMD: + pkt_out.code = SEND_POOLSIZE_ACK; + pkt_out.len = 0; + pkt_out.poolsize = POOLSIZE; + break; + + case SEND_CACHE_STATE_CMD: + pkt_out.code = SEND_CACHE_STATE_ACK; + pkt_out.state = gpsdo_state; + break; + + case SEND_GPSDO_CACHE_CMD: + pkt_out.code = SEND_GPSDO_CACHE_ACK; + pkt_out.state = gpsdo_state; + memcpy(pkt_out.data, gpsdo_buf, POOLSIZE); + break; + + default: + return; + } + + send_udp_pkt(OCTOCLOCK_UDP_GPSDO_PORT, src, (void*)&pkt_out, sizeof(octoclock_packet_t)); + } +} diff --git a/firmware/octoclock/lib/usart.c b/firmware/octoclock/lib/usart.c new file mode 100644 index 000000000..3620ac5e9 --- /dev/null +++ b/firmware/octoclock/lib/usart.c @@ -0,0 +1,49 @@ +/* + * Copyright 2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <octoclock.h> +#include <usart.h> + +#include <util/delay.h> +#include <avr/io.h> + +void usart_init(void){ + UCSR1B = (1 << TXEN) | (1 << RXEN) | (1 << RXCIE); //Turn on TX/RX circuitry, enable RX interrupts + UCSR1C = (3 << UCSZ0); //Use 8-bit character sizes, 1 stop bit, no parity + UBRR1H = (uint8_t)(BAUD_PRESCALE >> 8); + UBRR1L = (uint8_t)BAUD_PRESCALE; +} + +char usart_getc(void){ + while((UCSR1A & (1 << RXC)) == 0); + + return UDR1; +} + +char usart_getc_noblock(void){ + return ((UCSR1A & (1 << RXC))) ? UDR1 : -1; +} + +void usart_putc(char ch){ + while((UCSR1A & (1 << UDRE1)) == 0); + + UDR1 = ch; +} + +void usart_putc_nowait(char ch){ + if((UCSR1A & (1 << UDRE1)) != 0) UDR1 = ch; +} diff --git a/firmware/octoclock/octoclock_r4/CMakeLists.txt b/firmware/octoclock/octoclock_r4/CMakeLists.txt new file mode 100644 index 000000000..c3559d8d4 --- /dev/null +++ b/firmware/octoclock/octoclock_r4/CMakeLists.txt @@ -0,0 +1,50 @@ +# +# Copyright 2014 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +add_executable(octoclock_r4_fw.elf octoclock_r4_main.c) +target_link_libraries(octoclock_r4_fw.elf octoclock) +set_target_properties(octoclock_r4_fw.elf PROPERTIES + LINK_FLAGS "-Wl,--relax,-Map=octoclock_r4_fw.map,--cref" +) + +add_custom_command( + OUTPUT ${CMAKE_BINARY_DIR}/octoclock_r4_fw.bin + DEPENDS octoclock_r4_fw.elf + COMMENT "Generating octoclock_r4_fw.bin" + COMMAND ${AVR_OBJCOPY} -O binary ${CMAKE_CURRENT_BINARY_DIR}/octoclock_r4_fw.elf ${CMAKE_BINARY_DIR}/octoclock_r4_fw.bin +) +add_custom_target( + octoclock_r4_fw_bin ALL + DEPENDS ${CMAKE_BINARY_DIR}/octoclock_r4_fw.bin +) +add_custom_command( + OUTPUT ${CMAKE_BINARY_DIR}/octoclock_r4_fw.hex + DEPENDS octoclock_r4_fw.elf + COMMENT "Generating octoclock_r4_fw.hex" + COMMAND ${AVR_OBJCOPY} -O ihex ${CMAKE_CURRENT_BINARY_DIR}/octoclock_r4_fw.elf ${CMAKE_BINARY_DIR}/octoclock_r4_fw.hex +) +add_custom_target( + octoclock_r4_fw_hex ALL + DEPENDS ${CMAKE_BINARY_DIR}/octoclock_r4_fw.hex +) +add_custom_target( + upload_r4 + ${AVRDUDE} -p atmega128 -c ${PROGRAMMER} -P usb -U efuse:w:0xFF:m -U hfuse:w:0x81:m -U lfuse:w:0xFF:m -U flash:w:octoclock_r4_fw.hex:i + WORKING_DIRECTORY ${CMAKE_BINARY_DIR} + DEPENDS octoclock_r4_fw_hex + COMMENT "Uploading OctoClock firmware to device with ${PROGRAMMER}" +) diff --git a/firmware/octoclock/octoclock_r4/octoclock_r4_main.c b/firmware/octoclock/octoclock_r4/octoclock_r4_main.c new file mode 100644 index 000000000..5e8e6d09b --- /dev/null +++ b/firmware/octoclock/octoclock_r4/octoclock_r4_main.c @@ -0,0 +1,105 @@ +/* + * Copyright 2013-2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* + * Welcome to the firmware code for the USRP Octoclock accessory product! + * + * Notes regarding this firmware: + * NOT in M103 compatibility mode + * CKOPT full rail-to-rail + * xtal osc + * 16K CK (16K clock cycles) + * additional delay 65ms for Crystal Oscillator + * slowly rising power + * persistent EEPROM + * + * These settings are very conservative. If a lower power oscillator is + * required, change CKOPT to '1' (UNPROGRAMMED). + * + * M103C = [ ] + * WDTON = [ ] + * OCDEN = [ ] + * JTAGEN = [X] + * SPIEN = [X] + * EESAVE = [X] + * BOOTSZ = 4096W_F000 + * BOOTRST = [ ] + * CKOPT = [X] + * BODLEVEL = 2V7 + * BODEN = [ ] + * SUT_CKSEL = EXTHIFXTALRES_16KCK_64MS + * + * EXTENDED = 0xFF (valid) + * HIGH = 0x81 (valid) + * LOW = 0xFF (valid) + * + */ + +#include <string.h> +#include <stdint.h> +#include <stdbool.h> + +#include <avr/eeprom.h> +#include <avr/io.h> + +#include <octoclock.h> +#include <clkdist.h> +#include <debug.h> +#include <state.h> +#include <network.h> +#include <usart.h> +#include <gpsdo.h> +#include <net/enc28j60.h> +#include <net/udp_handlers.h> + +/******************************************************************************* +* Main Routine +*******************************************************************************/ + +int main(void){ + + asm("cli"); + + setup_atmel_io_ports(); + network_init(); + + #ifndef DEBUG + asm("sei"); + #endif + + init_udp_listeners(); + register_udp_listener(OCTOCLOCK_UDP_CTRL_PORT, handle_udp_ctrl_packet); + register_udp_listener(OCTOCLOCK_UDP_GPSDO_PORT, handle_udp_gpsdo_packet); + + DEBUG_INIT(); // Does nothing when not in debug mode + DEBUG_LOG(" "); //Force a newline between runs + usart_init(); + + //Set initial ClkDist and front panel settings + led(Middle,true); + setup_TI_CDCE18005(Primary_GPS); // 10 MHz from Internal Source + + led(Top,true); + PORTA |= (1<<PA6); // PPS from Internal source + + TIMER0_INIT(); + TIMER1_INIT(); + + while(true) { + network_check(); + } +} diff --git a/fpga/usrp3/top/b200/b200.v b/fpga/usrp3/top/b200/b200.v index b25c02bdf..585d5030e 100644 --- a/fpga/usrp3/top/b200/b200.v +++ b/fpga/usrp3/top/b200/b200.v @@ -179,16 +179,27 @@ module b200 ( /////////////////////////////////////////////////////////////////////// // SPI connections /////////////////////////////////////////////////////////////////////// - wire mosi, miso, sclk; wire [7:0] sen; - assign cat_ce = sen[0] & fx3_ce; - assign cat_mosi = (~sen[0] & mosi) | (~fx3_ce & fx3_mosi); - assign cat_sclk = (~sen[0] & sclk) | (~fx3_ce & fx3_sclk); - assign miso = cat_miso; - assign fx3_miso = ~fx3_ce & cat_miso; - assign pll_ce = sen[1]; + wire mosi, miso, sclk; + wire [7:0] sen; + + //AD9361 Slave + assign cat_ce = sen[0]; + assign cat_mosi = ~sen[0] & mosi; + assign cat_sclk = ~sen[0] & sclk; + assign miso = cat_miso; //PLL does not have a miso + + //ADF4001 Slave + assign pll_ce = sen[1]; assign pll_mosi = ~sen[1] & mosi; assign pll_sclk = ~sen[1] & sclk; + //FX3 Master + //The following signals are routed to the FX3 and were used by an obsolete + //bit-banging SPI engine. + // fx3_ce, fx3_sclk, fx3_mosi <Unused> + assign fx3_miso = 1'bZ; //Safe state because we cannot guarantee the + //direction of this pin in the FX3 + /////////////////////////////////////////////////////////////////////// // bus signals /////////////////////////////////////////////////////////////////////// diff --git a/fpga/usrp3/top/b200/b200_core.v b/fpga/usrp3/top/b200/b200_core.v index dc8baba4f..ec8d0ff5a 100644 --- a/fpga/usrp3/top/b200/b200_core.v +++ b/fpga/usrp3/top/b200/b200_core.v @@ -72,7 +72,7 @@ module b200_core localparam SR_CORE_READBACK = 8'd32; localparam SR_CORE_GPSDO_ST = 8'd40; localparam SR_CORE_PPS_SEL = 8'd48; - localparam COMPAT_MAJOR = 16'h0003; + localparam COMPAT_MAJOR = 16'h0004; localparam COMPAT_MINOR = 16'h0000; /******************************************************************* diff --git a/host/CMakeLists.txt b/host/CMakeLists.txt index 9cae1f057..9baebdb11 100644 --- a/host/CMakeLists.txt +++ b/host/CMakeLists.txt @@ -209,9 +209,8 @@ UHD_INSTALL(FILES ######################################################################## # Images download directory for utils/uhd_images_downloader.py ######################################################################## - -SET(UHD_IMAGES_MD5SUM "1e92df755dd71575ac238cd8bea3ea21") -SET(UHD_IMAGES_DOWNLOAD_SRC "http://files.ettus.com/binaries/maint_images/archive/uhd-images_003.007.002-release.zip") +SET(UHD_IMAGES_MD5SUM "9cfe5b877dc87c993553a475d32701c8") +SET(UHD_IMAGES_DOWNLOAD_SRC "http://files.ettus.com/binaries/master_images/archive/uhd-images_003.007.002-440-gb290682b.zip") ######################################################################## # Register top level components @@ -226,16 +225,16 @@ LIBUHD_REGISTER_COMPONENT("Tests" ENABLE_TESTS ON "ENABLE_LIBUHD" OFF) ######################################################################## ADD_SUBDIRECTORY(docs) +IF(ENABLE_LIBUHD) + ADD_SUBDIRECTORY(lib) +ENDIF(ENABLE_LIBUHD) + ADD_SUBDIRECTORY(include) IF(ENABLE_EXAMPLES) ADD_SUBDIRECTORY(examples) ENDIF(ENABLE_EXAMPLES) -IF(ENABLE_LIBUHD) - ADD_SUBDIRECTORY(lib) -ENDIF(ENABLE_LIBUHD) - IF(ENABLE_TESTS) ADD_SUBDIRECTORY(tests) ENDIF(ENABLE_TESTS) diff --git a/host/cmake/Modules/NSIS.template.in b/host/cmake/Modules/NSIS.template.in index 2caafa964..6e3c4af20 100644 --- a/host/cmake/Modules/NSIS.template.in +++ b/host/cmake/Modules/NSIS.template.in @@ -696,8 +696,7 @@ Section "-Core installation" CreateShortCut "$SMPROGRAMS\$STARTMENU_FOLDER\USRP2 Card Burner.lnk" "$INSTDIR\lib\uhd\utils\usrp2_card_burner_gui.py" "" "" "" SW_SHOWMINIMIZED CreateShortcut "$SMPROGRAMS\$STARTMENU_FOLDER\USRP-N2XX Net Burner.lnk" "$INSTDIR\lib\uhd\utils\usrp_n2xx_net_burner_gui.py" "" "" "" SW_SHOWMINIMIZED CreateShortcut "$SMPROGRAMS\$STARTMENU_FOLDER\UHD Images Downloader.lnk" "$INSTDIR\lib\uhd\utils\uhd_images_downloader.py" - CreateShortcut "$SMPROGRAMS\$STARTMENU_FOLDER\Application Manual.lnk" "$INSTDIR\share\doc\uhd\manual\html\index.html" - CreateShortcut "$SMPROGRAMS\$STARTMENU_FOLDER\API Documentation.lnk" "$INSTDIR\share\doc\uhd\doxygen\html\classes.html" + CreateShortcut "$SMPROGRAMS\$STARTMENU_FOLDER\UHD Documentation.lnk" "$INSTDIR\share\doc\uhd\doxygen\html\index.html" ;Read a value from an InstallOptions INI file !insertmacro MUI_INSTALLOPTIONS_READ $DO_NOT_ADD_TO_PATH "NSIS.InstallOptions.ini" "Field 2" "State" @@ -874,8 +873,7 @@ Section "Uninstall" Delete "$SMPROGRAMS\$MUI_TEMP\USRP2 Card Burner.lnk" Delete "$SMPROGRAMS\$MUI_TEMP\USRP-N2XX Net Burner.lnk" Delete "$SMPROGRAMS\$MUI_TEMP\UHD Images Downloader.lnk" - Delete "$SMPROGRAMS\$MUI_TEMP\Application Manual.lnk" - Delete "$SMPROGRAMS\$MUI_TEMP\API Documentation.lnk" + Delete "$SMPROGRAMS\$MUI_TEMP\UHD Documentation.lnk" @CPACK_NSIS_DELETE_ICONS_EXTRA@ ;Delete empty start menu parent diretories diff --git a/host/docs/CMakeLists.txt b/host/docs/CMakeLists.txt index 1ee0f1ade..84ed88281 100644 --- a/host/docs/CMakeLists.txt +++ b/host/docs/CMakeLists.txt @@ -18,96 +18,57 @@ ######################################################################## # List of manual sources ######################################################################## -SET(manual_sources - index.rst - identification.rst - build.rst - calibration.rst - coding.rst - dboards.rst - gpio_api.rst - gpsdo.rst - gpsdo_b2x0.rst - gpsdo_x3x0.rst - general.rst - images.rst - stream.rst - sync.rst - transport.rst - usrp1.rst - usrp2.rst - usrp_b100.rst - usrp_b200.rst - usrp_e1x0.rst - usrp_x3x0.rst - usrp_x3x0_config.rst -) ######################################################################## -# Setup Manual +# Setup general Doxygen variables ######################################################################## -MESSAGE(STATUS "") -FIND_PACKAGE(Docutils) - -LIBUHD_REGISTER_COMPONENT("Manual" ENABLE_MANUAL ON "DOCUTILS_FOUND" OFF) +FIND_PACKAGE(Doxygen) +SET(ENABLE_MANUAL_OR_DOXYGEN false) -IF(UHDHOST_PKG) - SET(PKG_DOC_DIR share/doc/uhd-host) -ENDIF(UHDHOST_PKG) +######################################################################## +# Setup Manual (using Doxygen) +######################################################################## +MESSAGE(STATUS "") +LIBUHD_REGISTER_COMPONENT("Manual" ENABLE_MANUAL ON "DOXYGEN_FOUND" OFF) IF(ENABLE_MANUAL) - #setup rst2html options - SET(stylesheet ${CMAKE_CURRENT_SOURCE_DIR}/style.css) - SET(rst2html_options - --stylesheet=${stylesheet} - --no-toc-backlinks --date --time - ) - - #create generation rule for each source - FOREACH(rstfile ${manual_sources}) - #set input and output file names - SET(rstfile ${CMAKE_CURRENT_SOURCE_DIR}/${rstfile}) - GET_FILENAME_COMPONENT(rstfile_we ${rstfile} NAME_WE) - SET(htmlfile ${CMAKE_CURRENT_BINARY_DIR}/${rstfile_we}.html) - - #make the html file depend on the rst file - ADD_CUSTOM_COMMAND( - OUTPUT ${htmlfile} DEPENDS ${rstfile} ${stylesheet} - COMMAND ${RST2HTML_EXECUTABLE} ${rstfile} ${htmlfile} ${rst2html_options} - COMMENT "Generating ${htmlfile}" - ) - - #make the manual target depend on the html file - LIST(APPEND manual_html_files ${htmlfile}) - UHD_INSTALL(FILES ${htmlfile} DESTINATION ${PKG_DOC_DIR}/manual/html COMPONENT manual) - ENDFOREACH(rstfile ${manual_sources}) - - #make the html manual a build-time dependency - ADD_CUSTOM_TARGET(manual_html ALL DEPENDS ${manual_html_files}) - UHD_INSTALL(FILES ${manual_sources} DESTINATION ${PKG_DOC_DIR}/manual/rst COMPONENT manual) - - #resources for html manual - ADD_CUSTOM_COMMAND( - TARGET manual_html POST_BUILD - COMMAND ${CMAKE_COMMAND} -E copy_directory ${CMAKE_CURRENT_SOURCE_DIR}/res ${CMAKE_CURRENT_BINARY_DIR}/res - ) - UHD_INSTALL(DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/res DESTINATION ${PKG_DOC_DIR}/manual/html COMPONENT manual) - + SET(ENABLE_MANUAL_OR_DOXYGEN true) + FILE(GLOB manual_sources "*.dox") + SET(DOXYGEN_DEPENDENCIES ${manual_sources}) + SET(DOXYGEN_INPUT_DIRS ${CMAKE_SOURCE_DIR}/docs) + SET(DOXYGEN_DEP_COMPONENT "manual") ENDIF(ENABLE_MANUAL) ######################################################################## -# Setup Doxygen +# Setup API documentation (using Doxygen) ######################################################################## MESSAGE(STATUS "") -FIND_PACKAGE(Doxygen) - -LIBUHD_REGISTER_COMPONENT("Doxygen" ENABLE_DOXYGEN ON "DOXYGEN_FOUND" OFF) +LIBUHD_REGISTER_COMPONENT("API/Doxygen" ENABLE_DOXYGEN ON "DOXYGEN_FOUND" OFF) +OPTION(ENABLE_DOXYGEN_FULL "Use Doxygen to document the entire source tree (not just API)" OFF) IF(LIBUHDDEV_PKG) SET(PKG_DOC_DIR share/doc/libuhd-dev) ENDIF(LIBUHDDEV_PKG) IF(ENABLE_DOXYGEN) + SET(ENABLE_MANUAL_OR_DOXYGEN true) + #make doxygen directory depend on the header files + FILE(GLOB_RECURSE header_files ${CMAKE_SOURCE_DIR}/include/*.hpp) + SET(DOXYGEN_DEPENDENCIES ${DOXYGEN_DEPENDENCIES} ${header_files}) + IF(ENABLE_DOXYGEN_FULL) + SET(DOXYGEN_INPUT_DIRS "${DOXYGEN_INPUT_DIRS} ${CMAKE_SOURCE_DIR}/include ${CMAKE_SOURCE_DIR}/lib") + ELSE(ENABLE_DOXYGEN_FULL) + SET(DOXYGEN_INPUT_DIRS "${DOXYGEN_INPUT_DIRS} ${CMAKE_SOURCE_DIR}/include") + ENDIF(ENABLE_DOXYGEN_FULL) + + SET(DOXYGEN_DEP_COMPONENT "doxygen") +ENDIF(ENABLE_DOXYGEN) + +######################################################################## +# Run Doxygen (on code and/or manual, depending on CMake flags) +######################################################################## +MESSAGE(STATUS "") +IF(ENABLE_MANUAL_OR_DOXYGEN) #generate the doxygen configuration file SET(CMAKE_CURRENT_BINARY_DIR_DOXYGEN ${CMAKE_CURRENT_BINARY_DIR}/doxygen) CONFIGURE_FILE( @@ -118,21 +79,22 @@ IF(ENABLE_DOXYGEN) #make doxygen directory depend on the header files FILE(GLOB_RECURSE header_files ${CMAKE_SOURCE_DIR}/include/*.hpp) ADD_CUSTOM_COMMAND( - OUTPUT ${CMAKE_CURRENT_BINARY_DIR_DOXYGEN} DEPENDS ${header_files} + OUTPUT ${CMAKE_CURRENT_BINARY_DIR_DOXYGEN} DEPENDS ${DOXYGEN_DEPENDENCIES} COMMAND ${DOXYGEN_EXECUTABLE} ${CMAKE_CURRENT_BINARY_DIR}/Doxyfile COMMENT "Generating documentation with doxygen" ) #make the doxygen generation a built-time dependency ADD_CUSTOM_TARGET(doxygen_docs ALL DEPENDS ${CMAKE_CURRENT_BINARY_DIR_DOXYGEN}) - UHD_INSTALL(DIRECTORY ${CMAKE_CURRENT_BINARY_DIR_DOXYGEN} DESTINATION ${PKG_DOC_DIR} COMPONENT doxygen) -ENDIF(ENABLE_DOXYGEN) + UHD_INSTALL(DIRECTORY ${CMAKE_CURRENT_BINARY_DIR_DOXYGEN} DESTINATION ${PKG_DOC_DIR} COMPONENT ${DOXYGEN_DEP_COMPONENT}) +ENDIF(ENABLE_MANUAL_OR_DOXYGEN) ######################################################################## # List of man page sources ######################################################################## SET(man_page_sources + octoclock_firmware_burner.1 uhd_cal_rx_iq_balance.1 uhd_cal_tx_dc_offset.1 uhd_cal_tx_iq_balance.1 diff --git a/host/docs/Doxyfile.in b/host/docs/Doxyfile.in index 7395516b5..d48e50fc4 100644 --- a/host/docs/Doxyfile.in +++ b/host/docs/Doxyfile.in @@ -1,14 +1,16 @@ -# Doxyfile 1.6.1 +# Doxyfile 1.8.4 # This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project +# doxygen (www.doxygen.org) for a project. # -# All text after a hash (#) is considered a comment and will be ignored +# All text after a double hash (##) is considered a comment and is placed +# in front of the TAG it is preceding . +# All text after a hash (#) is considered a comment and will be ignored. # The format is: # TAG = value [value, ...] # For lists items can also be appended using: # TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") +# Values that contain spaces should be placed between quotes (" "). #--------------------------------------------------------------------------- # Project related configuration options @@ -22,16 +24,30 @@ DOXYFILE_ENCODING = UTF-8 -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. +# The PROJECT_NAME tag is a single word (or sequence of words) that should +# identify the project. Note that if you do not use Doxywizard you need +# to put quotes around the project name if it contains spaces. -PROJECT_NAME = @CPACK_PACKAGE_NAME@ +PROJECT_NAME = "USRP Hardware Driver and USRP Manual" # The PROJECT_NUMBER tag can be used to enter a project or revision number. # This could be handy for archiving the generated documentation or # if some version control system is used. -PROJECT_NUMBER = @CPACK_PACKAGE_VERSION@ +PROJECT_NUMBER = "Version: @CPACK_PACKAGE_VERSION@" + +# Using the PROJECT_BRIEF tag one can provide an optional one line description +# for a project that appears at the top of each page and should give viewer +# a quick idea about the purpose of the project. Keep the description short. + +PROJECT_BRIEF = "UHD and USRP Manual" + +# With the PROJECT_LOGO tag one can specify an logo or icon that is +# included in the documentation. The maximum height of the logo should not +# exceed 55 pixels and the maximum width should not exceed 200 pixels. +# Doxygen will copy the logo to the output directory. + +PROJECT_LOGO = @CMAKE_SOURCE_DIR@/docs/Ettus_Logo.png # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) # base path where the generated documentation will be put. @@ -56,9 +72,9 @@ CREATE_SUBDIRS = NO # Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, # Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, # Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. +# messages), Korean, Korean-en, Latvian, Lithuanian, Norwegian, Macedonian, +# Persian, Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrillic, +# Slovak, Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. OUTPUT_LANGUAGE = English @@ -112,7 +128,9 @@ FULL_PATH_NAMES = YES # only done if one of the specified strings matches the left-hand part of # the path. The tag can be used to show relative paths in the file list. # If left blank the directory from which doxygen is run is used as the -# path to strip. +# path to strip. Note that you specify absolute paths here, but also +# relative paths, which will be relative from the directory where doxygen is +# started. STRIP_FROM_PATH = @CMAKE_SOURCE_DIR@ @@ -123,10 +141,10 @@ STRIP_FROM_PATH = @CMAKE_SOURCE_DIR@ # definition is used. Otherwise one should specify the include paths that # are normally passed to the compiler using the -I flag. -STRIP_FROM_INC_PATH = +STRIP_FROM_INC_PATH = @CMAKE_SOURCE_DIR@/include # If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems +# (but less readable) file names. This can be useful if your file system # doesn't support long names like on DOS, Mac, or CD-ROM. SHORT_NAMES = NO @@ -181,6 +199,13 @@ TAB_SIZE = 8 ALIASES = +# This tag can be used to specify a number of word-keyword mappings (TCL only). +# A mapping has the form "name=value". For example adding +# "class=itcl::class" will allow you to use the command class in the +# itcl::class meaning. + +TCL_SUBST = + # Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C # sources only. Doxygen will then generate output that is more tailored for C. # For instance, some of the names that are used will be different. The list @@ -207,22 +232,40 @@ OPTIMIZE_FOR_FORTRAN = NO OPTIMIZE_OUTPUT_VHDL = NO -# Doxygen selects the parser to use depending on the extension of the files it parses. -# With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this tag. -# The format is ext=language, where ext is a file extension, and language is one of -# the parsers supported by doxygen: IDL, Java, Javascript, C#, C, C++, D, PHP, -# Objective-C, Python, Fortran, VHDL, C, C++. For instance to make doxygen treat -# .inc files as Fortran files (default is PHP), and .f files as C (default is Fortran), -# use: inc=Fortran f=C. Note that for custom extensions you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. +# Doxygen selects the parser to use depending on the extension of the files it +# parses. With this tag you can assign which parser to use for a given +# extension. Doxygen has a built-in mapping, but you can override or extend it +# using this tag. The format is ext=language, where ext is a file extension, +# and language is one of the parsers supported by doxygen: IDL, Java, +# Javascript, CSharp, C, C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, +# C++. For instance to make doxygen treat .inc files as Fortran files (default +# is PHP), and .f files as C (default is Fortran), use: inc=Fortran f=C. Note +# that for custom extensions you also need to set FILE_PATTERNS otherwise the +# files are not read by doxygen. EXTENSION_MAPPING = +# If MARKDOWN_SUPPORT is enabled (the default) then doxygen pre-processes all +# comments according to the Markdown format, which allows for more readable +# documentation. See http://daringfireball.net/projects/markdown/ for details. +# The output of markdown processing is further processed by doxygen, so you +# can mix doxygen, HTML, and XML commands with Markdown formatting. +# Disable only in case of backward compatibilities issues. + +MARKDOWN_SUPPORT = YES + +# When enabled doxygen tries to link words that correspond to documented +# classes, or namespaces to their corresponding documentation. Such a link can +# be prevented in individual cases by by putting a % sign in front of the word +# or globally by setting AUTOLINK_SUPPORT to NO. + +AUTOLINK_SUPPORT = YES + # If you use STL classes (i.e. std::string, std::vector, etc.) but do not want # to include (a tag file for) the STL sources as input, then you should # set this tag to YES in order to let doxygen match functions declarations and # definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration +# func(std::string) {}). This also makes the inheritance and collaboration # diagrams that involve STL classes more complete and accurate. BUILTIN_STL_SUPPORT = YES @@ -238,10 +281,10 @@ CPP_CLI_SUPPORT = NO SIP_SUPPORT = NO -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or +# For Microsoft's IDL there are propget and propput attributes to indicate +# getter and setter methods for a property. Setting this option to YES (the +# default) will make doxygen replace the get and set methods by a property in +# the documentation. This will only work if the methods are indeed getting or # setting a simple type. If this is not the case, or you want to show the # methods anyway, you should set this option to NO. @@ -262,6 +305,22 @@ DISTRIBUTE_GROUP_DOC = NO SUBGROUPING = YES +# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and +# unions are shown inside the group in which they are included (e.g. using +# @ingroup) instead of on a separate page (for HTML and Man pages) or +# section (for LaTeX and RTF). + +INLINE_GROUPED_CLASSES = NO + +# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and +# unions with only public data fields or simple typedef fields will be shown +# inline in the documentation of the scope in which they are defined (i.e. file, +# namespace, or group documentation), provided this scope is documented. If set +# to NO (the default), structs, classes, and unions are shown on a separate +# page (for HTML and Man pages) or section (for LaTeX and RTF). + +INLINE_SIMPLE_STRUCTS = NO + # When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum # is documented as struct, union, or enum with the name of the typedef. So # typedef struct TypeS {} TypeT, will appear in the documentation as a struct @@ -272,21 +331,16 @@ SUBGROUPING = YES TYPEDEF_HIDES_STRUCT = NO -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 +# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This +# cache is used to resolve symbols given their name and scope. Since this can +# be an expensive process and often the same symbol appear multiple times in +# the code, doxygen keeps a cache of pre-resolved symbols. If the cache is too +# small doxygen will become slower. If the cache is too large, memory is wasted. +# The cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid +# range is 0..9, the default is 0, corresponding to a cache size of 2^16 = 65536 +# symbols. + +LOOKUP_CACHE_SIZE = 0 #--------------------------------------------------------------------------- # Build related configuration options @@ -295,7 +349,7 @@ SYMBOL_CACHE_SIZE = 0 # If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in # documentation are documented, even if no documentation was available. # Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES +# the EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES EXTRACT_ALL = YES @@ -304,6 +358,11 @@ EXTRACT_ALL = YES EXTRACT_PRIVATE = NO +# If the EXTRACT_PACKAGE tag is set to YES all members with package or internal +# scope will be included in the documentation. + +EXTRACT_PACKAGE = NO + # If the EXTRACT_STATIC tag is set to YES all static members of a file # will be included in the documentation. @@ -326,7 +385,7 @@ EXTRACT_LOCAL_METHODS = NO # extracted and appear in the documentation as a namespace called # 'anonymous_namespace{file}', where file will be replaced with the base # name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. +# anonymous namespaces are hidden. EXTRACT_ANON_NSPACES = NO @@ -386,6 +445,12 @@ HIDE_SCOPE_NAMES = NO SHOW_INCLUDE_FILES = YES +# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen +# will list include files with double quotes in the documentation +# rather than with sharp brackets. + +FORCE_LOCAL_INCLUDES = NO + # If the INLINE_INFO tag is set to YES (the default) then a tag [inline] # is inserted in the documentation for inline members. @@ -405,7 +470,13 @@ SORT_MEMBER_DOCS = YES SORT_BRIEF_DOCS = NO -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the (brief and detailed) documentation of class members so that constructors and destructors are listed first. If set to NO (the default) the constructors will appear in the respective orders defined by SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. +# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen +# will sort the (brief and detailed) documentation of class members so that +# constructors and destructors are listed first. If set to NO (the default) +# the constructors will appear in the respective orders defined by +# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. +# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO +# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. SORT_MEMBERS_CTORS_1ST = NO @@ -425,6 +496,15 @@ SORT_GROUP_NAMES = NO SORT_BY_SCOPE_NAME = NO +# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to +# do proper type resolution of all parameters of a function it will reject a +# match between the prototype and the implementation of a member function even +# if there is only one candidate or it is obvious which candidate to choose +# by doing a simple string match. By disabling STRICT_PROTO_MATCHING doxygen +# will still accept a match between prototype and implementation in such cases. + +STRICT_PROTO_MATCHING = NO + # The GENERATE_TODOLIST tag can be used to enable (YES) or # disable (NO) the todo list. This list is created by putting \todo # commands in the documentation. @@ -450,15 +530,16 @@ GENERATE_BUGLIST = YES GENERATE_DEPRECATEDLIST= YES # The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. +# documentation sections, marked by \if section-label ... \endif +# and \cond section-label ... \endcond blocks. ENABLED_SECTIONS = # The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in +# the initial value of a variable or macro consists of for it to appear in # the documentation. If the initializer consists of more lines than specified # here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the +# The appearance of the initializer of individual variables and macros in the # documentation can be controlled using \showinitializer or \hideinitializer # command in the documentation regardless of this setting. @@ -470,12 +551,6 @@ MAX_INITIALIZER_LINES = 30 SHOW_USED_FILES = YES -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - # Set the SHOW_FILES tag to NO to disable the generation of the Files page. # This will remove the Files entry from the Quick Index and from the # Folder Tree View (if specified). The default is YES. @@ -499,15 +574,26 @@ SHOW_NAMESPACES = YES FILE_VERSION_FILTER = -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed by -# doxygen. The layout file controls the global structure of the generated output files -# in an output format independent way. The create the layout file that represents -# doxygen's defaults, run doxygen with the -l option. You can optionally specify a -# file name after the option, if omitted DoxygenLayout.xml will be used as the name -# of the layout file. +# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed +# by doxygen. The layout file controls the global structure of the generated +# output files in an output format independent way. To create the layout file +# that represents doxygen's defaults, run doxygen with the -l option. +# You can optionally specify a file name after the option, if omitted +# DoxygenLayout.xml will be used as the name of the layout file. LAYOUT_FILE = +# The CITE_BIB_FILES tag can be used to specify one or more bib files +# containing the references data. This must be a list of .bib files. The +# .bib extension is automatically appended if omitted. Using this command +# requires the bibtex tool to be installed. See also +# http://en.wikipedia.org/wiki/BibTeX for more info. For LaTeX the style +# of the bibliography can be controlled using LATEX_BIB_STYLE. To use this +# feature you need bibtex and perl available in the search path. Do not use +# file names with spaces, bibtex cannot handle them. + +CITE_BIB_FILES = + #--------------------------------------------------------------------------- # configuration options related to warning and progress messages #--------------------------------------------------------------------------- @@ -536,7 +622,7 @@ WARN_IF_UNDOCUMENTED = YES WARN_IF_DOC_ERROR = YES -# This WARN_NO_PARAMDOC option can be abled to get warnings for +# The WARN_NO_PARAMDOC option can be enabled to get warnings for # functions that are documented, but have no documentation for their parameters # or return value. If set to NO (the default) doxygen will only warn about # wrong or incomplete parameter documentation, but not about the absence of @@ -568,7 +654,7 @@ WARN_LOGFILE = # directories like "/usr/src/myproject". Separate the files or directories # with spaces. -INPUT = @CMAKE_SOURCE_DIR@/include +INPUT = @DOXYGEN_INPUT_DIRS@ # This tag can be used to specify the character encoding of the source files # that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is @@ -582,10 +668,11 @@ INPUT_ENCODING = UTF-8 # FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp # and *.h) to filter out the source-files in the directories. If left # blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 +# *.c *.cc *.cxx *.cpp *.c++ *.d *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh +# *.hxx *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.dox *.py +# *.f90 *.f *.for *.vhd *.vhdl -FILE_PATTERNS = *.hpp +FILE_PATTERNS = *.hpp *.dox *.h # The RECURSIVE tag can be used to turn specify whether or not subdirectories # should be searched for input files as well. Possible values are YES and NO. @@ -593,14 +680,16 @@ FILE_PATTERNS = *.hpp RECURSIVE = YES -# The EXCLUDE tag can be used to specify files and/or directories that should +# The EXCLUDE tag can be used to specify files and/or directories that should be # excluded from the INPUT source files. This way you can easily exclude a # subdirectory from a directory tree whose root is specified with the INPUT tag. +# Note that relative paths are relative to the directory from which doxygen is +# run. EXCLUDE = -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded +# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or +# directories that are symbolic links (a Unix file system feature) are excluded # from the input. EXCLUDE_SYMLINKS = NO @@ -645,7 +734,7 @@ EXAMPLE_RECURSIVE = NO # directories that contain image that are included in the documentation (see # the \image command). -IMAGE_PATH = +IMAGE_PATH = @CMAKE_SOURCE_DIR@/docs/res # The INPUT_FILTER tag can be used to specify a program that doxygen should # invoke to filter for each input file. Doxygen will invoke the filter program @@ -653,8 +742,10 @@ IMAGE_PATH = # is the value of the INPUT_FILTER tag, and <input-file> is the name of an # input file. Doxygen will then use the output that the filter program writes # to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. +# If FILTER_PATTERNS is specified, this tag will be ignored. +# Note that the filter must not add or remove lines; it is applied before the +# code is scanned, but not when the output code is generated. If lines are added +# or removed, the anchors will not be placed correctly. INPUT_FILTER = @@ -664,8 +755,8 @@ INPUT_FILTER = # filter if there is a match. # The filters are a list of the form: # pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. +# info on how filters are used. If FILTER_PATTERNS is empty or if +# non of the patterns match the file name, INPUT_FILTER is applied. FILTER_PATTERNS = @@ -675,6 +766,21 @@ FILTER_PATTERNS = FILTER_SOURCE_FILES = NO +# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file +# pattern. A pattern will override the setting for FILTER_PATTERN (if any) +# and it is also possible to disable source filtering for a specific pattern +# using *.ext= (so without naming a filter). This option only has effect when +# FILTER_SOURCE_FILES is enabled. + +FILTER_SOURCE_PATTERNS = + +# If the USE_MD_FILE_AS_MAINPAGE tag refers to the name of a markdown file that +# is part of the input, its contents will be placed on the main page +# (index.html). This can be useful if you have a project on for instance GitHub +# and want reuse the introduction page also for the doxygen output. + +USE_MDFILE_AS_MAINPAGE = + #--------------------------------------------------------------------------- # configuration options related to source browsing #--------------------------------------------------------------------------- @@ -693,7 +799,7 @@ INLINE_SOURCES = NO # Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct # doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. +# fragments. Normal C, C++ and Fortran comments will always remain visible. STRIP_CODE_COMMENTS = YES @@ -777,7 +883,14 @@ HTML_FILE_EXTENSION = .html # The HTML_HEADER tag can be used to specify a personal HTML header for # each generated HTML page. If it is left blank doxygen will generate a -# standard header. +# standard header. Note that when using a custom header you are responsible +# for the proper inclusion of any scripts and style sheets that doxygen +# needs, which is dependent on the configuration options used. +# It is advised to generate a default header using "doxygen -w html +# header.html footer.html stylesheet.css YourConfigFile" and then modify +# that header. Note that the header is subject to change so you typically +# have to redo this when upgrading to a newer version of doxygen or when +# changing the value of configuration settings such as GENERATE_TREEVIEW! HTML_HEADER = @@ -789,27 +902,80 @@ HTML_FOOTER = # The HTML_STYLESHEET tag can be used to specify a user-defined cascading # style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! +# fine-tune the look of the HTML output. If left blank doxygen will +# generate a default style sheet. Note that it is recommended to use +# HTML_EXTRA_STYLESHEET instead of this one, as it is more robust and this +# tag will in the future become obsolete. HTML_STYLESHEET = -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. +# The HTML_EXTRA_STYLESHEET tag can be used to specify an additional +# user-defined cascading style sheet that is included after the standard +# style sheets created by doxygen. Using this option one can overrule +# certain style aspects. This is preferred over using HTML_STYLESHEET +# since it does not replace the standard style sheet and is therefor more +# robust against future updates. Doxygen will copy the style sheet file to +# the output directory. + +HTML_EXTRA_STYLESHEET = + +# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or +# other source files which should be copied to the HTML output directory. Note +# that these files will be copied to the base HTML output directory. Use the +# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these +# files. In the HTML_STYLESHEET file, use the file name only. Also note that +# the files will be copied as-is; there are no commands or markers available. + +HTML_EXTRA_FILES = + +# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. +# Doxygen will adjust the colors in the style sheet and background images +# according to this color. Hue is specified as an angle on a colorwheel, +# see http://en.wikipedia.org/wiki/Hue for more information. +# For instance the value 0 represents red, 60 is yellow, 120 is green, +# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. +# The allowed range is 0 to 359. + +HTML_COLORSTYLE_HUE = 92 + +# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of +# the colors in the HTML output. For a value of 0 the output will use +# grayscales only. A value of 255 will produce the most vivid colors. + +HTML_COLORSTYLE_SAT = 31 + +# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to +# the luminance component of the colors in the HTML output. Values below +# 100 gradually make the output lighter, whereas values above 100 make +# the output darker. The value divided by 100 is the actual gamma applied, +# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, +# and 100 does not change the gamma. -HTML_ALIGN_MEMBERS = YES +HTML_COLORSTYLE_GAMMA = 65 + +# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML +# page will contain the date and time when the page was generated. Setting +# this to NO can help when comparing the output of multiple runs. + +HTML_TIMESTAMP = YES # If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML # documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). +# page has loaded. HTML_DYNAMIC_SECTIONS = NO +# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of +# entries shown in the various tree structured indices initially; the user +# can expand and collapse entries dynamically later on. Doxygen will expand +# the tree to such a level that at most the specified number of entries are +# visible (unless a fully collapsed tree already exceeds this amount). +# So setting the number of entries 1 will produce a full collapsed tree by +# default. 0 is a special value representing an infinite number of entries +# and will result in a full expanded tree by default. + +HTML_INDEX_NUM_ENTRIES = 100 + # If the GENERATE_DOCSET tag is set to YES, additional index files # will be generated that can be used as input for Apple's Xcode 3 # integrated development environment, introduced with OSX 10.5 (Leopard). @@ -818,7 +984,8 @@ HTML_DYNAMIC_SECTIONS = NO # directory and running "make install" will install the docset in # ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find # it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html for more information. +# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html +# for more information. GENERATE_DOCSET = NO @@ -836,6 +1003,16 @@ DOCSET_FEEDNAME = "Doxygen generated docs" DOCSET_BUNDLE_ID = org.doxygen.Project +# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely +# identify the documentation publisher. This should be a reverse domain-name +# style string, e.g. com.mycompany.MyDocSet.documentation. + +DOCSET_PUBLISHER_ID = org.doxygen.Publisher + +# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. + +DOCSET_PUBLISHER_NAME = Publisher + # If the GENERATE_HTMLHELP tag is set to YES, additional index files # will be generated that can be used as input for tools like the # Microsoft HTML help workshop to generate a compiled HTML help file (.chm) @@ -880,10 +1057,10 @@ BINARY_TOC = NO TOC_EXPAND = NO -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and QHP_VIRTUAL_FOLDER -# are set, an additional index file will be generated that can be used as input for -# Qt's qhelpgenerator to generate a Qt Compressed Help (.qch) of the generated -# HTML documentation. +# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and +# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated +# that can be used as input for Qt's qhelpgenerator to generate a +# Qt Compressed Help (.qch) of the generated HTML documentation. GENERATE_QHP = NO @@ -905,20 +1082,24 @@ QHP_NAMESPACE = QHP_VIRTUAL_FOLDER = doc -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to add. -# For more information please see +# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to +# add. For more information please see # http://doc.trolltech.com/qthelpproject.html#custom-filters QHP_CUST_FILTER_NAME = -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the custom filter to add.For more information please see -# <a href="http://doc.trolltech.com/qthelpproject.html#custom-filters">Qt Help Project / Custom Filters</a>. +# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the +# custom filter to add. For more information please see +# <a href="http://doc.trolltech.com/qthelpproject.html#custom-filters"> +# Qt Help Project / Custom Filters</a>. QHP_CUST_FILTER_ATTRS = -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this project's +# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this +# project's # filter section matches. -# <a href="http://doc.trolltech.com/qthelpproject.html#filter-attributes">Qt Help Project / Filter Attributes</a>. +# <a href="http://doc.trolltech.com/qthelpproject.html#filter-attributes"> +# Qt Help Project / Filter Attributes</a>. QHP_SECT_FILTER_ATTRS = @@ -929,16 +1110,30 @@ QHP_SECT_FILTER_ATTRS = QHG_LOCATION = -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. +# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files +# will be generated, which together with the HTML files, form an Eclipse help +# plugin. To install this plugin and make it available under the help contents +# menu in Eclipse, the contents of the directory containing the HTML and XML +# files needs to be copied into the plugins directory of eclipse. The name of +# the directory within the plugins directory should be the same as +# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before +# the help appears. -DISABLE_INDEX = NO +GENERATE_ECLIPSEHELP = NO -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. +# A unique identifier for the eclipse help plugin. When installing the plugin +# the directory name containing the HTML and XML files should also have +# this name. -ENUM_VALUES_PER_LINE = 4 +ECLIPSE_DOC_ID = org.doxygen.Project + +# The DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) +# at top of each HTML page. The value NO (the default) enables the index and +# the value YES disables it. Since the tabs have the same information as the +# navigation tree you can set this option to NO if you already set +# GENERATE_TREEVIEW to YES. + +DISABLE_INDEX = YES # The GENERATE_TREEVIEW tag is used to specify whether a tree-like index # structure should be generated to display hierarchical information. @@ -947,13 +1142,17 @@ ENUM_VALUES_PER_LINE = 4 # is generated for HTML Help). For this to work a browser that supports # JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). # Windows users are probably better off using the HTML help feature. +# Since the tree basically has the same information as the tab index you +# could consider to set DISABLE_INDEX to NO when enabling this option. -GENERATE_TREEVIEW = NO +GENERATE_TREEVIEW = YES -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. +# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values +# (range [0,1..20]) that doxygen will group on one line in the generated HTML +# documentation. Note that a value of 0 will completely suppress the enum +# values from appearing in the overview section. -USE_INLINE_TREES = NO +ENUM_VALUES_PER_LINE = 4 # If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be # used to set the initial width (in pixels) of the frame in which the tree @@ -961,6 +1160,11 @@ USE_INLINE_TREES = NO TREEVIEW_WIDTH = 250 +# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open +# links to external symbols imported via tag files in a separate window. + +EXT_LINKS_IN_WINDOW = NO + # Use this tag to change the font size of Latex formulas included # as images in the HTML documentation. The default is 10. Note that # when you change the font size after a successful doxygen run you need @@ -969,13 +1173,112 @@ TREEVIEW_WIDTH = 250 FORMULA_FONTSIZE = 10 -# When the SEARCHENGINE tag is enable doxygen will generate a search box for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using HTML help (GENERATE_HTMLHELP) or Qt help (GENERATE_QHP) -# there is already a search function so this one should typically -# be disabled. +# Use the FORMULA_TRANPARENT tag to determine whether or not the images +# generated for formulas are transparent PNGs. Transparent PNGs are +# not supported properly for IE 6.0, but are supported on all modern browsers. +# Note that when changing this option you need to delete any form_*.png files +# in the HTML output before the changes have effect. + +FORMULA_TRANSPARENT = YES + +# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax +# (see http://www.mathjax.org) which uses client side Javascript for the +# rendering instead of using prerendered bitmaps. Use this if you do not +# have LaTeX installed or if you want to formulas look prettier in the HTML +# output. When enabled you may also need to install MathJax separately and +# configure the path to it using the MATHJAX_RELPATH option. + +USE_MATHJAX = NO + +# When MathJax is enabled you can set the default output format to be used for +# the MathJax output. Supported types are HTML-CSS, NativeMML (i.e. MathML) and +# SVG. The default value is HTML-CSS, which is slower, but has the best +# compatibility. + +MATHJAX_FORMAT = HTML-CSS + +# When MathJax is enabled you need to specify the location relative to the +# HTML output directory using the MATHJAX_RELPATH option. The destination +# directory should contain the MathJax.js script. For instance, if the mathjax +# directory is located at the same level as the HTML output directory, then +# MATHJAX_RELPATH should be ../mathjax. The default value points to +# the MathJax Content Delivery Network so you can quickly see the result without +# installing MathJax. +# However, it is strongly recommended to install a local +# copy of MathJax from http://www.mathjax.org before deployment. + +MATHJAX_RELPATH = http://cdn.mathjax.org/mathjax/latest + +# The MATHJAX_EXTENSIONS tag can be used to specify one or MathJax extension +# names that should be enabled during MathJax rendering. + +MATHJAX_EXTENSIONS = + +# The MATHJAX_CODEFILE tag can be used to specify a file with javascript +# pieces of code that will be used on startup of the MathJax code. + +MATHJAX_CODEFILE = + +# When the SEARCHENGINE tag is enabled doxygen will generate a search box +# for the HTML output. The underlying search engine uses javascript +# and DHTML and should work on any modern browser. Note that when using +# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets +# (GENERATE_DOCSET) there is already a search function so this one should +# typically be disabled. For large projects the javascript based search engine +# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. SEARCHENGINE = YES +# When the SERVER_BASED_SEARCH tag is enabled the search engine will be +# implemented using a web server instead of a web client using Javascript. +# There are two flavours of web server based search depending on the +# EXTERNAL_SEARCH setting. When disabled, doxygen will generate a PHP script for +# searching and an index file used by the script. When EXTERNAL_SEARCH is +# enabled the indexing and searching needs to be provided by external tools. +# See the manual for details. + +SERVER_BASED_SEARCH = NO + +# When EXTERNAL_SEARCH is enabled doxygen will no longer generate the PHP +# script for searching. Instead the search results are written to an XML file +# which needs to be processed by an external indexer. Doxygen will invoke an +# external search engine pointed to by the SEARCHENGINE_URL option to obtain +# the search results. Doxygen ships with an example indexer (doxyindexer) and +# search engine (doxysearch.cgi) which are based on the open source search +# engine library Xapian. See the manual for configuration details. + +EXTERNAL_SEARCH = NO + +# The SEARCHENGINE_URL should point to a search engine hosted by a web server +# which will returned the search results when EXTERNAL_SEARCH is enabled. +# Doxygen ships with an example search engine (doxysearch) which is based on +# the open source search engine library Xapian. See the manual for configuration +# details. + +SEARCHENGINE_URL = + +# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the unindexed +# search data is written to a file for indexing by an external tool. With the +# SEARCHDATA_FILE tag the name of this file can be specified. + +SEARCHDATA_FILE = searchdata.xml + +# When SERVER_BASED_SEARCH AND EXTERNAL_SEARCH are both enabled the +# EXTERNAL_SEARCH_ID tag can be used as an identifier for the project. This is +# useful in combination with EXTRA_SEARCH_MAPPINGS to search through multiple +# projects and redirect the results back to the right project. + +EXTERNAL_SEARCH_ID = + +# The EXTRA_SEARCH_MAPPINGS tag can be used to enable searching through doxygen +# projects other than the one defined by this configuration file, but that are +# all added to the same external search index. Each project needs to have a +# unique id set via EXTERNAL_SEARCH_ID. The search mapping then maps the id +# of to a relative location where the documentation can be found. +# The format is: EXTRA_SEARCH_MAPPINGS = id1=loc1 id2=loc2 ... + +EXTRA_SEARCH_MAPPINGS = + #--------------------------------------------------------------------------- # configuration options related to the LaTeX output #--------------------------------------------------------------------------- @@ -993,6 +1296,9 @@ LATEX_OUTPUT = latex # The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be # invoked. If left blank `latex' will be used as the default command name. +# Note that when enabling USE_PDFLATEX this option is only used for +# generating bitmaps for formulas in the HTML output, but not in the +# Makefile that is written to the output directory. LATEX_CMD_NAME = latex @@ -1009,8 +1315,8 @@ MAKEINDEX_CMD_NAME = makeindex COMPACT_LATEX = NO # The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. +# by the printer. Possible values are: a4, letter, legal and +# executive. If left blank a4 will be used. PAPER_TYPE = a4wide @@ -1026,6 +1332,20 @@ EXTRA_PACKAGES = LATEX_HEADER = +# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for +# the generated latex document. The footer should contain everything after +# the last chapter. If it is left blank doxygen will generate a +# standard footer. Notice: only use this tag if you know what you are doing! + +LATEX_FOOTER = + +# The LATEX_EXTRA_FILES tag can be used to specify one or more extra images +# or other source files which should be copied to the LaTeX output directory. +# Note that the files will be copied as-is; there are no commands or markers +# available. + +LATEX_EXTRA_FILES = + # If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated # is prepared for conversion to pdf (using ps2pdf). The pdf file will # contain links (just like the HTML output) instead of page references @@ -1052,10 +1372,19 @@ LATEX_BATCHMODE = NO LATEX_HIDE_INDICES = NO -# If LATEX_SOURCE_CODE is set to YES then doxygen will include source code with syntax highlighting in the LaTeX output. Note that which sources are shown also depends on other settings such as SOURCE_BROWSER. +# If LATEX_SOURCE_CODE is set to YES then doxygen will include +# source code with syntax highlighting in the LaTeX output. +# Note that which sources are shown also depends on other settings +# such as SOURCE_BROWSER. LATEX_SOURCE_CODE = NO +# The LATEX_BIB_STYLE tag can be used to specify the style to use for the +# bibliography, e.g. plainnat, or ieeetr. The default style is "plain". See +# http://en.wikipedia.org/wiki/BibTeX for more info. + +LATEX_BIB_STYLE = plain + #--------------------------------------------------------------------------- # configuration options related to the RTF output #--------------------------------------------------------------------------- @@ -1087,7 +1416,7 @@ COMPACT_RTF = NO RTF_HYPERLINKS = NO -# Load stylesheet definitions from file. Syntax is similar to doxygen's +# Load style sheet definitions from file. Syntax is similar to doxygen's # config file, i.e. a series of assignments. You only have to provide # replacements, missing definitions are set to their default value. @@ -1162,6 +1491,21 @@ XML_DTD = XML_PROGRAMLISTING = YES #--------------------------------------------------------------------------- +# configuration options related to the DOCBOOK output +#--------------------------------------------------------------------------- + +# If the GENERATE_DOCBOOK tag is set to YES Doxygen will generate DOCBOOK files +# that can be used to generate PDF. + +GENERATE_DOCBOOK = NO + +# The DOCBOOK_OUTPUT tag is used to specify where the DOCBOOK pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be put in +# front of it. If left blank docbook will be used as the default path. + +DOCBOOK_OUTPUT = docbook + +#--------------------------------------------------------------------------- # configuration options for the AutoGen Definitions output #--------------------------------------------------------------------------- @@ -1232,7 +1576,7 @@ MACRO_EXPANSION = YES EXPAND_ONLY_PREDEF = NO # If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. +# pointed to by INCLUDE_PATH will be searched when a #include is found. SEARCH_INCLUDES = YES @@ -1262,15 +1606,15 @@ PREDEFINED = # If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then # this tag can be used to specify a list of macro names that should be expanded. # The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. +# Use the PREDEFINED tag if you want to use a different macro definition that +# overrules the definition found in the source code. EXPAND_AS_DEFINED = # If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. +# doxygen's preprocessor will remove all references to function-like macros +# that are alone on a line, have an all uppercase name, and do not end with a +# semicolon, because these will confuse the parser if not removed. SKIP_FUNCTION_MACROS = YES @@ -1278,22 +1622,18 @@ SKIP_FUNCTION_MACROS = YES # Configuration::additions related to external references #--------------------------------------------------------------------------- -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: +# The TAGFILES option can be used to specify one or more tagfiles. For each +# tag file the location of the external documentation should be added. The +# format of a tag file without this location is as follows: # # TAGFILES = file1 file2 ... # Adding location for the tag files is done as follows: # # TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. +# where "loc1" and "loc2" can be relative or absolute paths +# or URLs. Note that each tag file must have a unique name (where the name does +# NOT include the path). If a tag file is not located in the directory in which +# doxygen is run, you must also specify the path to the tagfile here. TAGFILES = @@ -1314,6 +1654,12 @@ ALLEXTERNALS = NO EXTERNAL_GROUPS = YES +# If the EXTERNAL_PAGES tag is set to YES all external pages will be listed +# in the related pages index. If set to NO, only the current project's +# pages will be listed. + +EXTERNAL_PAGES = YES + # The PERL_PATH should be the absolute path and name of the perl script # interpreter (i.e. the result of `which perl'). @@ -1326,9 +1672,8 @@ PERL_PATH = /usr/bin/perl # If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will # generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base # or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. +# this option also works with HAVE_DOT disabled, but it is recommended to +# install and use dot, since it yields more powerful graphs. CLASS_DIAGRAMS = YES @@ -1354,33 +1699,38 @@ HIDE_UNDOC_RELATIONS = YES HAVE_DOT = NO -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. +# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is +# allowed to run in parallel. When set to 0 (the default) doxygen will +# base this on the number of processors available in the system. You can set it +# explicitly to a value larger than 0 to get control over the balance +# between CPU load and processing speed. + +DOT_NUM_THREADS = 0 + +# By default doxygen will use the Helvetica font for all dot files that +# doxygen generates. When you want a differently looking font you can specify +# the font name using DOT_FONTNAME. You need to make sure dot is able to find +# the font, which can be done by putting it in a standard location or by setting +# the DOTFONTPATH environment variable or by setting DOT_FONTPATH to the +# directory containing the font. -DOT_FONTNAME = FreeSans +DOT_FONTNAME = # The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. # The default size is 10pt. DOT_FONTSIZE = 10 -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. +# By default doxygen will tell dot to use the Helvetica font. +# If you specify a different font using DOT_FONTNAME you can use DOT_FONTPATH to +# set the path where dot can find it. DOT_FONTPATH = # If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen # will generate a graph for each documented class showing the direct and # indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. +# CLASS_DIAGRAMS tag to NO. CLASS_GRAPH = YES @@ -1402,6 +1752,15 @@ GROUP_GRAPHS = YES UML_LOOK = NO +# If the UML_LOOK tag is enabled, the fields and methods are shown inside +# the class node. If there are many fields or methods and many nodes the +# graph may become too big to be useful. The UML_LIMIT_NUM_FIELDS +# threshold limits the number of items for each type to make the size more +# manageable. Set this to 0 for no limit. Note that the threshold may be +# exceeded by 50% before the limit is enforced. + +UML_LIMIT_NUM_FIELDS = 10 + # If set to YES, the inheritance and collaboration graphs will show the # relations between templates and their instances. @@ -1438,11 +1797,11 @@ CALL_GRAPH = NO CALLER_GRAPH = NO # If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. +# will generate a graphical hierarchy of all classes instead of a textual one. GRAPHICAL_HIERARCHY = YES -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES +# If the DIRECTORY_GRAPH and HAVE_DOT tags are set to YES # then doxygen will show the dependencies a directory has on other directories # in a graphical way. The dependency relations are determined by the #include # relations between the files in the directories. @@ -1450,11 +1809,22 @@ GRAPHICAL_HIERARCHY = YES DIRECTORY_GRAPH = YES # The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. +# generated by dot. Possible values are svg, png, jpg, or gif. +# If left blank png will be used. If you choose svg you need to set +# HTML_FILE_EXTENSION to xhtml in order to make the SVG files +# visible in IE 9+ (other browsers do not have this requirement). DOT_IMAGE_FORMAT = png +# If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to +# enable generation of interactive SVG images that allow zooming and panning. +# Note that this requires a modern browser other than Internet Explorer. +# Tested and working are Firefox, Chrome, Safari, and Opera. For IE 9+ you +# need to set HTML_FILE_EXTENSION to xhtml in order to make the SVG files +# visible. Older versions of IE do not have SVG support. + +INTERACTIVE_SVG = NO + # The tag DOT_PATH can be used to specify the path where the dot tool can be # found. If left blank, it is assumed the dot tool can be found in the path. @@ -1466,6 +1836,12 @@ DOT_PATH = DOTFILE_DIRS = +# The MSCFILE_DIRS tag can be used to specify one or more directories that +# contain msc files that are included in the documentation (see the +# \mscfile command). + +MSCFILE_DIRS = + # The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of # nodes that will be shown in the graph. If the number of nodes in a graph # becomes larger than this value, doxygen will truncate the graph, which is diff --git a/host/docs/Ettus_Logo.png b/host/docs/Ettus_Logo.png Binary files differnew file mode 100644 index 000000000..89587ab9a --- /dev/null +++ b/host/docs/Ettus_Logo.png diff --git a/host/docs/build.dox b/host/docs/build.dox new file mode 100644 index 000000000..1584a7b58 --- /dev/null +++ b/host/docs/build.dox @@ -0,0 +1,186 @@ +/*! \page page_build_guide Building and Installing UHD + +\tableofcontents + +\section build_dependencies Build Dependencies + +<b>Linux Notes:</b> +This is dependent on the distribution you are using, but most, if not all, of +the dependencies should be available in the package repositories for your +package manager. + +<b>Mac OS X Notes:</b> +Install the Xcode app to get the build tools (GCC and Make). +Use MacPorts to get the Boost and Cheetah dependencies. +Other dependencies can be downloaded as DMG installers from the web +or installed via MacPorts. +See the UHD OS X page for more information: http://code.ettus.com/redmine/ettus/projects/uhd/wiki/UHD_OS_X + +<b>Windows Notes:</b> +The dependencies can be acquired through installable EXE files. +Usually, the Windows installer can be found on the project's website. +Some projects do not host Windows installers, and if this is the case, +follow the auxiliary download URL for the Windows installer (below). + +\section git Git +Required to check out the repository. +On Windows, install Cygwin with Git support to checkout the repository +or install msysGit from http://code.google.com/p/msysgit/downloads/list. + +\section cpp_compiler C++ Compiler + +The following compilers are known to work: + +- GCC +- Clang +- MSVC + +### CMake + +- **Purpose:** generates project build files +- **Minimum Version:** 2.6 +- **Usage:** build time (required) +- **Download URL:** http://www.cmake.org/cmake/resources/software.html + +### Boost + +- **Purpose:** C++ library +- **Minimum Version:** 1.36 (Linux), 1.40 (Windows) +- **Usage:** build time + runtime (required) +- **Download URL:** http://www.boost.org/users/download/ +- **Download URL (Windows installer):** http://www.boostpro.com/download + +### LibUSB + +- **Purpose:** USB-based hardware support +- **Minimum Version:** 1.0 +- **Usage:** build time + runtime (optional) +- **Download URL:** http://sourceforge.net/projects/libusb/files/libusb-1.0/ +- **Download URL (Windows):** https://github.com/libusbx/libusbx + +### Python + +- **Purpose:** used by Cheetah and utility scripts +- **Minimum Version:** 2.6 +- **Usage:** build time + runtime utility scripts (required) +- **Download URL:** http://www.python.org/download/ + +### Cheetah + +- **Purpose:** source code generation +- **Minimum Version:** 2.0 +- **Usage:** build time (required) +- **Download URL:** http://www.cheetahtemplate.org/download.html +- **Download URL (Windows installer):** http://feisley.com/python/cheetah/ + +**Alternative method:** +Install **setuptools**, and use the **easy_install** command to install Cheetah. +http://pypi.python.org/pypi/setuptools + +### Doxygen + +- **Purpose:** generates HTML API documentation +- **Usage:** build time (optional) +- **Download URL:** http://www.stack.nl/~dimitri/doxygen/download.html#latestsrc + +**Alternate method:** +Install **setuptools**, and use the **easy_install** command to install Docutils. +http://pypi.python.org/pypi/setuptools + +\section build_instructions_unix Build Instructions (Unix) + +\subsection generate_unix Generate Makefiles with CMake + + cd <uhd-repo-path>/host + mkdir build + cd build + cmake ../ + +Additionally, configuration variables can be passed into CMake via the command line. +The following common-use configuration variables are listed below: + +- For a custom install prefix: `-DCMAKE_INSTALL_PREFIX=<install-path>` +- To install libs into lib64: `cmake -DLIB_SUFFIX=64` + +Example usage: + + cmake -DCMAKE_INSTALL_PREFIX=/opt/uhd ../ + +\subsection build_install_unix Build and install + + make + make test + sudo make install + +\subsection libpath_linux Setup the library path (Linux) + +Make sure that `libuhd.so` is in your `LD_LIBRARY_PATH`, +or add it to `/etc/ld.so.conf` and make sure to run: + + sudo ldconfig + +\section build_instructions_windows Build Instructions (Windows) + +\subsection cmake_win Generate the project with CMake + +- Open the CMake GUI. +- Set the path to the source code: `<uhd-repo-path>/host`. +- Set the path to the build directory: `<uhd-repo-path>/host/build`. +- Make sure that the paths do not contain spaces. +- Click "Configure" and select "Microsoft Visual Studio 10". +- Set the build variables and click "Configure" again. +- Click "Generate", and a project file will be created in the build directory. + +\subsection libusb_notes LibUSB notes + +On Windows, CMake does not have the advantage of `pkg-config`, +so we must manually tell CMake how to locate the LibUSB header and lib. + +- From the CMake GUI, select "Advanced View". +- Set `LIBUSB_INCLUDE_DIRS` to the directory with `libusb.h`. +- Set `LIBUSB_LIBRARIES` to the full path for `libusb-1.0.lib`. +- Recommend the static `libusb-1.0.lib` to simplify runtime dependencies. +- Check the box to enable USB support, click "Configure" and "Generate". + +<b>Note:</b> On Windows, LibUSBx is required to use most USB3 controllers. + +\subsection build_in_msvc Build the project in MSVC +- Open the generated project file in MSVC. +- Change the build type from "Debug" to "Release". +- Select the "Build All" target, right-click, and choose "Build". +- Select the install target, right-click, and choose "Build". + +<b>Note:</b> +You may not have permission to build the install target. +You need to be an administrator or to run MSVC as administrator. + +\section build_msvc_cmd_line Build the project in MSVC (command line) +Open the Visual Studio Command Prompt Shorcut: + + cd <uhd-repo-path>\host\build + DevEnv uhd.sln /build Release /project ALL_BUILD + DevEnv uhd.sln /build Release /project INSTALL + +\subsection path_env Setup the PATH environment variable +* Add the UHD bin path to `%PATH%` (usually `C:\\Program Files\\UHD\\bin`) + +<b>Note:</b> +The default interface for editing environment variable paths in Windows is very poor. +We recommend using "Rapid Environment Editor" (http://www.rapidee.com) over the default editor. + +\section post_install_tasks Post-Install Tasks + +For USB-based devices, +see the `USB Transport Application Notes <./transport.html#usb-transport-libusb>`_ +for platform-specific post-installation tasks. + +\section post_install_tasks_macosx Post-Install Tasks (Mac OS X) + +Make sure that the value of `CMAKE_INSTALL_PREFIX` is at or near the +front of the shell `PATH` environment variable. Do \b NOT set +`DYLD_LIBRARY_PATH` or any related DYLD environment variable +permanently; these work differently than under Linux and should be +used for testing / temporary purposes only. + +*/ +// vim:ft=doxygen: diff --git a/host/docs/build.rst b/host/docs/build.rst deleted file mode 100644 index f53a56d9b..000000000 --- a/host/docs/build.rst +++ /dev/null @@ -1,228 +0,0 @@ -======================================================================== -UHD Software - Build Guide -======================================================================== - -.. contents:: Table of Contents - ------------------------------------------------------------------------- -Build Dependencies ------------------------------------------------------------------------- - -**Linux Notes:** -This is dependent on the distribution you are using, but most, if not all, of -the dependencies should be available in the package repositories for your -package manager. - -**Mac OS X Notes:** -Install the Xcode app to get the build tools (GCC and Make). -Use MacPorts to get the Boost and Cheetah dependencies. -Other dependencies can be downloaded as DMG installers from the web -or installed via MacPorts. -See the UHD OS X page for more information: http://code.ettus.com/redmine/ettus/projects/uhd/wiki/UHD_OS_X - -**Windows Notes:** -The dependencies can be acquired through installable EXE files. -Usually, the Windows installer can be found on the project's website. -Some projects do not host Windows installers, and if this is the case, -follow the auxiliary download URL for the Windows installer (below). - -^^^^^^^^^^^^^^^^ -Git -^^^^^^^^^^^^^^^^ -Required to check out the repository. -On Windows, install Cygwin with Git support to checkout the repository -or install msysGit from http://code.google.com/p/msysgit/downloads/list. - -^^^^^^^^^^^^^^^^ -C++ Compiler -^^^^^^^^^^^^^^^^ -The following compilers are known to work: - -* GCC -* Clang -* MSVC - -^^^^^^^^^^^^^^^^ -CMake -^^^^^^^^^^^^^^^^ -* **Purpose:** generates project build files -* **Minimum Version:** 2.6 -* **Usage:** build time (required) -* **Download URL:** http://www.cmake.org/cmake/resources/software.html - -^^^^^^^^^^^^^^^^ -Boost -^^^^^^^^^^^^^^^^ -* **Purpose:** C++ library -* **Minimum Version:** 1.36 (Linux), 1.40 (Windows) -* **Usage:** build time + runtime (required) -* **Download URL:** http://www.boost.org/users/download/ -* **Download URL (Windows installer):** http://www.boostpro.com/download - -^^^^^^^^^^^^^^^^ -LibUSB -^^^^^^^^^^^^^^^^ -* **Purpose:** USB-based hardware support -* **Minimum Version:** 1.0 -* **Usage:** build time + runtime (optional) -* **Download URL:** http://sourceforge.net/projects/libusb/files/libusb-1.0/ -* **Download URL (Windows):** https://github.com/libusbx/libusbx - -^^^^^^^^^^^^^^^^ -Python -^^^^^^^^^^^^^^^^ -* **Purpose:** used by Cheetah and utility scripts -* **Minimum Version:** 2.6 -* **Usage:** build time + runtime utility scripts (required) -* **Download URL:** http://www.python.org/download/ - -^^^^^^^^^^^^^^^^ -Cheetah -^^^^^^^^^^^^^^^^ -* **Purpose:** source code generation -* **Minimum Version:** 2.0 -* **Usage:** build time (required) -* **Download URL:** http://www.cheetahtemplate.org/download.html -* **Download URL (Windows installer):** http://feisley.com/python/cheetah/ - -**Alternative method:** -Install **setuptools**, and use the **easy_install** command to install Cheetah. -http://pypi.python.org/pypi/setuptools - -^^^^^^^^^^^^^^^^ -Doxygen -^^^^^^^^^^^^^^^^ -* **Purpose:** generates HTML API documentation -* **Usage:** build time (optional) -* **Download URL:** http://www.stack.nl/~dimitri/doxygen/download.html#latestsrc - -^^^^^^^^^^^^^^^^ -Docutils -^^^^^^^^^^^^^^^^ -* **Purpose:** generates HTML user manual -* **Usage:** build time (optional) -* **Download URL:** http://docutils.sourceforge.net/ - -**Alternate method:** -Install **setuptools**, and use the **easy_install** command to install Docutils. -http://pypi.python.org/pypi/setuptools - ------------------------------------------------------------------------- -Build Instructions (Unix) ------------------------------------------------------------------------- - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Generate Makefiles with CMake -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -:: - - cd <uhd-repo-path>/host - mkdir build - cd build - cmake ../ - -Additionally, configuration variables can be passed into CMake via the command line. -The following common-use configuration variables are listed below: - -* For a custom install prefix: **-DCMAKE_INSTALL_PREFIX=<install-path>** -* To install libs into lib64: **cmake -DLIB_SUFFIX=64** - -Example usage: -:: - - cmake -DCMAKE_INSTALL_PREFIX=/opt/uhd ../ - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Build and install -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -:: - - make - make test - sudo make install - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Setup the library path (Linux) -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Make sure that **libuhd.so** is in your **LD_LIBRARY_PATH**, -or add it to **/etc/ld.so.conf** and make sure to run: -:: - - sudo ldconfig - ------------------------------------------------------------------------- -Build Instructions (Windows) ------------------------------------------------------------------------- - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Generate the project with CMake -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -* Open the CMake GUI. -* Set the path to the source code: **<uhd-repo-path>/host**. -* Set the path to the build directory: **<uhd-repo-path>/host/build**. -* Make sure that the paths do not contain spaces. -* Click "Configure" and select "Microsoft Visual Studio 10". -* Set the build variables and click "Configure" again. -* Click "Generate", and a project file will be created in the build directory. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -LibUSB notes -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -On Windows, CMake does not have the advantage of **pkg-config**, -so we must manually tell CMake how to locate the LibUSB header and lib. - -* From the CMake GUI, select "Advanced View". -* Set **LIBUSB_INCLUDE_DIRS** to the directory with **libusb.h**. -* Set **LIBUSB_LIBRARIES** to the full path for **libusb-1.0.lib**. - - * Recommend the static **libusb-1.0.lib** to simplify runtime dependencies. - -* Check the box to enable USB support, click "Configure" and "Generate". - -**Note:** On Windows, LibUSBx is required to use most USB3 controllers. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Build the project in MSVC -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -* Open the generated project file in MSVC. -* Change the build type from "Debug" to "Release". -* Select the "Build All" target, right-click, and choose "Build". -* Select the install target, right-click, and choose "Build". - -**Note:** You may not have permission to build the install target. -You need to be an administrator or to run MSVC as administrator. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Build the project in MSVC (command line) -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Open the Visual Studio Command Prompt Shorcut: -:: - - cd <uhd-repo-path>\host\build - DevEnv uhd.sln /build Release /project ALL_BUILD - DevEnv uhd.sln /build Release /project INSTALL - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Setup the PATH environment variable -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -* Add the UHD bin path to **%PATH%** (usually **C:\\Program Files\\UHD\\bin**) - -**Note:** -The default interface for editing environment variable paths in Windows is very poor. -We recommend using "Rapid Environment Editor" (http://www.rapidee.com) over the default editor. - ------------------------------------------------------------------------- -Post-Install Tasks ------------------------------------------------------------------------- -For USB-based devices, -see the `USB Transport Application Notes <./transport.html#usb-transport-libusb>`_ -for platform-specific post-installation tasks. - ------------------------------------------------------------------------- -Post-Install Tasks (Mac OS X) ------------------------------------------------------------------------- -Make sure that the value of **CMAKE_INSTALL_PREFIX** is at or near the -front of the shell **PATH** environment variable. Do **NOT** set -DYLD_LIBRARY_PATH or any related DYLD environment variable -permanently; these work differently than under Linux and should be -used for testing / temporary purposes only. diff --git a/host/docs/calibration.dox b/host/docs/calibration.dox new file mode 100644 index 000000000..494cfca49 --- /dev/null +++ b/host/docs/calibration.dox @@ -0,0 +1,70 @@ +/*! \page page_calibration Calibration Application Notes + +\tableofcontents + +\section calibration_self Self-Calibration + +UHD software comes with several self-calibration utilities for +minimizing IQ imbalance and DC offset. These utilities perform +calibration sweeps using transmit leakage into the receive path (special +equipment is not required). The results from a calibration are written +to a CSV file in the user's home directory. UHD software will +automatically apply corrections at runtime when the user re-tunes the +daughterboard LO. Calibration results are specific to an individual RF +board. + +<b>Note:</b> When a calibration table is present, and the user wishes to +override the calibration settings through the API: the user should +re-apply the desired setting every time the LO is re-tuned. + +UHD software comes with the following calibration utilities: + +- **uhd_cal_rx_iq_balance:** - mimimizes RX IQ imbalance vs. LO + frequency +- **uhd_cal_tx_dc_offset:** - mimimizes TX DC offset vs. LO + frequency +- **uhd_cal_tx_iq_balance:** - mimimizes TX IQ imbalance vs. LO + frequency + +The following RF frontends are supported by the self-calibration +utilities: + +- RFX Series transceiver boards +- WBX Series transceiver boards +- SBX Series transceiver boards +- CBX Series transceiver boards + +\subsection calibration_self_utils Calibration Utilities + +UHD software installs the calibration utilities into +`<install-path>/bin`. **Disconnect** any external hardware from the +RF antenna ports, and run the following from the command line. Each +utility will take several minutes to complete. : + + uhd_cal_rx_iq_balance --verbose --args=<optional device args> + uhd_cal_tx_iq_balance --verbose --args=<optional device args> + uhd_cal_tx_dc_offset --verbose --args=<optional device args> + +See the output given by --help for more advanced options, such as: +manually choosing the frequency range and step size for the sweeps. + +<b>Note:</b> Your daughterboard needs a serial number to run a calibration +utility. Some older daughterboards may not have a serial number. If this +is the case, run the following command to burn a serial number into the +daughterboard's EEPROM: : + + <install dir>/lib/uhd/utils/usrp_burn_db_eeprom --ser=<desired serial> --args=<optional device args> + +\subsection calibration_ Calibration Data + +Calibration files are stored in the user's home/application directory. +They can easily be moved from machine to another by copying the "cal" +directory. Re-running a calibration utility will replace the existing +calibration file. The old calibration file will be renamed so it may be +recovered by the user. + +- **Linux:** `${HOME}/.uhd/cal/` +- **Windows:** `%APPDATA%\.uhd\cal\` + +*/ +// vim:ft=doxygen: diff --git a/host/docs/calibration.rst b/host/docs/calibration.rst deleted file mode 100644 index 23bef01b7..000000000 --- a/host/docs/calibration.rst +++ /dev/null @@ -1,70 +0,0 @@ -======================================================================== -UHD - Calibration Application Notes -======================================================================== - -.. contents:: Table of Contents - ------------------------------------------------------------------------- -Self-Calibration ------------------------------------------------------------------------- -UHD software comes with several self-calibration utilities for minimizing IQ -imbalance and DC offset. These utilities perform calibration sweeps using -transmit leakage into the receive path (special equipment is not required). -The results from a calibration are written to a CSV file in the user's home -directory. UHD software will automatically apply corrections at runtime when -the user re-tunes the daughterboard LO. Calibration results are specific to an -individual RF board. - -**Note:** -When a calibration table is present, -and the user wishes to override the calibration settings through the API: -the user should re-apply the desired setting every time the LO is re-tuned. - -UHD software comes with the following calibration utilities: - - * **uhd_cal_rx_iq_balance:** - mimimizes RX IQ imbalance vs. LO frequency - * **uhd_cal_tx_dc_offset:** - mimimizes TX DC offset vs. LO frequency - * **uhd_cal_tx_iq_balance:** - mimimizes TX IQ imbalance vs. LO frequency - -The following RF frontends are supported by the self-calibration utilities: - - * RFX Series transceiver boards - * WBX Series transceiver boards - * SBX Series transceiver boards - * CBX Series transceiver boards - -******************************************** -Calibration Utilities -******************************************** -UHD software installs the calibration utilities into **<install-path>/bin**. -**Disconnect** any external hardware from the RF antenna ports, -and run the following from the command line. -Each utility will take several minutes to complete. -:: - - uhd_cal_rx_iq_balance --verbose --args=<optional device args> - uhd_cal_tx_iq_balance --verbose --args=<optional device args> - uhd_cal_tx_dc_offset --verbose --args=<optional device args> - -See the output given by --help for more advanced options, such as: -manually choosing the frequency range and step size for the sweeps. - -**Note:** -Your daughterboard needs a serial number to run a calibration utility. Some older daughterboards -may not have a serial number. If this is the case, run the following command to burn a serial number -into the daughterboard's EEPROM: -:: - - <install dir>/lib/uhd/utils/usrp_burn_db_eeprom --ser=<desired serial> --args=<optional device args> - -******************************************** -Calibration Data -******************************************** -Calibration files are stored in the user's home/application directory. -They can easily be moved from machine to another by copying the "cal" directory. -Re-running a calibration utility will replace the existing calibration file. -The old calibration file will be renamed so it may be recovered by the user. - - * **Linux:** ${HOME}/.uhd/cal/ - * **Windows:** %APPDATA%\\.uhd\\cal\\ - diff --git a/host/docs/coding.dox b/host/docs/coding.dox new file mode 100644 index 000000000..32dbe944a --- /dev/null +++ b/host/docs/coding.dox @@ -0,0 +1,38 @@ +/*! \page page_coding Coding to the API + +\tableofcontents + +\section coding_api Various API interfaces + +\subsection coding_api_hilevel High-Level: The Multi-USRP + +The Multi-USRP class provides a high-level interface to a single USRP device +with one or more channels, or multiple USRP devicess in a homogeneous +setup. See the documentation for uhd::usrp::multi_usrp. + +\subsection coding_api_hilevelclock High-Level: The Multi-USRP-Clock + +The Multi-USRP-Clock class provides a high-level interface to a single clock +device or set of clock devices, from which the time can be queried. See the +documentation for uhd::usrp_clock::multi_usrp_clock. + +\subsection coding_api_lowlevel Low-Level: The device API + +A device is an abstraction for hardware that is connected to the host +system. For a USRP device, this means that the motherboard and +everything on it would be considered to be a "device". For a clock device, the +device itself would be considered a "device" in software. The device API +provides ways to: + +- Discover devices that are physically connected to the host system. +- Create a device object for a particular device identified by + address. +- Register a device driver into the discovery and factory sub-system. +- Streaming samples with metadata into and out of the device. +- Set and get properties on the device object. +- Access various sensors on the device. + +See the documentation for uhd::device. + +*/ +// vim:ft=doxygen: diff --git a/host/docs/coding.rst b/host/docs/coding.rst deleted file mode 100644 index 432307cca..000000000 --- a/host/docs/coding.rst +++ /dev/null @@ -1,30 +0,0 @@ -======================================================================== -UHD - Coding to the API -======================================================================== - -.. contents:: Table of Contents - ------------------------------------------------------------------------- -Various API interfaces ------------------------------------------------------------------------- -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Low-Level: The device API -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -A device is an abstraction for hardware that is connected to the host system. -For a USRP device, this means that the motherboard and everything on it would be -considered to be a "device". The device API provides ways to: - -* Discover devices that are physically connected to the host system. -* Create a device object for a particular device identified by address. -* Register a device driver into the discovery and factory sub-system. -* Streaming samples with metadata into and out of the device. -* Set and get properties on the device object. - -See the documentation in *device.hpp* for reference. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -High-Level: The Multi-USRP -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The Multi-USRP class provides a fat interface to a single USRP device with -one or more channels, or multiple USRP devicess in a homogeneous setup. -See the documentation in *usrp/multi_usrp.hpp* for reference. diff --git a/host/docs/dboards.dox b/host/docs/dboards.dox new file mode 100644 index 000000000..b25656b5b --- /dev/null +++ b/host/docs/dboards.dox @@ -0,0 +1,405 @@ +/*! \page page_dboards Daughterboard Application Notes + +\tableofcontents + +\section dboards Daughterboard Properties + + +The following contains interesting notes about each daughterboard. +Eventually, this page will be expanded to list out the full properties +of each board as well. + +\subsection dboards_basicrx Basic RX and LFRX + +The Basic RX and LFRX boards have 4 frontends: + +- **Frontend A:** real signal on antenna RXA +- **Frontend B:** real signal on antenna RXB +- **Frontend AB:** quadrature frontend using both antennas (IQ) +- **Frontend BA:** quadrature frontend using both antennas (QI) + +The boards have no tunable elements or programmable gains. Through the +magic of aliasing, you can down-convert signals greater than the Nyquist +rate of the ADC. + +BasicRX Bandwidth: + +- **For Real-Mode (A or B frontend)**: 250 MHz +- **For Complex (AB or BA frontend)**: 500 MHz + +LFRX Bandwidth: + +- **For Real-Mode (A or B frontend)**: 33 MHz +- **For Complex (AB or BA frontend)**: 66 MHz + +\subsection dboards_basictx Basic TX and LFTX + +The Basic TX and LFTX boards have 4 frontends: + +- **Frontend A:** real signal on antenna TXA +- **Frontend B:** real signal on antenna TXB +- **Frontend AB:** quadrature frontend using both antennas (IQ) +- **Frontend BA:** quadrature frontend using both antennas (QI) + +The boards have no tunable elements or programmable gains. Through the +magic of aliasing, you can up-convert signals greater than the Nyquist +rate of the DAC. + +BasicTX Bandwidth: + +- **For Real-Mode (A or B frontend**): 250 MHz +- **For Complex (AB or BA frontend)**: 500 MHz + +LFTX Bandwidth: + +- **For Real-Mode (A or B frontend)**: 33 MHz +- **For Complex (AB or BA frontend)**: 66 MHz + +\subsection dboards_dbsrx DBSRX + +The DBSRX board has 1 quadrature frontend. It defaults to direct +conversion but can use a low IF through lo_offset in uhd::tune_request_t. + +Receive Antennas: **J3** + +- **Frontend 0:** Complex baseband signal from antenna J3 + +The board has no user selectable antenna setting. + +Receive Gains: + +- **GC1**, Range: 0-56dB +- **GC2**, Range: 0-24dB + +Bandwidth: 8 MHz - 66 MHz + +Sensors: + +- **lo_locked**: boolean for LO lock state + +\subsection dboards_dbsrx2 DBSRX2 + +The DBSRX2 board has 1 quadrature frontend. It defaults to direct +conversion, but can use a low IF through lo_offset in uhd::tune_request_t. + +Receive Antennas: **J3** + +- **Frontend 0:** Complex baseband signal from antenna J3 + +The board has no user-selectable antenna setting. + +Receive Gains: + +- **GC1**, Range: 0-73dB +- **BBG**, Range: 0-15dB + +Bandwidth (Hz): 8 MHz -80 MHz + +Sensors: + +- **lo_locked**: boolean for LO lock state + +\subsection dboards_rfx RFX Series + +The RFX Series boards have 2 quadrature frontends: Transmit and Receive. +Transmit defaults to low IF, and Receive defaults to direct conversion. +The IF can be adjusted through lo_offset in uhd::tune_request_t. + +The RFX Series boards have independent receive and transmit LO's and +synthesizers allowing full-duplex operation on different transmit and +receive frequencies. + +Transmit Antennas: **TX/RX** + +Receive Antennas: **TX/RX** or **RX2** + +- **Frontend 0:** Complex baseband signal for selected antenna + +The user may set the receive antenna to be TX/RX or RX2. However, when +using an RFX board in full-duplex mode, the receive antenna will always +be set to RX2, regardless of the settings. + +Receive Gains: **PGA0**, Range: 0-70dB (except RFX400 range is 0-45dB) + +Bandwidth: + +- **RX**: 40 MHz +- **TX**: 40 MHz + +Sensors: + +- **lo_locked**: boolean for LO lock state + +\subsection dboards_xcvr XCVR 2450 + +The XCVR2450 has 2 quadrature frontends, one transmit, one receive. +Transmit and Receive default to direct conversion but can be used in low +IF mode through lo_offset in uhd::tune_request_t. + +The XCVR2450 has a non-contiguous tuning range consisting of a high band +(4.9-6.0 GHz) and a low band (2.4-2.5 GHz). + +Transmit Antennas: **J1** or **J2** + +Receive Antennas: **J1** or **J2** + +- **Frontend 0:** Complex baseband signal for selected antenna + +The XCVR2450 uses a common LO for both receive and transmit. Even though +the API allows the RX and TX LOs to be individually set, a change of one +LO setting will be reflected in the other LO setting. + +The XCVR2450 does not support full-duplex mode, attempting to operate in +full-duplex will result in transmit-only operation. + +Transmit Gains: + +- **VGA**, Range: 0-30dB +- **BB**, Range: 0-5dB + +Receive Gains: + +- **LNA**, Range: 0-30.5dB +- **VGA**, Range: 0-62dB + +Bandwidths: + +- **RX**: 15 MHz, 19 MHz, 28 MHz, 36 MHz; (each +-0, 5, or 10%) +- **TX**: 24 MHz, 36 MHz, 48 MHz + +Sensors: + +- **lo_locked**: boolean for LO lock state +- **rssi**: float for rssi in dBm + +\subsection dboards_wbx WBX Series + +Features: + +- 2 quadrature frontends (1 transmit, 1 receive) + - Defaults to direct conversion + - Can be used in low IF mode through lo_offset with uhd::tune_request_t +- Independent recieve and transmit LO's and synthesizers + - Allows for full-duplex operation on different transmit and receive frequencies + - Can be set to use Integer-N tuning for better spur performance + with uhd::tune_request_t + +Transmit Antennas: **TX/RX** + +Receive Antennas: **TX/RX** or **RX2** + +- **Frontend 0:** Complex baseband signal for selected antenna + +- **Note:** The user may set the receive antenna to be TX/RX or RX2. + However, when using a WBX board in full-duplex mode, the receive + antenna will always be set to RX2, regardless of the settings. + +Transmit Gains: **PGA0**, Range: 0-25dB + +Receive Gains: **PGA0**, Range: 0-31.5dB + +Bandwidths: + +- **WBX**: 40 MHz, RX & TX +- **WBX-120**: 120 MHz, RX & TX + +Sensors: + +- **lo_locked**: boolean for LO lock state + +\subsection dboards_sbx SBX Series + +Features: + +- 2 quadrature frontends (1 transmit, 1 receive) + - Defaults to direct conversion + - Can be used in low IF mode through lo_offset with uhd::tune_request_t +- Independent recieve and transmit LO's and synthesizers + - Allows for full-duplex operation on different transmit and + receive frequencies + - Can be set to use Integer-N tuning for better spur performance with uhd::tune_request_t + +Transmit Antennas: **TX/RX** + +Receive Antennas: **TX/RX** or **RX2** + +- **Frontend 0:** Complex baseband signal for selected antenna + +- **Note:** The user may set the receive antenna to be TX/RX or RX2. + However, when using an SBX board in full-duplex mode, the receive + antenna will always be set to RX2, regardless of the settings. + +Transmit Gains: **PGA0**, Range: 0-31.5dB + +Receive Gains: **PGA0**, Range: 0-31.5dB + +Bandwidths: + +- **SBX**: 40 MHz, RX & TX +- **SBX-120**: 120 MHz, RX & TX + +Sensors: + +- **lo_locked**: boolean for LO lock state + +LEDs: + +- All LEDs flash when daughterboard control is initialized +- **TX LD**: Transmit Synthesizer Lock Detect +- **TX/RX**: Receiver on TX/RX antenna port (No TX) +- **RX LD**: Receive Synthesizer Lock Detect +- **RX1/RX2**: Receiver on RX2 antenna port + +\subsection dboards_cbx CBX Series + +Features: +- 2 quadrature frontends (1 transmit, 1 receive) + - Defaults to direct conversion + - Can be used in low IF mode through lo_offset with uhd::tune_request_t +- Independent recieve and transmit LO's and synthesizers + - Allows for full-duplex operation on different transmit and + receive frequencies + - Can be set to use Integer-N tuning for better spur performance with uhd::tune_request_t + +Transmit Antennas: **TX/RX** + +Receive Antennas: **TX/RX** or **RX2** + +- **Frontend 0:** Complex baseband signal for selected antenna + +- **Note:** The user may set the receive antenna to be TX/RX or RX2. + However, when using a CBX board in full-duplex mode, the receive + antenna will always be set to RX2, regardless of the settings. + +Transmit Gains: **PGA0**, Range: 0-31.5dB + +Receive Gains: **PGA0**, Range: 0-31.5dB + +Bandwidths: + +- **CBX**: 40 MHz, RX & TX +- **CBX-120**: 120 MHz, RX & TX + +Sensors: + +- **lo_locked**: boolean for LO lock state + +LEDs: + +- All LEDs flash when daughterboard control is initialized +- **TX LD**: Transmit Synthesizer Lock Detect +- **TX/RX**: Receiver on TX/RX antenna port (No TX) +- **RX LD**: Receive Synthesizer Lock Detect +- **RX1/RX2**: Receiver on RX2 antenna port + +\subsection dboards_tvrx TVRX + +The TVRX board has 1 real-mode frontend. It is operated at a low IF. + +Receive Antennas: RX + +- **Frontend 0:** real-mode baseband signal from antenna RX + +Receive Gains: + +- **RF**, Range: -13.3-50.3dB (frequency-dependent) +- **IF**, Range: -1.5-32.5dB + +Bandwidth: 6 MHz + +\subsection dboards_tvrx2 TVRX2 + +The TVRX2 board has 2 real-mode frontends. It is operated at a low IF. + +Receive Frontends: + +- **Frontend RX1:** real-mode baseband from antenna J100 +- **Frontend RX2:** real-mode baseband from antenna J140 + +Note: The TVRX2 has always-on AGC; the software controllable gain is the +final gain stage which controls the AGC set-point for output to ADC. + +Receive Gains: + +- **IF**, Range: 0.0-30.0dB + +Bandwidth: 1.7 MHz, 6 MHz, 7 MHz, 8 MHz, 10 MHz + +Sensors: + +- **lo_locked**: boolean for LO lock state +- **rssi**: float for measured RSSI in dBm +- **temperature**: float for measured temperature in degC + +\subsection dboards_dbsrxmod DBSRX - Modifying for other boards that USRP1 + +Due to different clocking capabilities, the DBSRX will require +modifications to operate on a non-USRP1 motherboard. On a USRP1 +motherboard, a divided clock is provided from an FPGA pin because the +standard daughterboard clock lines cannot provided a divided clock. +However, on other USRP motherboards, the divided clock is provided over +the standard daughterboard clock lines. + +\subsubsection dboards_dbsrxmod_1 Step 1: Move the clock configuration resistor + +Remove **R193** (which is 10 Ohms, 0603 size), and put it on **R194**, +which is empty. This is made somewhat more complicated by the fact that +the silkscreen is not clear in that area. **R193** is on the back, +immediately below the large beige connector, **J2**. **R194** is just +below, and to the left of **R193**. The silkscreen for **R193** is ok, +but for **R194**, it is upside down, and partially cut off. If you lose +**R193**, you can use anything from 0 to 10 Ohms there. + +\subsubsection dboards_dbsrxmod_1 Step 2: Burn a new daughterboard id into the EEPROM + +With the daughterboard plugged-in, run the following commands: + + cd <install-path>/lib/uhd/utils + ./usrp_burn_db_eeprom --id=0x000d --unit=RX --args=<args> --slot=<slot> + +- **\<args\>** are device address arguments (optional if only one USRP + device is on your machine) +- **\<slot\>** is the name of the daughterboard slot (optional if the + USRP device has only one slot) + +\subsection dboards_rfxmod RFX - Modify to use motherboard oscillator + +Older RFX boards require modifications to use the motherboard +oscillator. If this is the case, UHD software will print a warning about +the modification. Please follow the modification procedures below: + +- Step 1: Disable the daughterboard clocks** + +Move **R64** to **R84**. Move **R142** to **R153**. + +- Step 2: Connect the motherboard blocks + +Move **R35** to **R36**. Move **R117** to **R115**. These are all 0-Ohm, +so if you lose one, just short across the appropriate pads. + +- Step 3: Burn the appropriate daughterboard ID into the EEPROM + +With the daughterboard plugged in, run the following commands: : + + cd <install-path>/lib/uhd/utils + ./usrp_burn_db_eeprom --id=<rx_id> --unit=RX --args=<args> --slot=<slot> + ./usrp_burn_db_eeprom --id=<tx_id> --unit=TX --args=<args> --slot=<slot> + +- `<rx_id>` choose the appropriate RX ID for your daughterboard + - **RFX400:** 0x0024 + - **RFX900:** 0x0025 + - **RFX1800:** 0x0034 + - **RFX1200:** 0x0026 + - **RFX2400:** 0x0027 +- `<tx_id>` choose the appropriate TX ID for your daughterboard + - **RFX400:** 0x0028 + - **RFX900:** 0x0029 + - **RFX1800:** 0x0035 + - **RFX1200:** 0x002a + - **RFX2400:** 0x002b +- `<args>` are device address arguments (optional if only one USRP device is on your machine) +- `<slot>` is the name of the daughterboard slot (optional if the USRP device has only one slot) + + +*/ +// vim:ft=doxygen: diff --git a/host/docs/dboards.rst b/host/docs/dboards.rst deleted file mode 100644 index d6cbc6151..000000000 --- a/host/docs/dboards.rst +++ /dev/null @@ -1,425 +0,0 @@ -======================================================================== -UHD Daughterboard Application Notes -======================================================================== - -.. contents:: Table of Contents - ------------------------------------------------------------------------- -Daughterboard Properties ------------------------------------------------------------------------- - -The following contains interesting notes about each daughterboard. -Eventually, this page will be expanded to list out the full -properties of each board as well. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Basic RX and LFRX -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The Basic RX and LFRX boards have 4 frontends: - -* **Frontend A:** real signal on antenna RXA -* **Frontend B:** real signal on antenna RXB -* **Frontend AB:** quadrature frontend using both antennas (IQ) -* **Frontend BA:** quadrature frontend using both antennas (QI) - -The boards have no tunable elements or programmable gains. -Through the magic of aliasing, you can down-convert signals -greater than the Nyquist rate of the ADC. - -BasicRX Bandwidth: - -* **For Real-Mode (A or B frontend)**: 250 MHz -* **For Complex (AB or BA frontend)**: 500 MHz - -LFRX Bandwidth: - -* **For Real-Mode (A or B frontend)**: 33 MHz -* **For Complex (AB or BA frontend)**: 66 MHz - -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Basic TX and LFTX -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The Basic TX and LFTX boards have 4 frontends: - -* **Frontend A:** real signal on antenna TXA -* **Frontend B:** real signal on antenna TXB -* **Frontend AB:** quadrature frontend using both antennas (IQ) -* **Frontend BA:** quadrature frontend using both antennas (QI) - -The boards have no tunable elements or programmable gains. -Through the magic of aliasing, you can up-convert signals -greater than the Nyquist rate of the DAC. - -BasicTX Bandwidth (Hz): - -* **For Real-Mode (A or B frontend**): 250 MHz -* **For Complex (AB or BA frontend)**: 500 MHz - -LFTX Bandwidth (Hz): - -* **For Real-Mode (A or B frontend)**: 33 MHz -* **For Complex (AB or BA frontend)**: 66 MHz - -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -DBSRX -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The DBSRX board has 1 quadrature frontend. -It defaults to direct conversion but can use a low IF through lo_offset in **uhd::tune_request_t**. - -Receive Antennas: **J3** - -* **Frontend 0:** Complex baseband signal from antenna J3 - -The board has no user selectable antenna setting. - -Receive Gains: - -* **GC1**, Range: 0-56dB -* **GC2**, Range: 0-24dB - -Bandwidth: 8 MHz - 66 MHz - -Sensors: - -* **lo_locked**: boolean for LO lock state - -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -DBSRX2 -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The DBSRX2 board has 1 quadrature frontend. -It defaults to direct conversion, but can use a low IF through lo_offset in **uhd::tune_request_t**. - -Receive Antennas: **J3** - -* **Frontend 0:** Complex baseband signal from antenna J3 - -The board has no user-selectable antenna setting. - -Receive Gains: - -* **GC1**, Range: 0-73dB -* **BBG**, Range: 0-15dB - -Bandwidth (Hz): 8 MHz -80 MHz - -Sensors: - -* **lo_locked**: boolean for LO lock state - -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -RFX Series -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The RFX Series boards have 2 quadrature frontends: Transmit and Receive. -Transmit defaults to low IF, and Receive defaults to direct conversion. -The IF can be adjusted through lo_offset in **uhd::tune_request_t**. - -The RFX Series boards have independent receive and transmit LO's and synthesizers -allowing full-duplex operation on different transmit and receive frequencies. - -Transmit Antennas: **TX/RX** - -Receive Antennas: **TX/RX** or **RX2** - -* **Frontend 0:** Complex baseband signal for selected antenna - -The user may set the receive antenna to be TX/RX or RX2. -However, when using an RFX board in full-duplex mode, -the receive antenna will always be set to RX2, regardless of the settings. - -Receive Gains: **PGA0**, Range: 0-70dB (except RFX400 range is 0-45dB) - -Bandwidth: - -* **RX**: 40 MHz -* **TX**: 40 MHz - -Sensors: - -* **lo_locked**: boolean for LO lock state - -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -XCVR 2450 -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The XCVR2450 has 2 quadrature frontends, one transmit, one receive. -Transmit and Receive default to direct conversion but -can be used in low IF mode through lo_offset in uhd::tune_request_t. - -The XCVR2450 has a non-contiguous tuning range consisting of a -high band (4.9-6.0 GHz) and a low band (2.4-2.5 GHz). - -Transmit Antennas: **J1** or **J2** - -Receive Antennas: **J1** or **J2** - -* **Frontend 0:** Complex baseband signal for selected antenna - -The XCVR2450 uses a common LO for both receive and transmit. -Even though the API allows the RX and TX LOs to be individually set, -a change of one LO setting will be reflected in the other LO setting. - -The XCVR2450 does not support full-duplex mode, attempting to operate -in full-duplex will result in transmit-only operation. - -Transmit Gains: - -* **VGA**, Range: 0-30dB -* **BB**, Range: 0-5dB - -Receive Gains: - -* **LNA**, Range: 0-30.5dB -* **VGA**, Range: 0-62dB - -Bandwidths: - -* **RX**: 15 MHz, 19 MHz, 28 MHz, 36 MHz; (each +-0, 5, or 10%) -* **TX**: 24 MHz, 36 MHz, 48 MHz - -Sensors: - -* **lo_locked**: boolean for LO lock state -* **rssi**: float for rssi in dBm - -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -WBX Series -^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Features: - -* 2 quadrature frontends (1 transmit, 1 receive) - - * Defaults to direct conversion - * Can be used in low IF mode through lo_offset with **uhd::tune_request_t** - -* Independent recieve and transmit LO's and synthesizers - - * Allows for full-duplex operation on different transmit and receive frequencies - * Can be set to use Integer-N tuning for better spur performance with **uhd::tune_request_t** - -Transmit Antennas: **TX/RX** - -Receive Antennas: **TX/RX** or **RX2** - -* **Frontend 0:** Complex baseband signal for selected antenna - -* **Note:** The user may set the receive antenna to be TX/RX or RX2. However, when using a WBX board in full-duplex mode, the receive antenna will always be set to RX2, regardless of the settings. - -Transmit Gains: **PGA0**, Range: 0-25dB - -Receive Gains: **PGA0**, Range: 0-31.5dB - -Bandwidths: - -* **WBX**: 40 MHz, RX & TX -* **WBX-120**: 120 MHz, RX & TX - -Sensors: - -* **lo_locked**: boolean for LO lock state - -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -SBX Series -^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Features: - -* 2 quadrature frontends (1 transmit, 1 receive) - - * Defaults to direct conversion - * Can be used in low IF mode through lo_offset with **uhd::tune_request_t** - -* Independent recieve and transmit LO's and synthesizers - - * Allows for full-duplex operation on different transmit and receive frequencies - * Can be set to use Integer-N tuning for better spur performance with **uhd::tune_request_t** - -Transmit Antennas: **TX/RX** - -Receive Antennas: **TX/RX** or **RX2** - -* **Frontend 0:** Complex baseband signal for selected antenna - -* **Note:** The user may set the receive antenna to be TX/RX or RX2. However, when using an SBX board in full-duplex mode, the receive antenna will always be set to RX2, regardless of the settings. - -Transmit Gains: **PGA0**, Range: 0-31.5dB - -Receive Gains: **PGA0**, Range: 0-31.5dB - -Bandwidths: - -* **SBX**: 40 MHz, RX & TX -* **SBX-120**: 120 MHz, RX & TX - -Sensors: - -* **lo_locked**: boolean for LO lock state - -LEDs: - -* All LEDs flash when daughterboard control is initialized -* **TX LD**: Transmit Synthesizer Lock Detect -* **TX/RX**: Receiver on TX/RX antenna port (No TX) -* **RX LD**: Receive Synthesizer Lock Detect -* **RX1/RX2**: Receiver on RX2 antenna port - -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -CBX Series -^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Features: - -* 2 quadrature frontends (1 transmit, 1 receive) - - * Defaults to direct conversion - * Can be used in low IF mode through lo_offset with **uhd::tune_request_t** - -* Independent recieve and transmit LO's and synthesizers - - * Allows for full-duplex operation on different transmit and receive frequencies - * Can be set to use Integer-N tuning for better spur performance with **uhd::tune_request_t** - -Transmit Antennas: **TX/RX** - -Receive Antennas: **TX/RX** or **RX2** - -* **Frontend 0:** Complex baseband signal for selected antenna - -* **Note:** The user may set the receive antenna to be TX/RX or RX2. However, when using a CBX board in full-duplex mode, the receive antenna will always be set to RX2, regardless of the settings. - -Transmit Gains: **PGA0**, Range: 0-31.5dB - -Receive Gains: **PGA0**, Range: 0-31.5dB - -Bandwidths: - -* **CBX**: 40 MHz, RX & TX -* **CBX-120**: 120 MHz, RX & TX - -Sensors: - -* **lo_locked**: boolean for LO lock state - -LEDs: - -* All LEDs flash when daughterboard control is initialized -* **TX LD**: Transmit Synthesizer Lock Detect -* **TX/RX**: Receiver on TX/RX antenna port (No TX) -* **RX LD**: Receive Synthesizer Lock Detect -* **RX1/RX2**: Receiver on RX2 antenna port - -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -TVRX -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The TVRX board has 1 real-mode frontend. -It is operated at a low IF. - -Receive Antennas: RX - -* **Frontend 0:** real-mode baseband signal from antenna RX - -Receive Gains: - -* **RF**, Range: -13.3-50.3dB (frequency-dependent) -* **IF**, Range: -1.5-32.5dB - -Bandwidth: 6 MHz - -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -TVRX2 -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The TVRX2 board has 2 real-mode frontends. -It is operated at a low IF. - -Receive Frontends: - -* **Frontend RX1:** real-mode baseband from antenna J100 -* **Frontend RX2:** real-mode baseband from antenna J140 - -Note: The TVRX2 has always-on AGC; the software controllable gain is the -final gain stage which controls the AGC set-point for output to ADC. - -Receive Gains: - -* **IF**, Range: 0.0-30.0dB - -Bandwidth: 1.7 MHz, 6 MHz, 7 MHz, 8 MHz, 10 MHz - -Sensors: - -* **lo_locked**: boolean for LO lock state -* **rssi**: float for measured RSSI in dBm -* **temperature**: float for measured temperature in degC - -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -DBSRX - Mod -^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Due to different clocking capabilities, -the DBSRX will require modifications to operate on a non-USRP1 motherboard. -On a USRP1 motherboard, a divided clock is provided from an FPGA pin -because the standard daughterboard clock lines cannot provided a divided clock. -However, on other USRP motherboards, the divided clock is provided -over the standard daughterboard clock lines. - -**Step 1: Move the clock configuration resistor** - -Remove **R193** (which is 10 Ohms, 0603 size), and put it on **R194**, which is empty. -This is made somewhat more complicated by the fact that the silkscreen is not clear in that area. -**R193** is on the back, immediately below the large beige connector, **J2**. -**R194** is just below, and to the left of **R193**. -The silkscreen for **R193** is ok, but for **R194**, -it is upside down, and partially cut off. -If you lose **R193**, you can use anything from 0 to 10 Ohms there. - -**Step 2: Burn a new daughterboard id into the EEPROM** - -With the daughterboard plugged-in, run the following commands: -:: - - cd <install-path>/lib/uhd/utils - ./usrp_burn_db_eeprom --id=0x000d --unit=RX --args=<args> --slot=<slot> - -* **<args>** are device address arguments (optional if only one USRP device is on your machine) -* **<slot>** is the name of the daughterboard slot (optional if the USRP device has only one slot) - -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -RFX - Mod -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Older RFX boards require modifications to use the motherboard oscillator. -If this is the case, UHD software will print a warning about the modification. -Please follow the modification procedures below: - -**Step 1: Disable the daughterboard clocks** - -Move **R64** to **R84**. Move **R142** to **R153**. - -**Step 2: Connect the motherboard blocks** - -Move **R35** to **R36**. Move **R117** to **R115**. -These are all 0-Ohm, so if you lose one, just short across the appropriate pads. - -**Step 3: Burn the appropriate daughterboard ID into the EEPROM** - -With the daughterboard plugged-in, run the following commands: -:: - - cd <install-path>/lib/uhd/utils - ./usrp_burn_db_eeprom --id=<rx_id> --unit=RX --args=<args> --slot=<slot> - ./usrp_burn_db_eeprom --id=<tx_id> --unit=TX --args=<args> --slot=<slot> - -* **<rx_id>** choose the appropriate RX ID for your daughterboard - - * **RFX400:** 0x0024 - * **RFX900:** 0x0025 - * **RFX1800:** 0x0034 - * **RFX1200:** 0x0026 - * **RFX2400:** 0x0027 -* **<tx_id>** choose the appropriate TX ID for your daughterboard - - * **RFX400:** 0x0028 - * **RFX900:** 0x0029 - * **RFX1800:** 0x0035 - * **RFX1200:** 0x002a - * **RFX2400:** 0x002b -* **<args>** are device address arguments (optional if only one USRP device is on your machine) -* **<slot>** is the name of the daughterboard slot (optional if the USRP device has only one slot) diff --git a/host/docs/general.dox b/host/docs/general.dox new file mode 100644 index 000000000..3a344ffe7 --- /dev/null +++ b/host/docs/general.dox @@ -0,0 +1,225 @@ +/*! \page page_general General Application Notes + +\tableofcontents + +\section general_tuning Tuning Notes + +\subsection general_tuning_process Two-stage tuning process + +A USRP device has two stages of tuning: + +- RF front-end: translates bewteen RF and IF +- DSP: translates between IF and baseband + +In a typical use-case, the user specifies an overall center frequency +for the signal chain. The RF front-end will be tuned as close as +possible to the center frequency, and the DSP will account for the error +in tuning between target frequency and actual frequency. The user may +also explicitly control both stages of tuning through through the **tune_request_t** object, which allows for more advanced tuning. + +In general, Using UHD software's advanced tuning is highly recommended +as it makes it easy to move the DC component out of your +band-of-interest. This can be done by passing your desired LO offset to +the **tune_request_t** object, and letting the UHD software handle the +rest. + +The **tune_request_t** object can also be used with certain +daughterboards to use Integer-N tuning instead of the default fractional +tuning, allowing for better spur performance. The daughterboards that +support this functionality are: + +- WBX (all revisions) +- WBX-120 +- SBX (all revisions) +- SBX-120 +- CBX +- CBX-120 + +\subsubsection general_tuning_rxchain Tuning the receive chain: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} +//tuning to a desired center frequency +usrp->set_rx_freq(target_frequency_in_hz); + +--OR-- + +//advanced tuning with tune_request_t uhd::tune_request_t +tune_req(target_frequency_in_hz, desired_lo_offset); +tune_req.args = uhd::device_addr_t("mode_n=integer"); //to use Int-N tuning +//fill in any additional/optional tune request fields... +usrp->set_rx_freq(tune_req); +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +More information can be found in uhd::tune_request_t. + +\subsection general_tuning_rfsettling RF front-end settling time + +After tuning, the RF front-end will need time to settle into a usable +state. Typically, this means that the local oscillators must be given +time to lock before streaming begins. Lock time is not consistent; it +varies depending upon the device and requested settings. After tuning +and before streaming, the user should wait for the **lo_locked** sensor +to become true or sleep for a conservative amount of time (perhaps a +second). + +\subsubsection general_tuning_waitcode Pseudo-code for dealing with settling time after tuning on receive: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} + usrp->set_rx_freq(...); + sleep(1); + usrp->issue_stream_command(...); + + --OR-- + + usrp->set_rx_freq(...); + while (not usrp->get_rx_sensor("lo_locked").to_bool()){ + //sleep for a short time in milliseconds + } + usrp->issue_stream_command(...); +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +\section general_subdev Specifying the Subdevice to Use + +A subdevice specification string for USRP family devices is composed of: + + <motherboard slot name>:<daughterboard frontend name> + +Ex: The subdev spec markup string to select a WBX on slot B. + + B:0 + +Ex: The subdev spec markup string to select a BasicRX on slot B. + + B:AB + + -- OR -- + + B:A + + -- OR -- + + B:B + +\subsection general_subdev_slotnames USRP Family Motherboard Slot Names + +All USRP family motherboards have a first slot named **A:**. The USRP1 and the X3x0 +have two daughterboard subdevice slots, known as **A:** and **B:**. + +\subsection general_subdev_dbnames Daughterboard Frontend Names + +Daughterboard frontend names can be used to specify which signal path is +used from a daughterboard. Most daughterboards have only one frontend **:0**. +A few daughterboards (Basic, LF and TVRX2) have multiple +frontend names available. The frontend names are documented in \ref page_dboards. + +\section general_ounotes Overflow/Underflow Notes + +<b>Note:</b> The following overflow/underflow notes do not apply to USRP1, +which does not support the advanced features available in newer +products. + +\subsection general_ounotes_overflow Overflow notes + +When receiving, the device produces samples at a constant rate. +Overflows occurs when the host does not consume data fast enough. When +UHD software detects the overflow, it prints an "O" or "D" to stdout, +and pushes an inline message packet into the receive stream. + +<b>Network-based devices</b>: The host does not back-pressure the receive +stream. When the kernel's socket buffer becomes full, it will drop +subsequent packets. UHD software detects the overflow as a discontinuity +in the packet's sequence numbers, and pushes an inline message packet +into the receive stream. In this case the character "D" is printed to +stdout as an indication. + +<b>Other devices</b>: The host back-pressures the receive stream. +Therefore, overflows always occur in the device itself. When the +device's internal buffers become full, streaming is shut off, and an +inline message packet is sent to the host. In this case the character +"O" is printed to stdout as an indication. If the device was in +continuous streaming mode, the UHD software will automatically restart +streaming when the buffer has space again. + +\subsection general_ounotes_underrun Underrun notes + +When transmitting, the device consumes samples at a constant rate. +Underflow occurs when the host does not produce data fast enough. When +UHD software detects the underflow, it prints a "U" to stdout, and +pushes a message packet into the async message stream. + +<b>Note:</b> "O" and "U" message are generally harmless, and just mean the host machine can't keep up with the requested rates. + +\section general_threading Threading Notes + +\subsection general_threading_safety Thread safety notes + +For the most part, UHD software is thread-safe. Please observe the +following limitations: + +<b>Fast-path thread requirements:</b> There are three fast-path methods for +a device: `send()`, `recv()`, and `recv_async_msg()`. All three +methods are thread-safe and can be called from different thread +contexts. For performance, the user should call each method from a +separate thread context. These methods can also be used in a +non-blocking fashion by using a timeout of zero. + +<b>Slow-path thread requirements:</b> It is safe to change multiple +settings simultaneously. However, this could leave the settings for a +device in an uncertain state. This is because changing one setting could +have an impact on how a call affects other settings. Example: setting +the channel mapping affects how the antennas are set. It is recommended +to use at most one thread context for manipulating device settings. + +\subsection general_threading_prio Thread priority scheduling + +When UHD software spawns a new thread, it may try to boost the thread's +scheduling priority. If setting the new priority fails, the UHD software +prints a warning to the console, as shown below. This warning is harmless; +it simply means that the thread will retain a normal or default scheduling priority. + + UHD Warning: + Unable to set the thread priority. Performance may be negatively affected. + Please see the general application notes in the manual for instructions. + EnvironmentError: OSError: error in pthread_setschedparam + +<b>Linux Notes:</b> + +Non-privileged users need special permission to change the scheduling +priority. Add the following line to the file `/etc/security/limits.conf`: + + @GROUP - rtprio 99 + +Replace `GROUP` with a group in which your user is a member. You may need +to log out and log back into the account for the settings to take effect. +In most Linux distributions, a list of groups and group members can be found in the file `/etc/group`. + +\section general_misc Miscellaneous Notes + +\subsection general_misc_dynamic Support for dynamically loadable modules + +For a module to be loaded at runtime, it must be: + +- found in the `UHD_MODULE_PATH` environment variable, +- installed into the `\<install-path\>/share/uhd/modules` directory, +- or installed into `/usr/share/uhd/modules` directory (UNIX only). + +\subsection general_misc_prints Disabling or redirecting prints to stdout + +The user can disable the UHD library from printing directly to stdout by +registering a custom message handler. The handler will intercept all +messages, which can be dropped or redirected. Only one handler can be +registered at a time. Make **register_handler** your first call into +the UHD library: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} +#include <uhd/utils/msg.hpp> + +void my_handler(uhd::msg::type_t type, const std::string &msg){ +//handle the message... +} + +uhd::msg::register_handler(&my_handler); +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +*/ +// vim:ft=doxygen: diff --git a/host/docs/general.rst b/host/docs/general.rst deleted file mode 100644 index 930c18188..000000000 --- a/host/docs/general.rst +++ /dev/null @@ -1,242 +0,0 @@ -=============================== -UHD - General Application Notes -=============================== - -.. contents:: Table of Contents - ------------- -Tuning Notes ------------- - -^^^^^^^^^^^^^^^^^^^^^^^^ -Two-stage tuning process -^^^^^^^^^^^^^^^^^^^^^^^^ -A USRP device has two stages of tuning: - -* RF front-end: translates bewteen RF and IF -* DSP: translates between IF and baseband - -In a typical use-case, the user specifies an overall center frequency for the -signal chain. The RF front-end will be tuned as close as possible to the center -frequency, and the DSP will account for the error in tuning between target -frequency and actual frequency. The user may also explicitly control both -stages of tuning through through the **tune_request_t** object, which allows for -more advanced tuning. - -In general, Using UHD software's advanced tuning is highly recommended as it makes it -easy to move the DC component out of your band-of-interest. This can be done by -passing your desired LO offset to the **tune_request_t** object, and letting the UHD -software handle the rest. - -The **tune_request_t** object can also be used with certain daughterboards to use -Integer-N tuning instead of the default fractional tuning, allowing for better spur -performance. The daughterboards that support this functionality are: - -* WBX (all revisions) -* WBX-120 -* SBX (all revisions) -* SBX-120 -* CBX -* CBX-120 - -Tuning the receive chain: -::::::::::::::::::::::::: - - //tuning to a desired center frequency - usrp->set_rx_freq(target_frequency_in_hz); - - --OR-- - - //advanced tuning with tune_request_t - uhd::tune_request_t tune_req(target_frequency_in_hz, desired_lo_offset); - tune_req.args = uhd::device_addr_t("mode_n=integer"); //to use Int-N tuning - //fill in any additional/optional tune request fields... - usrp->set_rx_freq(tune_req); - -More information can be found in `tune_request.hpp <./../../doxygen/html/structuhd_1_1tune__request__t.html>`_. - -^^^^^^^^^^^^^^^^^^^^^^^^^^ -RF front-end settling time -^^^^^^^^^^^^^^^^^^^^^^^^^^ -After tuning, the RF front-end will need time to settle into a usable state. -Typically, this means that the local oscillators must be given time to lock -before streaming begins. Lock time is not consistent; it varies depending upon -the device and requested settings. After tuning and before streaming, the user -should wait for the **lo_locked** sensor to become true or sleep for -a conservative amount of time (perhaps a second). - -Pseudo-code for dealing with settling time after tuning on receive: -::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: - -:: - - usrp->set_rx_freq(...); - sleep(1); - usrp->issue_stream_command(...); - - --OR-- - - usrp->set_rx_freq(...); - while (not usrp->get_rx_sensor("lo_locked").to_bool()){ - //sleep for a short time in milliseconds - } - usrp->issue_stream_command(...); - - -------------------------------- -Specifying the Subdevice to Use -------------------------------- -A subdevice specification string for USRP family devices is composed of: - -:: - - <motherboard slot name>:<daughterboard frontend name> - -Ex: The subdev spec markup string to select a WBX on slot B. - -:: - - B:0 - -Ex: The subdev spec markup string to select a BasicRX on slot B. - -:: - - B:AB - - -- OR -- - - B:A - - -- OR -- - - B:B - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -USRP Family Motherboard Slot Names -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -All USRP family motherboards have a first slot named **A:**. The USRP1 has -two daughterboard subdevice slots, known as **A:** and **B:**. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Daughterboard Frontend Names -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Daughterboard frontend names can be used to specify which signal path is used -from a daughterboard. Most daughterboards have only one frontend **:0**. A few -daughterboards (Basic, LF and TVRX2) have multiple frontend names available. -The frontend names are documented in the -`Daughterboard Application Notes <./dboards.html>`_ - ------------------------- -Overflow/Underflow Notes ------------------------- -**Note:** The following overflow/underflow notes do not apply to USRP1, -which does not support the advanced features available in newer products. - -^^^^^^^^^^^^^^ -Overflow notes -^^^^^^^^^^^^^^ -When receiving, the device produces samples at a constant rate. -Overflows occurs when the host does not consume data fast enough. -When UHD software detects the overflow, it prints an "O" or "D" to stdout, -and pushes an inline message packet into the receive stream. - -**Network-based devices**: -The host does not back-pressure the receive stream. -When the kernel's socket buffer becomes full, it will drop subsequent packets. -UHD software detects the overflow as a discontinuity in the packet's sequence numbers, -and pushes an inline message packet into the receive stream. -In this case the character "D" is printed to stdout as an indication. - -**Other devices**: -The host back-pressures the receive stream. -Therefore, overflows always occur in the device itself. -When the device's internal buffers become full, streaming is shut off, -and an inline message packet is sent to the host. -In this case the character "O" is printed to stdout as an indication. -If the device was in continuous streaming mode, -the UHD software will automatically restart streaming when the buffer has -space again. - -^^^^^^^^^^^^^^^ -Underflow notes -^^^^^^^^^^^^^^^ -When transmitting, the device consumes samples at a constant rate. -Underflow occurs when the host does not produce data fast enough. -When UHD software detects the underflow, it prints a "U" to stdout, -and pushes a message packet into the async message stream. - ---------------- -Threading Notes ---------------- - -^^^^^^^^^^^^^^^^^^^ -Thread safety notes -^^^^^^^^^^^^^^^^^^^ -For the most part, UHD software is thread-safe. -Please observe the following limitations: - -**Fast-path thread requirements:** -There are three fast-path methods for a device: **send()**, **recv()**, and **recv_async_msg()**. -All three methods are thread-safe and can be called from different thread contexts. -For performance, the user should call each method from a separate thread context. -These methods can also be used in a non-blocking fashion by using a timeout of zero. - -**Slow-path thread requirements:** -It is safe to change multiple settings simultaneously. However, -this could leave the settings for a device in an uncertain state. -This is because changing one setting could have an impact on how a call affects other settings. -Example: setting the channel mapping affects how the antennas are set. -It is recommended to use at most one thread context for manipulating device settings. - -^^^^^^^^^^^^^^^^^^^^^^^^^^ -Thread priority scheduling -^^^^^^^^^^^^^^^^^^^^^^^^^^ - -When UHD software spawns a new thread it may try to boost the thread's scheduling priority. -When setting the priority fails, the UHD software prints out an error. -This error is harmless; it simply means that the thread will have a normal scheduling priority. - -**Linux Notes:** - -Non-privileged users need special permission to change the scheduling priority. -Add the following line to **/etc/security/limits.conf**: -:::::::::::::::::::::::::::::::::::::::::::::::::::::::: - - @<my_group> - rtprio 99 - -Replace **<my_group>** with a group to which your user belongs. -Settings will not take effect until the user is in a different login session. - -------------------- -Miscellaneous Notes -------------------- - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Support for dynamically loadable modules -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -For a module to be loaded at runtime, it must be: - -* found in the **UHD_MODULE_PATH** environment variable, -* installed into the **<install-path>/share/uhd/modules** directory, -* or installed into **/usr/share/uhd/modules** directory (UNIX only). - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Disabling or redirecting prints to stdout -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The user can disable the UHD library from printing directly to stdout by registering a custom message handler. -The handler will intercept all messages, which can be dropped or redirected. -Only one handler can be registered at a time. -Make **register_handler** your first call into the UHD library: - -:: - - #include <uhd/utils/msg.hpp> - - void my_handler(uhd::msg::type_t type, const std::string &msg){ - //handle the message... - } - - uhd::msg::register_handler(&my_handler); diff --git a/host/docs/gpio_api.dox b/host/docs/gpio_api.dox new file mode 100644 index 000000000..96d2a14be --- /dev/null +++ b/host/docs/gpio_api.dox @@ -0,0 +1,119 @@ +/*! \page page_gpio_api X3x0 GPIO API + +\tableofcontents + +\section xgpio_fpanel The X3x0 Front Panel GPIO + +The X3x0 is the first USRP device to offer an auxiliary GPIO connection +on the motherboard itself (independent of the daughterboards). These +GPIO pins are controlled directly by the FPGA, where they are controlled +by an ATR (Automatic Transmit / Receive). This allows them to be toggled +simultaneously with other radio-level changes (e.g., enabling or +disabling a TX or RX mixer). + +\subsection xgpio_fpanel_gpio Front Panel GPIO + +\subsubsection xgpio_fpanel_conn Connector + +\image html x3x0_gpio_conn.png "X3x0 GPIO Connectors" + +\subsubsection xgpio_fpanel_pins Pin Mapping + +- Pin 1: +3.3V +- Pin 2: Data[0] +- Pin 3: Data[1] +- Pin 4: Data[2] +- Pin 5: Data[3] +- Pin 6: Data[4] +- Pin 7: Data[5] +- Pin 8: Data[6] +- Pin 9: Data[7] +- Pin 10: Data[8] +- Pin 11: Data[9] +- Pin 12: Data[10] +- Pin 13: Data[11] +- Pin 14: 0V +- Pin 15: 0V + +\subsection xgpio_fpanel_atr Explaining ATR + +ATR works by defining the value of the GPIO pins for certain states of +the radio. This is the "automatic" part of it. For example, you can tell +UHD that when the radio is transmitting and receiving (full duplex), +GPIO6 should be high, but when it is only transmitting, GPI06 should be +low. This state machine is set up using a series of GPIO attributes, +with paired values and a mask, which you will want to define for the +GPIO pins you intend to use. To set up the ATR, you use uhd::usrp::multi_usrp::set_gpio_attr(). + +- **CTRL**: Is this pin controlled by ATR (automatic), or by manual + control only? +- **DDR**: "Data Direction Register" - defines whether or not a GPIO + is an output or an input. +- **OUT**: Manually set the value of a pin (only to be used in non-ATR + mode). +- **ATR_0X**: The status of the pins when the radio is **idle**. +- **ATR_RX**: The status of the pins when the radio is only + **receiving**. +- **ATR_TX**: The status of the pins when the radio is only + **transmitting**. +- **ATR_XX**: The status of the pins when the radio is in + **full-duplex** mode. + +The counterpart to setting the ATR (the "getter"), is called +uhd::usrp::multi_usrp::get_gpio_attr(). +t has the exact same attributes as above, and has +one more: + +- **READBACK**: Readback the GPIOs marked as inputs. + +\subsection xgpio_fpanel_xample An Example + +The front panel X3x0 GPIO bank is enumerated in the motherboard property +tree ('*<mb_path>/gpio/FP0/\*'), and so is easily accessible through +the standard uhd::usrp::multi_usrp UHD interface. + +You can discover this using the uhd::usrp::multi_usrp::get_gpio_banks() function. +This will tell you that there is a GPIO bank on your +X3x0 called "FP0". This is the bank we want to set-up. + +Let's say we want to use GPIO6 for an external amp. We want it to be +automatically controlled by ATR as an output, and we want it to be high +when we are transmitting, and low in all other cases. We are also using +GPIO4, which we want to control manually, as an output. We can set this +up with the following code: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} + // set up our masks, defining the pin numbers + #define AMP_GPIO_MASK (1 << 6) + #define MAN_GPIO_MASK (1 << 4) + + #define ATR_MASKS (AMP_GPIO_MASK | MAN_GPIO_MASK) + + // set up our values for ATR control: 1 for ATR, 0 for manual + #define ATR_CONTROL (AMP_GPIO_MASK & ~MAN_GPIO_MASK) + + // set up the GPIO directions: 1 for output, 0 for input + #define GPIO_DDR (AMP_GPIO_MASK & ~MAN_GPIO_MASK) + + // assume an existing USRP device handle, called "usrp_x300" + + // now, let's do the basic ATR setup + usrp_x300->set_gpio_attr("FP0", "CTRL", ATR_CONTROL, ATR_MASKS); + usrp_x300->set_gpio_attr("FP0", "DDR", GPIO_DDR, ATR_MASKS); + + // let's manually set GPIO4 high + usrp_x300->set_gpio_attr("FP0", "OUT", 1, MAN_GPIO_MASK); + + // finally, let's set up GPIO6 as we described above + usrp_x300->set_gpio_attr("FP0", "ATR_0X", 0, AMP_GPIO_MASK); + usrp_x300->set_gpio_attr("FP0", "ATR_RX", 0, AMP_GPIO_MASK); + usrp_x300->set_gpio_attr("FP0", "ATR_TX", 0, AMP_GPIO_MASK); + usrp_x300->set_gpio_attr("FP0", "ATR_XX", 0, AMP_GPIO_MASK); +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +After the above code is run, the ATR in the FPGA will automatically +control GPIO6, as we have described, based on the radio state, and we +have direct manual control over GPIO4. + +*/ +// vim:ft=doxygen: diff --git a/host/docs/gpio_api.rst b/host/docs/gpio_api.rst deleted file mode 100644 index 9fd86d081..000000000 --- a/host/docs/gpio_api.rst +++ /dev/null @@ -1,129 +0,0 @@ -======================================================================== -UHD - X3x0 GPIO API -======================================================================== - -.. contents:: Table of Contents - ------------------------------------------------------------------------- -The X3x0 Front Panel GPIO ------------------------------------------------------------------------- -The X3x0 is the first USRP device to offer an auxiliary GPIO connection on the -motherboard itself (independent of the daughterboards). These GPIO pins are -controlled directly by the FPGA, where they are controlled by an ATR (Automatic -Transmit / Receive). This allows them to be toggled simultaneously with other -radio-level changes (e.g., enabling or disabling a TX or RX mixer). - - -^^^^^^^^^^^^^^^^ -Front Panel GPIO -^^^^^^^^^^^^^^^^ - -Connector -::::::::: - -.. image:: ./res/x3x0_gpio_conn.png - :scale: 75% - :align: left - -Pin Mapping -::::::::::: - -* Pin 1: +3.3V -* Pin 2: Data[0] -* Pin 3: Data[1] -* Pin 4: Data[2] -* Pin 5: Data[3] -* Pin 6: Data[4] -* Pin 7: Data[5] -* Pin 8: Data[6] -* Pin 9: Data[7] -* Pin 10: Data[8] -* Pin 11: Data[9] -* Pin 12: Data[10] -* Pin 13: Data[11] -* Pin 14: 0V -* Pin 15: 0V - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Explaining ATR -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -ATR works by defining the value of the GPIO pins for certain states of the -radio. This is the "automatic" part of it. For example, you can tell UHD that -when the radio is transmitting and receiving (full duplex), GPIO6 should be -high, but when it is only transmitting, GPI06 should be low. This state machine -is set up using a series of GPIO attributes, with paired values and a mask, -which you will want to define for the GPIO pins you intend to use. To set up -the ATR, you use the **multi_usrp** function *set_gpio_attr*. - -* **CTRL**: Is this pin controlled by ATR (automatic), or by manual control - only? -* **DDR**: "Data Direction Register" - defines whether or not a GPIO is an - output or an input. -* **OUT**: Manually set the value of a pin (only to be used in non-ATR mode). -* **ATR_0X**: The status of the pins when the radio is **idle**. -* **ATR_RX**: The status of the pins when the radio is only **receiving**. -* **ATR_TX**: The status of the pins when the radio is only **transmitting**. -* **ATR_XX**: The status of the pins when the radio is in **full-duplex** mode. - -The counterpart to setting the ATR (the "getter"), is called *get_gpio_attr*. -It has the exact same attributes as above, and has one more: - -* **READBACK**: Readback the GPIOs marked as inputs. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -An Example -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The front panel X3x0 GPIO bank is enumerated in the motherboard property tree -("*<mb_path>/gpio/FP0/*"), and so is easily accessible through the standard -**multi_usrp** UHD interface. - -You can discover this using the *get_gpio_banks* function in **multi_usrp**. -This will tell you that there is a GPIO bank on your X3x0 called "FP0". This is -the bank we want to set-up. - -Let's say we want to use GPIO6 for an external amp. We want it to be -automatically controlled by ATR as an output, and we want it to be high when we -are transmitting, and low in all other cases. We are also using GPIO4, which -we want to control manually, as an output. We can set this up with the following -code: - -:: - - // set up our masks, defining the pin numbers - #define AMP_GPIO_MASK (1 << 6) - #define MAN_GPIO_MASK (1 << 4) - - #define ATR_MASKS (AMP_GPIO_MASK | MAN_GPIO_MASK) - - // set up our values for ATR control: 1 for ATR, 0 for manual - #define ATR_CONTROL (AMP_GPIO_MASK & ~MAN_GPIO_MASK) - - // set up the GPIO directions: 1 for output, 0 for input - #define GPIO_DDR (AMP_GPIO_MASK & ~MAN_GPIO_MASK) - - // assume an existing USRP device handle, called "usrp_x300" - - // now, let's do the basic ATR setup - usrp_x300->set_gpio_attr("FP0", "CTRL", ATR_CONTROL, ATR_MASKS); - usrp_x300->set_gpio_attr("FP0", "DDR", GPIO_DDR, ATR_MASKS); - - // let's manually set GPIO4 high - usrp_x300->set_gpio_attr("FP0", "OUT", 1, MAN_GPIO_MASK); - - // finally, let's set up GPIO6 as we described above - usrp_x300->set_gpio_attr("FP0", "ATR_0X", 0, AMP_GPIO_MASK); - usrp_x300->set_gpio_attr("FP0", "ATR_RX", 0, AMP_GPIO_MASK); - usrp_x300->set_gpio_attr("FP0", "ATR_TX", 0, AMP_GPIO_MASK); - usrp_x300->set_gpio_attr("FP0", "ATR_XX", 0, AMP_GPIO_MASK); - -After the above code is run, the ATR in the FPGA will automatically control -GPIO6, as we have described, based on the radio state, and we have direct -manual control over GPIO4. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Further Information -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -For more information, see the Doxygen API documentation: - -* `multi_usrp API <./../../doxygen/html/classuhd_1_1usrp_1_1multi__usrp.html>`_ diff --git a/host/docs/gpsdo.dox b/host/docs/gpsdo.dox new file mode 100644 index 000000000..397bde297 --- /dev/null +++ b/host/docs/gpsdo.dox @@ -0,0 +1,81 @@ +/*! \page page_gpsdo Internal GPSDO Application Notes (USRP-N2x0/E1X0 Models) + +\tableofcontents + +This application note describes the use of integrated GPS-disciplined +oscillators (GPSDOs) for the USRP N-Series and E1xx. For information +regarding the GPSDO that is compatible with the USRP X-Series, please +see: \ref page_gpsdo_x3x0 + + +\section gpsdo_specs Specifications + +- **Receiver type**: 50 channel with WAAS, EGNOS, MSAS +- **10MHz ADEV**: 1e-11 over \> 24h +- **1PPS RMS jitter**: \< 50ns 1-sigma +- **Holdover**: \< 11us over 3h +- **Phase noise**: + - **1Hz:** -80 dBc/Hz + - **10Hz:** -110 dBc/Hz + - **100Hz:** -135 dBc/Hz + - **1kHz:** -145 dBc/Hz + - **10kHz:** \< -145 dBc/Hz + +<b>Antenna Types:</b> + +The GPSDO is capable of supplying a 3V for active GPS antennas or +supporting passive antennas. + +\section gpsdo_install Installation Instructions + +Instructions for mounting the GPSDO kit onto your USRP device can be +found here: http://www.ettus.com/content/files/gpsdo-kit_2.pdf + +\subsection gspdo_install_post Post-installation Task (N-Series only) + +<b>Note:</b> The following instructions are only necessary for UHD 3.4.\* +and below. + +This is necessary if you require absolute GPS time in your application +or need to communicate with the GPSDO to obtain location, satellite +info, etc. If you only require 10 MHz and PPS signals for reference or +MIMO use (see \ref page_sync), it is not necessary to perform this step. + +To configure the USRP to communicate with the GPSDO, use the +`usrp_burn_mb_eeprom` utility: + + cd <install-path>/lib/uhd/utils + ./usrp_burn_mb_eeprom --args=<optional device args> --values="gpsdo=internal" + + -- restore original setting -- + ./usrp_burn_mb_eeprom --args=<optional device args> --values="gpsdo=internal" + +\section gpsdo_use Using the GPSDO in Your Application + +By default, if a GPSDO is detected at startup, the USRP will be +configured to use it as a frequency and time reference. The internal +VITA timestamp will be initialized to the GPS time, and the internal +oscillator will be phase-locked to the 10 MHz GPSDO reference. If the +GPSDO is not locked to satellites, the VITA time will not be +initialized. + +GPS data is obtained through the **mboard_sensors** interface. To +retrieve the current GPS time, use the **gps_time** sensor: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} + usrp->get_mboard_sensor("gps_time"); +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The returned value will be the current epoch time, in seconds since +January 1, 1970. This value is readily converted into human-readable +format using the **time.h** library in C, **boost::posix_time** in C++, +etc. + +Other information can be fetched as well. You can query the lock status +with the **gps_locked** sensor, as well as obtain raw NMEA sentences +using the **gps_gprmc**, and **gps_gpgga** sensors. Location +information can be parsed out of the **gps_gpgga** sensor by using **gpsd** +or another NMEA parser. + +*/ +// vim:ft=doxygen: diff --git a/host/docs/gpsdo.rst b/host/docs/gpsdo.rst index 8ffff8672..5afd9d78d 100644 --- a/host/docs/gpsdo.rst +++ b/host/docs/gpsdo.rst @@ -55,10 +55,10 @@ To configure the USRP to communicate with the GPSDO, use the :: cd <install-path>/lib/uhd/utils - ./usrp_burn_mb_eeprom --args=<optional device args> --key=gpsdo --val=internal + ./usrp_burn_mb_eeprom --args=<optional device args> --values="gpsdo=internal" -- restore original setting -- - ./usrp_burn_mb_eeprom --args=<optional device args> --key=gpsdo --val=none + ./usrp_burn_mb_eeprom --args=<optional device args> --values="gpsdo=none" ------------------------------------------------------------------------ Using the GPSDO in Your Application diff --git a/host/docs/gpsdo_b2x0.dox b/host/docs/gpsdo_b2x0.dox new file mode 100644 index 000000000..a54665427 --- /dev/null +++ b/host/docs/gpsdo_b2x0.dox @@ -0,0 +1,73 @@ +/*! \page page_gpsdo_b2x0 Internal GPSDO Application Notes (USRP-B2x0 Models) + +\tableofcontents + +This application note describes the use of integrated GPS-disciplined +oscillators with Ettus Research USRP devices. + +\section gpsdob_specs Specifications + +- **Receiver type**: 50 channel with WAAS, EGNOS, MSAS +- **10MHz ADEV**: 5e-11 over \>24h +- **1PPS RMS jitter**: \<50ns 1-sigma +- **Holdover**: \<20us over 3h + +<b>Phase noise</b>: + + Offset | Phase Noise Power +---------|------------------- + 1Hz | -65dBc/Hz + 10Hz | > -102dBc/Hz + 100Hz | -132dBc/Hz + 1kHz | -148dBc/Hz + 10kHz | -152dBc/Hz + 100kHz | \< -155dBc/Hz + +<b>Antenna Types:</b> + +The GPSDO is capable of supplying a 3V for active GPS antennas or +supporting passive antennas. + +\section gpsdob_install Installation Instructions + +To install the GPSDO, you must insert it into the slot on the board near +the 10 MHz Reference SMA. Keep in mind that the two sides of the GPSDO +have a different number of pins. When inserting the GPSDO, make sure to +press down firmly and evenly. When turning on the USRP B2X0 device, a +green LED should illuminate on the GPSDO. This signifies that the unit +has successfully been placed. + +<b>NOTE: The pins on the GPSDO are very fragile. Be sure to press down +evenly, or the pins may bend or break. Once the GPSDO is in place, we +very highly discourage further removal, as this also risks damaging the +pins.</b> + +\section gpsdob_using Using the GPSDO in Your Application + +By default, if a GPSDO is detected at startup, the USRP will be +configured to use it as a frequency and time reference. The internal +VITA timestamp will be initialized to the GPS time, and the internal +oscillator will be phase-locked to the 10MHz GPSDO reference. If the +GPSDO is not locked to satellites, the VITA time will not be +initialized. + +GPS data is obtained through the **mboard_sensors** interface. To +retrieve the current GPS time, use the **gps_time** sensor: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} +usrp->get_mboard_sensor("gps_time"); +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The returned value will be the current epoch time, in seconds since +January 1, 1970. This value is readily converted into human-readable +format using the **time.h** library in C, **boost::posix_time** in C++, +etc. + +Other information can be fetched as well. You can query the lock status +with the **gps_locked** sensor, as well as obtain raw NMEA sentences +using the **gps_gprmc**, and **gps_gpgga** sensors. Location +information can be parsed out of the **gps_gpgga** sensor by using **gpsd** +or another NMEA parser. + +*/ +// vim:ft=doxygen: diff --git a/host/docs/gpsdo_b2x0.rst b/host/docs/gpsdo_b2x0.rst deleted file mode 100644 index a0815d23a..000000000 --- a/host/docs/gpsdo_b2x0.rst +++ /dev/null @@ -1,79 +0,0 @@ -======================================================================== -UHD - Internal GPSDO Application Notes (USRP-B2x0 Models) -======================================================================== - -.. contents:: Table of Contents - -This application note describes the use of integrated GPS-disciplined -oscillators with Ettus Research USRP devices. - ------------------------------------------------------------------------- -Specifications ------------------------------------------------------------------------- -* **Receiver type**: 50 channel with WAAS, EGNOS, MSAS -* **10MHz ADEV**: 5e-11 over >24h -* **1PPS RMS jitter**: <50ns 1-sigma -* **Holdover**: <20us over 3h - -**Phase noise**: - -+------------+-------------+ -| | TCXO | -+============+=============+ -| **1Hz** | -65dBc/Hz | -+------------+-------------+ -| **10Hz** | -102dBc/Hz | -+------------+-------------+ -| **100Hz** | -132dBc/Hz | -+------------+-------------+ -| **1kHz** | -148dBc/Hz | -+------------+-------------+ -| **10kHz** | -152dBc/Hz | -+------------+-------------+ -| **100kHz** | <-155dBc/Hz | -+------------+-------------+ - -**Antenna Types:** - -The GPSDO is capable of supplying a 3V for active GPS antennas or supporting passive antennas. - ------------------------------------------------------------------------- -Installation Instructions ------------------------------------------------------------------------- -To install the GPSDO, you must insert it into the slot on the board -near the 10 MHz Reference SMA. Keep in mind that the two sides of the -GPSDO have a different number of pins. When inserting the GPSDO, make -sure to press down firmly and evenly. When turning on the USRP B2X0 device, -a green LED should illuminate on the GPSDO. This signifies that the unit -has successfully been placed. - -**NOTE: The pins on the GPSDO are very fragile. Be sure to press down -evenly, or the pins may bend or break. Once the GPSDO is in place, -we very highly discourage further removal, as this also risks damaging -the pins.** - ------------------------------------------------------------------------- -Using the GPSDO in Your Application ------------------------------------------------------------------------- -By default, if a GPSDO is detected at startup, the USRP will be configured -to use it as a frequency and time reference. The internal VITA timestamp -will be initialized to the GPS time, and the internal oscillator will be -phase-locked to the 10MHz GPSDO reference. If the GPSDO is not locked to -satellites, the VITA time will not be initialized. - -GPS data is obtained through the **mboard_sensors** interface. To retrieve -the current GPS time, use the **gps_time** sensor: - -:: - - usrp->get_mboard_sensor("gps_time"); - -The returned value will be the current epoch time, in seconds since -January 1, 1970. This value is readily converted into human-readable -format using the **time.h** library in C, **boost::posix_time** in C++, etc. - -Other information can be fetched as well. You can query the lock status -with the **gps_locked** sensor, as well as obtain raw NMEA sentences using -the **gps_gprmc**, and **gps_gpgga** sensors. Location -information can be parsed out of the **gps_gpgga** sensor by using **gpsd** or -another NMEA parser. diff --git a/host/docs/gpsdo_x3x0.dox b/host/docs/gpsdo_x3x0.dox new file mode 100644 index 000000000..24997d50b --- /dev/null +++ b/host/docs/gpsdo_x3x0.dox @@ -0,0 +1,76 @@ +/*! \page page_gpsdo_x3x0 Internal GPSDO Application Notes (USRP-X3x0 Models) + +\tableofcontents + +This application note describes the use of the board-mounted GPS +Disciplined OCXO, as used with the USRP X300/X310. For information +regarding the GPSDO that is compatible with the USRP N2xx or E1xx, +please see \ref page_gpsdo. + +\section gpsdox_specs Specifications + +- **Receiver type**: 50 channel with WAAS, EGNOS, MSAS +- **10 MHz ADEV**: 5e-11 over \>24h +- **1PPS RMS jitter**: \<50ns 1-sigma +- **Holdover**: \<20us over 3h + +<b>Phase noise</b>: + + Offset | OCXO Phase noise power +---------|---------------------------- +1Hz |-75dBc/Hz +10Hz |-110dBc/Hz +100Hz |-132dBc/Hz +1kHz |-142dBc/Hz +10kHz |-145dBc/Hz +100kHz |-150dBc/Hz + +<b>Antenna Types:</b> + +The GPSDO is capable of supplying a 3V for active GPS antennas or +supporting passive antennas. + +\section gpsdox_install Installation Instructions + +To install the GPSDO, you must insert it into the slot on the board near +the 10 MHz Reference SMA. Keep in mind that the two sides of the GPSDO +have a different number of pins. When inserting the GPSDO, make sure to +press down firmly and evenly. When turning on the USRP X3x0 device, a +green LED should illuminate on the GPSDO. This signifies that the unit +has successfully been placed. + +<b>NOTE: The pins on the GPSDO are very fragile. Be sure to press down +evenly, or the pins may bend or break. Once the GPSDO is in place, we +very highly discourage further removal, as this also risks damaging the +pins.</b> + +\section gpsdox_using Using the GPSDO in Your Application + +By default, if a GPSDO is detected at startup, the USRP will be +configured to use it as a frequency and time reference. The internal +VITA timestamp will be initialized to the GPS time, and the internal +oscillator will be phase-locked to the 10MHz GPSDO reference. If the +GPSDO is not locked to satellites, the VITA time will not be +initialized. + +GPS data is obtained through the **mboard_sensors** interface. To +retrieve the current GPS time, use the **gps_time** sensor: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} + usrp->get_mboard_sensor("gps_time"); +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The returned value will be the current epoch time, in seconds since +January 1, 1970. This value is readily converted into human-readable +format using the **time.h** library in C, **boost::posix_time** in C++, +etc. + +Other information can be fetched as well. You can query the lock status +with the **gps_locked** sensor, as well as obtain raw NMEA sentences +using the **gps_gprmc**, and **gps_gpgga** sensors. Location +information can be parsed out of the **gps_gpgga** sensor by using **gpsd** +or another NMEA parser. + + +*/ +// vim:ft=doxygen: diff --git a/host/docs/gpsdo_x3x0.rst b/host/docs/gpsdo_x3x0.rst deleted file mode 100644 index 0d4d31f3b..000000000 --- a/host/docs/gpsdo_x3x0.rst +++ /dev/null @@ -1,82 +0,0 @@ -======================================================================== -UHD - Internal GPSDO Application Notes (USRP-X3x0 Models) -======================================================================== - -.. contents:: Table of Contents - -This application note describes the use of the board-mounted GPS Disciplined OCXO, -as used with the USRP X300/X310. For information regarding the GPSDO that is -compatible with the USRP N2xx or E1xx, please see: - -`USRP-N2x0/E1x0 Internal GPSDO Device Manual <./gpsdo.html>`_ - ------------------------------------------------------------------------- -Specifications ------------------------------------------------------------------------- -* **Receiver type**: 50 channel with WAAS, EGNOS, MSAS -* **10 MHz ADEV**: 5e-11 over >24h -* **1PPS RMS jitter**: <50ns 1-sigma -* **Holdover**: <20us over 3h - -**Phase noise**: - -+------------+------------+ -| | OCXO | -+============+============+ -| **1Hz** | -75dBc/Hz | -+------------+------------+ -| **10Hz** | -110dBc/Hz | -+------------+------------+ -| **100Hz** | -132dBc/Hz | -+------------+------------+ -| **1kHz** | -142dBc/Hz | -+------------+------------+ -| **10kHz** | -145dBc/Hz | -+------------+------------+ -| **100kHz** | -150dBc/Hz | -+------------+------------+ - -**Antenna Types:** - -The GPSDO is capable of supplying a 3V for active GPS antennas or supporting passive antennas. - ------------------------------------------------------------------------- -Installation Instructions ------------------------------------------------------------------------- -To install the GPSDO, you must insert it into the slot on the board -near the 10 MHz Reference SMA. Keep in mind that the two sides of the -GPSDO have a different number of pins. When inserting the GPSDO, make -sure to press down firmly and evenly. When turning on the USRP B2X0 device, -a green LED should illuminate on the GPSDO. This signifies that the unit -has successfully been placed. - -**NOTE: The pins on the GPSDO are very fragile. Be sure to press down -evenly, or the pins may bend or break. Once the GPSDO is in place, -we very highly discourage further removal, as this also risks damaging -the pins.** - ------------------------------------------------------------------------- -Using the GPSDO in Your Application ------------------------------------------------------------------------- -By default, if a GPSDO is detected at startup, the USRP will be configured -to use it as a frequency and time reference. The internal VITA timestamp -will be initialized to the GPS time, and the internal oscillator will be -phase-locked to the 10MHz GPSDO reference. If the GPSDO is not locked to -satellites, the VITA time will not be initialized. - -GPS data is obtained through the **mboard_sensors** interface. To retrieve -the current GPS time, use the **gps_time** sensor: - -:: - - usrp->get_mboard_sensor("gps_time"); - -The returned value will be the current epoch time, in seconds since -January 1, 1970. This value is readily converted into human-readable -format using the **time.h** library in C, **boost::posix_time** in C++, etc. - -Other information can be fetched as well. You can query the lock status -with the **gps_locked** sensor, as well as obtain raw NMEA sentences using -the **gps_gprmc**, and **gps_gpgga** sensors. Location -information can be parsed out of the **gps_gpgga** sensor by using **gpsd** or -another NMEA parser. diff --git a/host/docs/identification.dox b/host/docs/identification.dox new file mode 100644 index 000000000..38bc93439 --- /dev/null +++ b/host/docs/identification.dox @@ -0,0 +1,112 @@ +/*! \page page_identification Device Identification Notes + +\tableofcontents + +\section id_identifying Identifying USRP Devices + +Devices are addressed through key/value string pairs. These string pairs +can be used to narrow down the search for a specific device or group of +devices. Most UHD utility applications and examples have an `--args` +parameter that takes a device address, which is expressed as a delimited +string. + +See device_addr.hpp for reference. + +\subsection id_identifying_common Common device identifiers + +Every device has several ways of identifying it on the host system: + +Identifier | Key | Notes | Example +-----------|----------|-----------------------------------------------------------|--------------------------------- +Serial | serial | globally unique identifier | 12345678 +Address | addr | unique identifier on a network | 192.168.10.2 +Resource | resource | unique identifier for USRP RIO devices (over PCI Express) | RIO0 +Name | name | optional user-set identifier | my_usrp1 (User-defined value) +Type | type | hardware series identifier | usrp1, usrp2, b200, x300, ... + +\subsection id_identifying_cmdline Device discovery via command line + +Devices attached to your system can be discovered using the +`uhd_find_devices` program. This program scans your system for +supported devices and prints out an enumerated list of discovered +devices and their addresses. The list of discovered devices can be +narrowed down by specifying device address args. + + uhd_find_devices + +Device address arguments can be supplied to narrow the scope of the +search. + + uhd_find_devices --args="type=usrp1" + + -- OR -- + + uhd_find_devices --args="serial=12345678" + +\subsection id_identifying_api Device discovery through the API + +The device::find() API call searches for devices and returns a list +of discovered devices. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} + uhd::device_addr_t hint; //an empty hint discovers all devices + uhd::device_addrs_t dev_addrs = uhd::device::find(hint); +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The `hint` argument can be populated to narrow the scope of the search. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} + uhd::device_addr_t hint; + hint["type"] = "usrp1"; + uhd::device_addrs_t dev_addrs = uhd::device::find(hint); + + -- OR -- + + uhd::device_addr_t hint; + hint["serial"] = "12345678"; + uhd::device_addrs_t dev_addrs = uhd::device::find(hint); +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +\subsection id_identifying_props Device properties + +Properties of devices attached to your system can be probed with the +`uhd_usrp_probe` program. This program constructs an instance of the +device and prints out its properties, such as detected daughterboards, +frequency range, gain ranges, etc... + +<b>Usage:</b> + + uhd_usrp_probe --args <device-specific-address-args> + +\section id_naming Naming a USRP Device + +For convenience purposes, users may assign a custom name to their USRP +device. The USRP device can then be identified via name, rather than a +difficult to remember serial or address. + +A name has the following properties: + +- is composed of ASCII characters +- is 0-20 characters +- is not required to be unique + +\subsection id_naming_set Set a custom name + +Run the following commands: + + cd <install-path>/lib/uhd/utils + ./usrp_burn_mb_eeprom --args=<optional device args> --values="name=lab1_xcvr" + +\subsection id_naming_discovery Discovery via name + +The keyword `name` can be used to narrow the scope of the search. +Example with the find devices utility: + + uhd_find_devices --args="name=lab1_xcvr" + + -- OR -- + + uhd_find_devices --args="type=usrp1, name=lab1_xcvr" + +*/ +// vim:ft=doxygen: diff --git a/host/docs/identification.rst b/host/docs/identification.rst index cbae25082..65b4e5e99 100644 --- a/host/docs/identification.rst +++ b/host/docs/identification.rst @@ -112,7 +112,7 @@ Run the following commands: :: cd <install-path>/lib/uhd/utils - ./usrp_burn_mb_eeprom --args=<optional device args> --key=name --val=lab1_xcvr + ./usrp_burn_mb_eeprom --args=<optional device args> --values="name=lab1_xcvr" ^^^^^^^^^^^^^^^^^^ Discovery via name diff --git a/host/docs/images.dox b/host/docs/images.dox new file mode 100644 index 000000000..321452b87 --- /dev/null +++ b/host/docs/images.dox @@ -0,0 +1,114 @@ +/*! \page page_images Firmware and FPGA Image Application Notes + +\tableofcontents + +\section images_overview Images Overview + +Every USRP device must be loaded with special firmware and FPGA images. +The methods of loading images into the device vary among devices: + +- **USRP1:** The host code will automatically load the firmware and + FPGA at runtime. +- **USRP2:** The user must manually write the images onto the USRP2 SD + card. +- **USRP-N Series:** The user programs an image into on-board storage, + which then is automatically loaded at runtime. +- **USRP-E Series:** The host code will automatically load the FPGA at + runtime. +- **USRP-B Series:** The host code will automatically load the FPGA at + runtime. +- **USRP-X Series:** The user programs an image into on-board storage, + which then is automatically loaded at runtime. + +\section images_prebuild Pre-built Images + +Pre-built images are available for download. + +- <a href="http://files.ettus.com/binaries/master_images/">Master Branch images</a> +- <a href="http://files.ettus.com/binaries/maint_images/">Maint Branch images</a> + +The pre-built images come in two forms: + +- bundled with UHD software in a platform-specific installer +- stand-alone platform-independent archive files + +\subsection images_prebuilt_downloader UHD Images Downloader + +The UHD images downloader downloads UHD images compatible with the host +code and places them in the default images directory. + +By default, it can be found at: `<install-path>/lib/uhd/utils/uhd_images_downloader.py` + +By default, it installs images to: `<install-path>/share/uhd/images` + +\subsection images_prebuilt_installers Platform installers + +The UNIX-based installers will install the images into `/usr/share/uhd/images`. + +The Windows installers will install the images into `C:/Program Files/UHD/share/uhd/images`. + +\subsection images_prebuilt_archive Archive install + +When installing images from an archive, there are two options: + +<b>Option 1:</b> + +Unpack the archive into the UHD installation prefix. UHD software will +always search `<install-path>/share/uhd/images` for image files. +Where `<install-path>` was set by the `CMAKE_INSTALL_PREFIX` at +configure-time. + +<b>Option 2:</b> + +Unpack the archive anywhere and set the `UHD_IMAGES_PATH` +environment variable. `UHD_IMAGES_PATH` may contain a list of +directories to search for image files. + +\section images_building Building Images + +The UHD source repository comes with the source code necessary to build +both firmware and FPGA images for all supported devices. + +The build commands for a particular image can be found in +`<uhd-repo-path>/images/Makefile`. + +\subsection images_building_xilinx Xilinx FPGA builds + +USRP Xilinx FPGA images are built with two different versions of ISE, +depending on the device. + +The build requires that you have a UNIX-like environment with `Make`. +Make sure that `xtclsh` from the Xilinx ISE bin directory is in your `$PATH`. + +- Xilinx ISE 14.4: USRP X3x0 Series, USRP B2x0 + +See `<uhd-repo-path>/fpga/usrp3/top/`. + +- Xilinx ISSE 12.2: USRP N2x0, USRP B1x0, USRP E1x0, USRP2 + +See `<uhd-repo-path>/fpga/usrp2/top/`. + +\subsection images_building_zpu ZPU firmware builds + +The ZPU GCC compiler is required to build the ZPU firmware images. The +build requires that you have a UNIX-like environment with `CMake` and +`Make`. Make sure that `zpu-elf-gcc` is in your `$PATH`. + +See `<uhd-repo-path>/firmware/zpu`. + +\subsection images_building_altera Altera FPGA builds + +Quartus is required to build the Altera FPGA image for the USRP1. +Pre-built images can also be found in `<uhd-repo-path>/fpga/usrp1/rbf`. + +See `<uhd-repo-path>/fpga/usrp1/toplevel/`. + +\subsection images_building_fx2 FX2 firmware builds + +The SDCC compiler is required to build the FX2 firmware images. The +build requires that you have a UNIX-like environment with `CMake` and `Make`. + +See `<uhd-repo-path>/firmware/fx2`. + +*/ +// vim:ft=doxygen: diff --git a/host/docs/images.rst b/host/docs/images.rst deleted file mode 100644 index 37fbabf4b..000000000 --- a/host/docs/images.rst +++ /dev/null @@ -1,126 +0,0 @@ -======================================================================== -UHD - Firmware and FPGA Image Application Notes -======================================================================== - -.. contents:: Table of Contents - ------------------------------------------------------------------------- -Images Overview ------------------------------------------------------------------------- -Every USRP device must be loaded with special firmware and FPGA images. -The methods of loading images into the device vary among devices: - -* **USRP1:** The host code will automatically load the firmware and FPGA at runtime. -* **USRP2:** The user must manually write the images onto the USRP2 SD card. -* **USRP-N Series:** The user programs an image into on-board storage, which - then is automatically loaded at runtime. -* **USRP-E Series:** The host code will automatically load the FPGA at runtime. -* **USRP-B Series:** The host code will automatically load the FPGA at runtime. -* **USRP-X Series:** The user programs an image into on-board storage, which - then is automatically loaded at runtime. - ------------------------------------------------------------------------- -Pre-built Images ------------------------------------------------------------------------- - -Pre-built images are available for download. - -* `Master Branch images <http://files.ettus.com/binaries/master_images/>`_ -* `Maint Branch images <http://files.ettus.com/binaries/maint_images/>`_ - -The pre-built images come in two forms: - -* bundled with UHD software in a platform-specific installer -* stand-alone platform-independent archive files - -^^^^^^^^^^^^^^^^^^^^^^ -UHD Images Downloader -^^^^^^^^^^^^^^^^^^^^^^ - -The UHD images downloader downloads UHD images compatible with the host code -and places them in the default images directory. - -By default, it can be found at: **<install-path>/lib/uhd/utils/uhd_images_downloader.py** - -By default, it installs images to: **<install-path>/share/uhd/images** - -^^^^^^^^^^^^^^^^^^^^^^ -Platform installers -^^^^^^^^^^^^^^^^^^^^^^ -The UNIX-based installers will install the images into **/usr/share/uhd/images**. - -The Windows installers will install the images into **C:/Program Files/UHD/share/uhd/images**. - -^^^^^^^^^^^^^^^^^^^^^^ -Archive install -^^^^^^^^^^^^^^^^^^^^^^ -When installing images from an archive, there are two options: - -**Option 1:** - -Unpack the archive into the UHD installation prefix. -UHD software will always search **<install-path>/share/uhd/images** for image files. -Where **<install-path>** was set by the **CMAKE_INSTALL_PREFIX** at configure-time. - -**Option 2:** - -Unpack the archive anywhere and set the **UHD_IMAGES_PATH** environment variable. -**UHD_IMAGES_PATH** may contain a list of directories to search for image files. - ------------------------------------------------------------------------- -Building Images ------------------------------------------------------------------------- - -The UHD source repository comes with the source code necessary to build -both firmware and FPGA images for all supported devices. - -The build commands for a particular image can be found in **<uhd-repo-path>/images/Makefile**. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Xilinx FPGA builds -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -USRP Xilinx FPGA images are built with two different versions of ISE, depending -on the device. - -The build requires that you have a UNIX-like environment with **Make**. -Make sure that **xtclsh** from the Xilinx ISE bin directory is in your **$PATH**. - - -**Xilinx ISE 14.4** -* USRP X3x0 Series - -See **<uhd-repo-path>/fpga/usrp3/top/**. - -**Xilinx ISE 12.2** -* USRP N2x0 -* USRP B2x0 -* USRP B1x0 -* USRP E1x0 -* USRP2 - -See **<uhd-repo-path>/fpga/usrp2/top/**. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -ZPU firmware builds -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The ZPU GCC compiler is required to build the ZPU firmware images. -The build requires that you have a UNIX-like environment with **CMake** and **Make**. -Make sure that **zpu-elf-gcc** is in your **$PATH**. - -See **<uhd-repo-path>/firmware/zpu**. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Altera FPGA builds -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Quartus is required to build the Altera FPGA image for the USRP1. -Pre-built images can also be found in **<uhd-repo-path>/fpga/usrp1/rbf**. - -See **<uhd-repo-path>/fpga/usrp1/toplevel/***. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -FX2 firmware builds -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The SDCC compiler is required to build the FX2 firmware images. -The build requires that you have a UNIX-like environment with **CMake** and **Make**. - -See **<uhd-repo-path>/firmware/fx2**. diff --git a/host/docs/index.rst b/host/docs/index.rst deleted file mode 100644 index ffad1488d..000000000 --- a/host/docs/index.rst +++ /dev/null @@ -1,68 +0,0 @@ -======================================================================== -UHD - USRP Hardware Driver -======================================================================== - -UHD software is the "Universal Software Radio Peripheral" Hardware Driver software. -The goal of UHD software is to provide a host driver and API for current and future Ettus Research products. -Users will be able to use the UHD driver standalone or with third-party applications. - ------------------------------------------------------------------------- -Contents ------------------------------------------------------------------------- - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Building and Installing UHD Software -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -* `Build Guide <./build.html>`_ -* `Installation Guide (Linux) <http://code.ettus.com/redmine/ettus/projects/uhd/wiki/UHD_Linux>`_ -* `Installation Guide (Windows) <http://code.ettus.com/redmine/ettus/projects/uhd/wiki/UHD_Windows>`_ - -^^^^^^^^^^^^^^^^^^^^^ -General UHD Manuals -^^^^^^^^^^^^^^^^^^^^^ -* `General Application Notes <./general.html>`_ -* `Device Identification Notes <./identification.html>`_ -* `Firmware and FPGA Image Notes <./images.html>`_ -* `Daughterboard Application Notes <./dboards.html>`_ -* `Transport Application Notes <./transport.html>`_ -* `Synchronization Application Notes <./sync.html>`_ -* `Calibration Application Notes <./calibration.html>`_ - -^^^^^^^^^^^^^^^^^^^^^ -USRP N-Series Devices -^^^^^^^^^^^^^^^^^^^^^ -* `USRP-N2x0 Series Device Manual <./usrp2.html>`_ -* `USRP-N2x0 Internal GPSDO Device Manual <./gpsdo.html>`_ - -^^^^^^^^^^^^^^^^^^^^^ -USRP B-Series Devices -^^^^^^^^^^^^^^^^^^^^^ -* `USRP-B100 Series Device Manual <./usrp_b100.html>`_ -* `USRP-B2x0 Series Device Manual <./usrp_b200.html>`_ -* `USRP1 Device Manual <./usrp1.html>`_ - -^^^^^^^^^^^^^^^^^^^^^ -USRP E-Series Devices -^^^^^^^^^^^^^^^^^^^^^ -* `USRP-E1x0 Series Device Manual <./usrp_e1x0.html>`_ -* `USRP-E1x0 Internal GPSDO Device Manual <./gpsdo.html>`_ - -^^^^^^^^^^^^^^^^^^^^^ -USRP X-Series Devices -^^^^^^^^^^^^^^^^^^^^^ -* `USRP-X3x0 Series Device Manual <./usrp_x3x0.html>`_ -* `USRP-X3x0 Internal GPSDO Device Manual <./gpsdo_x3x0.html>`_ -* `USRP-X3x0 Front Panel GPIO API <./gpio_api.html>`_ -* `USRP-X3x0 System Configuration <./usrp_x3x0_config.html>`_ - -^^^^^^^^^^^^^^^^^^^^^ -USRP Legacy Series -^^^^^^^^^^^^^^^^^^^^^ -* `USRP2 Device Manual <./usrp2.html>`_ - -^^^^^^^^^^^^^^^^^^^^^ -API Documentation -^^^^^^^^^^^^^^^^^^^^^ -* `Doxygen <./../../doxygen/html/index.html>`_ -* `Using the API <./coding.html>`_ -* `Device Streaming <./stream.html>`_ diff --git a/host/docs/mainpage.dox b/host/docs/mainpage.dox new file mode 100644 index 000000000..597938c35 --- /dev/null +++ b/host/docs/mainpage.dox @@ -0,0 +1,66 @@ +/*! \mainpage Table Of Contents + +\tableofcontents + +Welcome to the manual pages for the USRP Hardware Driver (UHD), the host driver +for Ettus Research devices. Here, you will find information on how to use the +devices and how to use the API to connect to them through your own software. + +# Building and Installing UHD + +\li \subpage page_build_guide +\li <a href="http://code.ettus.com/redmine/ettus/projects/uhd/wiki/UHD_Linux">Installation Guide (Linux)</a> +\li <a href="http://code.ettus.com/redmine/ettus/projects/uhd/wiki/UHD_Windows">Installation Guide (Windows)</a> + +# General UHD Manuals + +\li \subpage page_general +\li \subpage page_identification +\li \subpage page_images +\li \subpage page_dboards +\li \subpage page_transport +\li \subpage page_sync +\li \subpage page_calibration + +# Device Specific Manuals + +## USRP N-Series Devices + +\li \subpage page_usrp2 +\li \subpage page_gpsdo + +## USRP B-Series Devices + +\li \subpage page_usrp_b100 +\li \subpage page_usrp_b200 +\li \subpage page_gpsdo_b2x0 +\li \subpage page_usrp1 + +## USRP E-Series Devices + +\li \subpage page_usrp_e1x0 +\li \subpage page_gpsdo + +## USRP X-Series Devices + +\li \subpage page_usrp_x3x0 +\li \subpage page_gpsdo_x3x0 +\li \subpage page_gpio_api +\li \subpage page_usrp_x3x0_config +\li \subpage page_ni_rio_kernel + +## USRP Legacy Series + +\li \subpage page_usrp2 + +## OctoClock + +\li \subpage page_octoclock + +# API Documentation + +\li \subpage page_coding +\li \subpage page_stream + +*/ +// vim:ft=doxygen: diff --git a/host/docs/ni_rio_kernel.dox b/host/docs/ni_rio_kernel.dox new file mode 100644 index 000000000..d364cad3c --- /dev/null +++ b/host/docs/ni_rio_kernel.dox @@ -0,0 +1,142 @@ +/*! \page page_ni_rio_kernel NI RIO Kernel Modules for X-Series PCIe Connectivity + +\tableofcontents + +\section linux_rio Linux NI RIO Installation and Usage + +\subsection linux_requirements Requirements + +In order to use the PCIe transport connection on the USRP X300 / X310 devices, +you must install the NI USRP RIO driver stack. These include kernel modules +which must be loaded. + +Your kernel version must be supported by the kernel modules. Only 64-bit kernels +are supported. + +<b>Currently, the latest supported kernel version is 3.14.x.</b> + +\subsection linux_installation Installing the Drivers in Linux + +The NI USRP RIO installer can be found <a +href=http://files.ettus.com/binaries/niusrprio/niusrprio-installer.tar.gz>here</a>. + +Download the installer and extract it with the following command: + + tar zxf niusrprio-installer.tar.gz + +The files will be extracted into a directory called <b>niusrprio-installer</b>. + +To install the NI USRPRIO kernel modules and RPC server, run the following +command: + + sudo niusrprio-installer/INSTALL + +Select 'y' for each prompt, and the script will install all necessary +components. This script will automatically load all necessary kernel modules +for the duration of the session. + +\subsection linux_enabling Enabling and Disabling Usage + +Once everything is installed, run the following commands to enable use of the +X300/X310 over PCI Express: + + sudo /usr/local/bin/niusrprio_pcie start + +To stop these processes, run the following command: + + sudo /usr/local/bin/niusrprio_pcie stop + +To check if the kernel modules are loaded and if the RPC server is running, run +the following command: + + /usr/local/bin/niusrprio_pcie status + +<b>NOTE:</b> niusrprio_pcie start does not run when the host system is booted. +If you would like the USRP PCIe device to be available automatically after +a system restart, please create an init.d script that runs niusrprio_pcie start. + +\subsection linux_swapping Hot-Plugging and Power-Cycling + +The NI USRPRIO kernel modules are built for a specific kernel version. If you +upgrade/downgrade the linux kernel on the host to a version different from the +one that the installer was run on, then you may see the following error message +when running `niusrprio star`. + + ERROR: could not insert 'NiRioSrv': Unknown symbol in module, or unknown + parameter (see dmesg) ERROR: could not insert 'niusrpriok': Unknown symbol + in module, or unknown parameter (see dmesg) + +To rebuild the kernel modules for the currently running kernel, simple run the +following + + sudo /usr/local/bin/niusrprio_pcie stop sudo /usr/local/bin/updateNIDrivers + --no-prompt sudo /usr/local/bin/niusrprio_pcie start + +\subsection linux_uninstalling Uninstalling in Linux + +To uninstall the NI USRP RIO kernel modules and RPC server, run the following +command: + + sudo niusrprio-installer/UNINSTALL + +Select y at the prompt, and the script will uninstall all installed components. + + +\section windows_rio Windows NI RIO Installation and Usage + +\subsection win_requirements Requirements + +The kernel driver is only supported on: + +- Windows 8.1 32-bit +- Windows 8.1 64-bit +- Windows 7 32-bit +- Windows 7 64-bit +- Windows Vista 32-bit +- Windows Vista 64-bit +- Windows XP (SP3) 32-bit. + +\subsection win_install Installing NI-USRP in Windows + +The NI-USRP 1.3 installer can be found <a +href="http://www.ni.com/download/ni-usrp-1.3/4711/en/">here</a> You will need to +create a free NI User Account to download the installer. + +Perform the following steps to download and install the NI-USRP exe driver +package: + +- Choose the "2. Standard Download:NIUSRP130.exe" option to download +- NIUSRP130.exe to your computer Run NIUSRP130.exe as an Administrator and +- extract the contents to 'C:\\National Instruments Downloads\\NI-USRP\\1.3' In the +- extract location, run setup.exe and follow the prompts. + +Reboot the computer after both the NI-USRP package has been installed. + +\subsection win_enabling Enabling and Disabling Usage + +Once everything is installed and the system is rebooted, your X300/X310 PCI +Express device should automatically be detected by the Windows Device Manager. +The device should be enabled by default. + +- To disable the USRPRIO device, navigate to "Device Manager", locate your +- USRPRIO-X3x0 device, right-click on it and choose "Disable". To enable the +- USRPRIO device, navigate to "Device Manager", locate your USRPRIO-X3x0 device, +- right-click on it and choose "Enable". + +\subsection win_swapping Hot-plugging and Power-cycling + +The USRP X3x0, NI USRP-294x and NI USRP-295x devices <b>cannot</b> be hot-swapped +when connected over PCI Express. Unplugging the PCI Express connection or +powering the device should be done only after disabling the device. + +<b>WARNING:</b> If the device is unplugged without running the above command, the +system could become unstable. + +\subsection win_uninstall Uninstalling NI-USRP in Windows + +Navigate to the Control Panel and open "Programs". Then select National +Instruments Software and select NI-USRP and NI-RIO from the list. Click on +uninstall to remove the drivers from your system. + +*/ +// vim:ft=doxygen: diff --git a/host/docs/octoclock.dox b/host/docs/octoclock.dox new file mode 100644 index 000000000..d4c6161a1 --- /dev/null +++ b/host/docs/octoclock.dox @@ -0,0 +1,126 @@ +/*! \page page_octoclock OctoClock Device Manual + +\tableofcontents + +\section octoclock_features Feature list + +- Hardware Capabilities: + - Fully integrated timing source with 8-Way distribution (10 MHz and 1 PPS) + - User selection between internal GPSDO (when present) or external 10 MHz/1 PPS source + - Source detection with automatic switch over in case of failure or disconnect + - Streaming GPS time and NMEA strings over Ethernet (OctoClock-G only) + +\section octoclock_load Loading Firmware onto the Octoclock + +\subsection bootloader OctoClock bootloader + +If you purchased your OctoClock device before Ethernet functionality was introduced, or if your unit's +bootloader has somehow become corrupted, you must burn the bootloader onto the device before you can load +the primary firmware. + +To load the bootloader onto the OctoClock, two things are needed: + +- AVR programmer +- AVRdude software + +Connect the AVR programmer to J108, as specified on the <a href="http://files.ettus.com/schematics/octoclock/octoclock.pdf"> +schematics</a>. Once you verify that the programmer is properly connected, run the following commands to burn the firmware: + + cd <install path>/share/uhd/images + avrdude -p atmega128 -c <programmer name> -P usb -U efuse:w:0xFF:m -U hfuse:w:0x80:m -U lfuse:w:0xFF:m -U flash:w:octoclock_bootloader.hex:i + +**Note:** On Linux, **sudo** must be used with the **avrdude** command. + +Once the bootloader has been burned, power-cycle your OctoClock device and refer to the below instructions on burning the OctoClock's +primary firmware. + +\subsection application Primary Octoclock firmware + +To load firmware onto the OctoClock, you must use the *octoclock_firmware_burner* utility, specifying the IP +address of the OctoClock device, as follows: + + octoclock_firmware_burner --addr=192.168.10.3 + +\section octoclock_network Setting Up Networking + +\subsection host_interface Setting up the host interface + +The OctoClock communicates with the host machine at the UDP layer over Gigabit Ethernet. The default device +of the OctoClock is **192.168.10.3**. You will need to configure the host machine's Ethernet interface with +a static IP address to enable communication. An address of **192.168.10.1** and a subnet mask of +**255.255.255.0** is recommended. + +**Note:** When using UHD software, if an IP address for the OctoClock is not specified, the software will +use UDP broadcast packets to locate the OctoClock. On some systems, the firewall will block UDP broadcast +packets. It is recommended that you change your firewall settings. + +\subsection changing_ip Changing the OctoClock's IP address + +You may need to change the OctoClock's IP address for various reasons. + +- To satisfy your particular network configuration +- To use multiple OctoClocks on the same host computer + +To change the OctoClock's IP address, run the following commands (using the default IP address as an example): + + cd <install path>/lib/uhd/utils + ./octoclock_burn_eeprom --args="<optional device args>" --values="ip-addr=192.168.10.3" + +\section addressing Addressing the Device + +There are two ways to address the OctoClock from UHD software: the IP address, and the serial. + +To use the IP address, address it as follows: + + "addr=<ip address>" + +If you want to use multiple OctoClock devices, address it as follows: + + "addr0=<ip address 1>,addr1=<ip address 2>" + +To use the serial, address it as follows: + + "serial=<serial>" + +\section hardware_setup Hardware Setup Notes + +\subsection front_panel_leds Front Panel LEDs + +The LEDs on the front panel show the current status of the device. Each LED is described below: + +- **Internal:** the device is using the internal GPSDO +- **External:** the device is using an external reference +- **Status:** the device is successfully distributing a 10 MHz and PPS signal +- **PPS:** lights up when a PPS signal is detected +- **GPS Lock:** the internal GPSDO has achieved a lock (not necessary to distribute the signals) +- **Power:** the device is receiving power + +\subsection front_panel_switch Front Panel Switch + +The front panel switch, marked **Primary Ref** determines which reference the OctoClock will prefer to use. If it is receiving +both an internal and external reference, the device will use whichever one the switch specifies. + +However, if it is only receiving an internal reference, it will use this reference no matter what position the switch is in. +The same applies for an external signal. + +\section misc Miscellaneous + +\subsection available_sensors Available Sensors + +The following sensors are available on both the OctoClock and Octoclock-G; these can be queried through the +<a href="classuhd_1_1octoclock.html">API</a>. + +- **ext_ref_detected:** whether or not the device detects an external reference +- **gps_detected:** whether or not the device detects an internal GPSDO +- **using_ref:** which reference the device is using (internal or external) +- **switch_pos:** the position of the front switch (internal or external) + +On the OctoClock-G, the following sensors are added: + +- **gps_gpgga:** the latest GPGGA string sent by the GPSDO +- **gps_gprmc:** the latest GPRMC string sent by the GPSDO +- **gps_time:** the time reported by the GPSDO +- **gps_locked:** whether or not the GPSDO is locked (true/false) +- **gps_servo:** the latest debug trace information sent by the GPSDO + +*/ diff --git a/host/docs/octoclock_firmware_burner.1 b/host/docs/octoclock_firmware_burner.1 new file mode 100644 index 000000000..44ff47a85 --- /dev/null +++ b/host/docs/octoclock_firmware_burner.1 @@ -0,0 +1,45 @@ +.TH "octoclock_firmware_burner" 1 "3.7.1" UHD "User Commands" +.SH NAME +octoclock_firmware_burner - OctoClock Firmware Burner +.SH DESCRIPTION +Burn firmware images onto an Ettus Research OctoClock device over Ethernet. +.SH SYNOPSIS +.B octoclock_firmware_burner [OPTIONS] +.SH OPTIONS +This program works best when only an IP address is specified. +.IP "Device IP Address:" +--addr=\fI"Address"\fR +.IP "This help information:" +--help +.IP "Custom Firmware Filepath:" +--fw-path=\fI"filepath"\fR +.IP "List all OctoClock devices without burning" +--list +.SH EXAMPLES +.SS Selecting a custom firmware path +.sp +octoclock_firmware_burner --addr=192.168.10.3 --fw-path=~/custom_octoclock_image.bin +.ft +.fi +.SH SEE ALSO +UHD documentation: +.B http://files.ettus.com/manual/ +.LP +Other UHD programs: +.sp +uhd_images_downloader(1) usrp2_card_burner(1) usrp_n2xx_simple_net_burner(1) usrp_x3xx_fpga_burner(1) +.SH AUTHOR +This manual page was written by Nicholas Corgan +for the Debian project (but may be used by others). +.SH COPYRIGHT +Copyright (c) 2014 Ettus Research LLC +.LP +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. +.LP +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. diff --git a/host/docs/stream.dox b/host/docs/stream.dox new file mode 100644 index 000000000..0c015c5bd --- /dev/null +++ b/host/docs/stream.dox @@ -0,0 +1,56 @@ +/*! \page page_stream Device streaming + +\tableofcontents + +\section stream_intro Introduction to Streaming + +The concept of streaming refers to the transportation of samples between +host and device. A stream is an object that facilitates streaming +between host application and device. An RX stream allows the user to +receive samples from the device. A TX stream allows the user to transmit +samples to the device. + +\section stream_lle Link Layer Encapsulation + +The VITA49 standard provides encapsulation for sample data across a link +layer. On all second generation hardware (and later), samples are +encapsulated into VRT IF data packets. These packets also provide sample +decoration such as stream time and burst flags. Sample decoration is +exposed to the user in the form of RX and TX metadata structs. + +The length of an IF data packet can be limited by several factors: + +- **MTU of the link layer:** network card, network switch +- **Buffering on the host:** frame size in a ring buffer +- **Buffering on the device:** size of BRAM FIFOs + +\section stream_datatypes Data Types + +There are two important data types to consider when streaming: + +- The data type of the samples used on the host for processing +- The data type of the samples sent through the link-layer + +\subsection stream_datatypes_cpu The host/CPU data type + +The host data type refers to the format of samples used in the host for +baseband processing. Typically, the data type is complex baseband such +as normalized **complex-float32** or **complex-int16**. + +\subsection stream_datatypes_otw The link-layer data type + +The link-layer or "over-the-wire" data type refers to the format of the +samples sent through the link. Typically, this data type is **complex-int16**. +However, to increase throughput over the link-layer, +at the expense of precision, **complex-int8** may be used. + +\subsection stream_datatypes_conv Conversion + +The user may request arbitrary combinations of host and link data types; +however, not all combinations are supported. The user may register +custom data type formats and conversion routines. See +convert.hpp for further documentation. + +TODO: provide example of convert API +*/ +// vim:ft=doxygen: diff --git a/host/docs/stream.rst b/host/docs/stream.rst deleted file mode 100644 index 337d7ca40..000000000 --- a/host/docs/stream.rst +++ /dev/null @@ -1,59 +0,0 @@ -======================================================================== -UHD - Device streaming -======================================================================== - -.. contents:: Table of Contents - ------------------------------------------------------------------------- -Introduction to Streaming ------------------------------------------------------------------------- -The concept of streaming refers to the transportation of samples between host and device. -A stream is an object that facilitates streaming between host application and device. -An RX stream allows the user to receive samples from the device. -A TX stream allows the user to transmit samples to the device. - ------------------------------------------------------------------------- -Link Layer Encapsulation ------------------------------------------------------------------------- -The VITA49 standard provides encapsulation for sample data across a link layer. -On all second generation hardware (and later), samples are encapsulated into VRT IF data packets. -These packets also provide sample decoration such as stream time and burst flags. -Sample decoration is exposed to the user in the form of RX and TX metadata structs. - -The length of an IF data packet can be limited by several factors: - -* **MTU of the link layer:** network card, network switch -* **Buffering on the host:** frame size in a ring buffer -* **Buffering on the device:** size of BRAM FIFOs - ------------------------------------------------------------------------- -Data Types ------------------------------------------------------------------------- -There are two important data types to consider when streaming: - -* The data type of the samples used on the host for processing -* The data type of the samples sent through the link-layer - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The host/CPU data type -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The host data type refers to the format of samples used in the host for baseband processing. -Typically, the data type is complex baseband such as normalized **complex-float32** or **complex-int16**. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The link-layer data type -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The link-layer or "over-the-wire" data type refers to the format of the samples sent through the link. -Typically, this data type is **complex-int16**. -However, to increase throughput over the link-layer, -at the expense of precision, **complex-int8** may be used. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Conversion -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The user may request arbitrary combinations of host and link data types; -however, not all combinations are supported. -The user may register custom data type formats and conversion routines. -See **uhd/convert.hpp** for further documentation. - -TODO: provide example of convert API diff --git a/host/docs/sync.dox b/host/docs/sync.dox new file mode 100644 index 000000000..f41d3a78c --- /dev/null +++ b/host/docs/sync.dox @@ -0,0 +1,197 @@ +/*! \page page_sync Synchronization Application Notes + +\tableofcontents + +The following application notes explain how to synchronize multiple USRP +devices with the goal of transmitting or receiving time-aligned samples +for MIMO or other applications requiring multiple USRP devices operating +synchronously. + +<b>Note:</b> The following synchronization notes do not apply to USRP1, +which does not support the advanced features available in newer +products. + +\section sync_commonref Common Reference Signals + +USRP devices take two reference signals in order to synchronize clocks +and time: + +- A 10MHz reference to provide a single frequency reference for both + devices. +- A pulse-per-second (PPS) to synchronize the sample time across + devices. +- A MIMO cable transmits an encoded time message from one device to + another. + +\subsection sync_commonref_pps PPS and 10 MHz reference signals + +Connect the front panel SMA connectors to the reference sources. +Typically, these signals are provided by an external GPSDO. However, +some USRP models can provide these signals from an optional internal +GPSDO. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} +usrp->set_clock_source("external"); +usrp->set_time_source("external"); +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +<b>Note:</b> Sometimes the delay on the PPS signal will cause it to arrive +inside the timing margin the FPGA sampling clock, causing PPS edges to +be separated by less or more than 100 million cycles of the FPGA clock. +If this is the case, you can change the edge reference of the PPS signal +with this parameter: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} +usrp->set_time_source("_external_"); +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +<b>Note2:</b> For users generating their own signals for the external SMA +connectors, the PPS should be clocked from the 10MHz reference. See the +application notes for your device for specific signal requirements. + +\subsection sync_commonref_mimo MIMO cable reference signals + +Use the MIMO expansion cable to share reference sources (USRP2 and +N-Series). The MIMO cable can be used synchronize one device to another +device. Users of the MIMO cable may use Method 1 (explained below) to +synchronize multiple pairs of devices. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} + usrp->set_clock_source("mimo"); + usrp->set_time_source("mimo"); +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +\section sync_time Synchronizing the Device Time + +The purpose of the PPS signal is to synchronously latch a time into the +device. You can use the `set_time_next_pps(...)` function to either +initialize the sample time to 0 or an absolute time, such as GPS time or +UTC time. For the purposes of synchronizing devices, it doesn't matter +what time you initialize to when using `set_time_next_pps(...)`. + +\subsection sync_time_reg Method 1 - poll the USRP time registers + +One way to initialize the PPS edge is to poll the "last PPS" time from +the USRP device. When the last PPS time increments, the user can +determine that a PPS has occurred: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} + const uhd::time_spec_t last_pps_time = usrp->get_time_last_pps(); + while (last_pps_time == usrp->get_time_last_pps()){ + //sleep 100 milliseconds (give or take) + } + usrp->set_time_next_pps(uhd::time_spec_t(0.0)); +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +\subsection sync_time_gpsdo Method 2 - query the GPSDO for seconds + +Most GPSDOs can be configured to output a NMEA string over the serial +port once every PPS. The user can wait for this string to determine the +PPS edge, and the user can also parse this string to determine GPS time: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} + //call user's function to wait for NMEA message... + usrp->set_time_next_pps(uhd::time_spec_t(0.0)); + + -- OR -- + + //call user's function to wait for NMEA message... + //call user's function to parse the NMEA message... + usrp->set_time_next_pps(uhd::time_spec_t(gps_time+1)); +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +\subsection sync_time_internalgps Method 3 - internal GPSDO + +USRP devices with internal GPSDOs properly configured will automatically +configure themselves to set the VITA time to current UTC time. See \ref page_gpsdo +for more details. + +\subsection sync_time_mimocable Method 4 - MIMO cable + +A USRP device can synchronize its time to another USRP device via the +MIMO cable. Unlike the other methods, this does not use a real "pulse +per second". Rather, the USRP device sends an encoded time message over +the MIMO cable. The slave device will automatically synchronize to the +time on the master device. See \ref usrp2_mimocable for more detail. + +\section sync_phase Synchronizing Channel Phase + +\subsection sync_phase_cordics Align CORDICs in the DSP + +In order to achieve phase alignment between USRP devices, the CORDICS in +both devices must be aligned with respect to each other. This is easily +achieved by issuing stream commands with a time spec property, which +instructs the streaming to begin at a specified time. Since the devices +are already synchronized via the 10 MHz and PPS inputs, the streaming +will start at exactly the same time on both devices. The CORDICs are +reset at each start-of-burst command, so users should ensure that every +start-of-burst also has a time spec set. + +For receive, a burst is started when the user issues a stream command. +This stream command should have a time spec set: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} + uhd::stream_cmd_t stream_cmd(uhd::stream_cmd_t::STREAM_MODE_NUM_SAMPS_AND_DONE); + stream_cmd.num_samps = samps_to_recv; + stream_cmd.stream_now = false; + stream_cmd.time_spec = time_to_recv; + usrp->issue_stream_cmd(stream_cmd); +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +For transmit, a burst is started when the user calls send(). The +metadata should have a time spec set: : + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} + uhd::tx_metadata_t md; + md.start_of_burst = true; + md.end_of_burst = false; + md.has_time_spec = true; + md.time_spec = time_to_send; + + //send a single packet + size_t num_tx_samps = tx_streamer->send(buffs, samps_to_send, md); +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +\subsection sync_phase_lo Align LOs in the front-end (SBX, WBX, CBX) + +Using timed commands, multiple frontends can be tuned at a specific +time. This timed-tuning ensures that the phase offsets between VCO/PLL +chains will remain constant after each re-tune. See notes below: + +- There is a random phase offset between any two frontends +- This phase offset is different for different LO frequencies +- This phase offset remains constant after retuning + - Due to a divider, WBX phase offset will be randomly +/- 180 deg after re-tune +- This phase offset will drift over time due to thermal and other characteristics +- Periodic calibration will be necessary for phase-coherent applications + +Code snippet example, tuning with timed commands: : + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} + //we will tune the frontends in 100ms from now + uhd::time_spec_t cmd_time = usrp->get_time_now() + uhd::time_spec_t(0.1); + + //sets command time on all devices + //the next commands are all timed + usrp->set_command_time(cmd_time); + + //tune channel 0 and channel 1 + usrp->set_rx_freq(1.03e9, 0); // Channel 0 + usrp->set_rx_freq(1.03e9, 1); // Channel 1 + + //end timed commands + usrp->clear_command_time(); +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +\subsection sync_phase_lootherfe Align LOs in the front-end (others) + +After tuning the RF front-ends, each local oscillator may have a random +phase offset due to the dividers in the VCO/PLL chains. This offset will +remain constant after the device has been initialized, and will remain +constant until the device is closed or re-tuned. This phase offset is +typically removed by the user in MIMO applications, using a training +sequence to estimate the offset. It will be necessary to re-align the +LOs after each tune command. + +*/ +// vim:ft=doxygen: diff --git a/host/docs/sync.rst b/host/docs/sync.rst deleted file mode 100644 index 21be60a20..000000000 --- a/host/docs/sync.rst +++ /dev/null @@ -1,197 +0,0 @@ -======================================================================== -UHD - Synchronization Application Notes -======================================================================== - -.. contents:: Table of Contents - -The following application notes explain how to synchronize multiple USRP -devices with the goal of transmitting or receiving time-aligned samples for MIMO -or other applications requiring multiple USRP devices operating synchronously. - -**Note:** The following synchronization notes do not apply to USRP1, -which does not support the advanced features available in newer products. - ------------------------------------------------------------------------- -Common Reference Signals ------------------------------------------------------------------------- -USRP devices take two reference signals in order to synchronize clocks and time: - -* A 10MHz reference to provide a single frequency reference for both devices. -* A pulse-per-second (PPS) to synchronize the sample time across devices. -* A MIMO cable transmits an encoded time message from one device to another. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -PPS and 10 MHz reference signals -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Connect the front panel SMA connectors to the reference sources. -Typically, these signals are provided by an external GPSDO. -However, some USRP models can provide these signals from an optional internal GPSDO. - -:: - - usrp->set_clock_source("external"); - usrp->set_time_source("external"); - -**Note:** -Sometimes the delay on the PPS signal will cause it to arrive inside the timing -margin the FPGA sampling clock, causing PPS edges to be separated by less or -more than 100 million cycles of the FPGA clock. If this is the case, -you can change the edge reference of the PPS signal with this parameter: - -:: - - usrp->set_time_source("_external_"); - -**Note2:** -For users generating their own signals for the external SMA connectors, -the PPS should be clocked from the 10MHz reference. -See the application notes for your device for specific signal requirements. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -MIMO cable reference signals -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Use the MIMO expansion cable to share reference sources (USRP2 and N-Series). -The MIMO cable can be used synchronize one device to another device. -Users of the MIMO cable may use Method 1 (explained below) to synchronize multiple pairs of devices. - -:: - - usrp->set_clock_source("mimo"); - usrp->set_time_source("mimo"); - ------------------------------------------------------------------------- -Synchronizing the Device Time ------------------------------------------------------------------------- -The purpose of the PPS signal is to synchronously latch a time into the device. -You can use the **set_time_next_pps(...)** function to either initialize the sample time to 0 -or an absolute time, such as GPS time or UTC time. -For the purposes of synchronizing devices, -it doesn't matter what time you initialize to when using **set_time_next_pps(...)**. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Method 1 - poll the USRP time registers -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -One way to initialize the PPS edge is to poll the "last PPS" time from the USRP device. -When the last PPS time increments, the user can determine that a PPS has occurred: - -:: - - const uhd::time_spec_t last_pps_time = usrp->get_time_last_pps(); - while (last_pps_time == usrp->get_time_last_pps()){ - //sleep 100 milliseconds (give or take) - } - usrp->set_time_next_pps(uhd::time_spec_t(0.0)); - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Method 2 - query the GPSDO for seconds -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Most GPSDOs can be configured to output a NMEA string over the serial port once every PPS. -The user can wait for this string to determine the PPS edge, -and the user can also parse this string to determine GPS time: - -:: - - //call user's function to wait for NMEA message... - usrp->set_time_next_pps(uhd::time_spec_t(0.0)); - - -- OR -- - - //call user's function to wait for NMEA message... - //call user's function to parse the NMEA message... - usrp->set_time_next_pps(uhd::time_spec_t(gps_time+1)); - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Method 3 - internal GPSDO -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -USRP devices with internal GPSDOs properly configured will automatically -configure themselves to set the VITA time to current UTC time. -See the `GPSDO Application Notes <./gpsdo.html>`_ for more details. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Method 4 - MIMO cable -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -A USRP device can synchronize its time to another USRP device via the MIMO cable. -Unlike the other methods, this does not use a real "pulse per second". -Rather, the USRP device sends an encoded time message over the MIMO cable. -The slave device will automatically synchronize to the time on the master device. -See the `MIMO Cable Application Notes <./usrp2.html#using-the-mimo-cable>`_ for more detail. - ------------------------------------------------------------------------- -Synchronizing Channel Phase ------------------------------------------------------------------------- - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Align CORDICs in the DSP -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -In order to achieve phase alignment between USRP devices, the CORDICS in both -devices must be aligned with respect to each other. This is easily achieved -by issuing stream commands with a time spec property, which instructs the -streaming to begin at a specified time. Since the devices are already -synchronized via the 10MHz and PPS inputs, the streaming will start at exactly -the same time on both devices. The CORDICs are reset at each start-of-burst -command, so users should ensure that every start-of-burst also has a time spec set. - -For receive, a burst is started when the user issues a stream command. This stream command should have a time spec set: -:: - - uhd::stream_cmd_t stream_cmd(uhd::stream_cmd_t::STREAM_MODE_NUM_SAMPS_AND_DONE); - stream_cmd.num_samps = samps_to_recv; - stream_cmd.stream_now = false; - stream_cmd.time_spec = time_to_recv; - usrp->issue_stream_cmd(stream_cmd); - -For transmit, a burst is started when the user calls send(). The metadata should have a time spec set: -:: - - uhd::tx_metadata_t md; - md.start_of_burst = true; - md.end_of_burst = false; - md.has_time_spec = true; - md.time_spec = time_to_send; - - //send a single packet - size_t num_tx_samps = tx_streamer->send(buffs, samps_to_send, md); - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Align LOs in the front-end (SBX, WBX, CBX) -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Using timed commands, multiple frontends can be tuned at a specific time. -This timed-tuning ensures that the phase offsets between VCO/PLL chains -will remain constant after each re-tune. See notes below: - -* There is a random phase offset between any two frontends -* This phase offset is different for different LO frequencies -* This phase offset remains constant after retuning - - * Due to a divider, WBX phase offset will be randomly +/- 180 deg after re-tune - -* This phase offset will drift over time due to thermal and other characteristics -* Periodic calibration will be necessary for phase-coherent applications - -Code snippet example, tuning with timed commands: -:: - - //we will tune the frontends in 100ms from now - uhd::time_spec_t cmd_time = usrp->get_time_now() + uhd::time_spec_t(0.1); - - //sets command time on all devices - //the next commands are all timed - usrp->set_command_time(cmd_time); - - //tune channel 0 and channel 1 - usrp->set_rx_freq(1.03e9, 0/*ch0*/); - usrp->set_rx_freq(1.03e9, 1/*ch1*/); - - //end timed commands - usrp->clear_command_time(); - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Align LOs in the front-end (others) -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -After tuning the RF front-ends, -each local oscillator may have a random phase offset due to the dividers -in the VCO/PLL chains. This offset will remain constant after the device -has been initialized, and will remain constant until the device is closed -or re-tuned. This phase offset is typically removed by the user in MIMO -applications, using a training sequence to estimate the offset. It will -be necessary to re-align the LOs after each tune command. diff --git a/host/docs/transport.dox b/host/docs/transport.dox new file mode 100644 index 000000000..a00a7aa5f --- /dev/null +++ b/host/docs/transport.dox @@ -0,0 +1,160 @@ +/*! \page page_transport Transport Application Notes + +\tableofcontents + +\section transport_intro Introduction + +A transport is the layer between the packet interface and a device IO +interface. The advanced user can pass optional parameters into the +underlying transport layer through the device address. These optional +parameters control how the transport object allocates memory, resizes +kernel buffers, spawns threads, etc. When not spcified, the transport +layer will use values for these parameters that are known to perform +well on a variety of systems. The transport parameters are defined below +for the various transports in the UHD software: + +\section transport_udp UDP Transport (Sockets) + +The UDP transport is implemented with user-space sockets. This means +standard Berkeley sockets API using send()/recv(). + +\subsection transport_udp_params Transport parameters + +The following parameters can be used to alter the transport's default +behavior: + +- `recv_frame_size:` The size of a single receive buffer in bytes +- `num_recv_frames:` The number of receive buffers to allocate +- `send_frame_size:` The size of a single send buffer in bytes +- `num_send_frames:` The number of send buffers to allocate + +<b>Notes:</b> +- `num_recv_frames` does not affect performance. +- `num_send_frames` does not affect performance. +- `recv_frame_size` and `send_frame_size` can be used + to increase or decrease the maximum number of samples per packet. The + frame sizes default to an MTU of 1472 bytes per IP/UDP packet and may be + increased if permitted by your network hardware. + +\subsection transport_udp_flow Flow control parameters + +The host-based flow control expects periodic update packets from the +device. These update packets inform the host of the last packet consumed +by the device, which allows the host to determine throttling conditions +for the transmission of packets. The following mechanisms affect the +transmission of periodic update packets: + +- `ups_per_fifo:` The number of update packets for each FIFO's + worth of bytes sent into the device +- `ups_per_sec:` The number of update packets per second (defaults + to 20 updates per second) + +\subsection transport_udp_sockbufs Resize socket buffers + +It may be useful to increase the size of the socket buffers to move the +burden of buffering samples into the kernel or to buffer incoming +samples faster than they can be processed. However, if your application +cannot process samples fast enough, no amount of buffering can save you. +The following parameters can be used to alter socket's buffer sizes: + +- `recv_buff_size:` The desired size of the receive buffer in + bytes +- `send_buff_size:` The desired size of the send buffer in bytes + +<b>Note:</b> Large send buffers tend to decrease transmit performance. + +\subsection transport_udp_latency Latency Optimization + +Latency is a measurement of the time it takes a sample to travel between +the host and device. Most computer hardware and software is bandwidth +optimized, which may negatively affect latency. If your application has +strict latency requirements, please consider the following notes: + +<b>Note1:</b> The time taken by the device to populate a packet is +proportional to the sample rate. Therefore, to improve receive latency, +configure the transport for a smaller frame size. + +<b>Note2:</b> For overall latency improvements, look for "Interrupt +Coalescing" settings for your OS and ethernet chipset. It seems the +Intel ethernet chipsets offer fine-grained control in Linux. Also, +consult: + +- <http://publib.boulder.ibm.com/infocenter/pseries/v5r3/index.jsp?topic=/com.ibm.aix.prftungd/doc/prftungd/interrupt_coal.htm> + +\subsection transport_udp_linux Linux specific notes + +On Linux, the maximum buffer sizes are capped by the sysctl values +`net.core.rmem_max` and `net.core.wmem_max`. To change the maximum +values, run the following commands: : + + sudo sysctl -w net.core.rmem_max=<new value> + sudo sysctl -w net.core.wmem_max=<new value> + +Set the values permanently by editing `/etc/sysctl.conf`. + +\subsection transport_udp_windows Windows specific notes + +**UDP send fast-path:** It is important to change the default UDP +behavior such that 1500 byte packets still travel through the fast path +of the sockets stack. This can be adjusted with the +FastSendDatagramThreshold registry key: + +- FastSendDatagramThreshold registry key documented here: + + - <http://www.microsoft.com/windows/windowsmedia/howto/articles/optimize_web.aspx#appendix_e> + +- Double click and run + `<install-path>/share/uhd/FastSendDatagramThreshold.reg` +- A system reboot is recommended after the registry key change. + +<b>Power profile:</b> The Windows power profile can seriously impact +instantaneous bandwidth. Application can take time to ramp-up to full +performance capability. It is recommended that users set the power +profile to "high performance". + +\section transport_usb USB Transport (LibUSB) + +The USB transport is implemented with LibUSB. LibUSB provides an +asynchronous API for USB bulk transfers. + +\subsection transport_usb_params Transport parameters + +The following parameters can be used to alter the transport's default +behavior: + +- `recv_frame_size:` The size of a single receive transfers in + bytes +- `num_recv_frames:` The number of simultaneous receive transfers +- `send_frame_size:` The size of a single send transfers in bytes +- `num_send_frames:` The number of simultaneous send transfers + +\subsection transport_usb_udev Setup Udev for USB (Linux) + +On Linux, Udev handles USB plug and unplug events. The following +commands install a Udev rule so that non-root users may access the +device: + + cd <install-path>/lib/uhd/utils + sudo cp uhd-usrp.rules /etc/udev/rules.d/ + sudo udevadm control --reload-rules + sudo udevadm trigger + +\subsection transport_usb_installwin Install USB driver (Windows) + +A driver package must be installed to use a USB-based product with UHD +software: + +- Download the driver from the UHD wiki page + <a href="http://files.ettus.com/binaries/misc/erllc_uhd_winusb_driver.zip">here</a>. +- Unzip the file into a known location. We will refer to this as the `<directory>`. +- Open the device manager and plug in the USRP device. You will see an + unrecognized USB device in the device manager. +- Right click on the unrecognized USB device and select update/install + driver software (may vary for your OS). +- In the driver installation wizard, select "browse for driver", + browse to the `<directory>`, and select the `.inf` file. +- Continue through the installation wizard until the driver is + installed. + +*/ +// vim:ft=doxygen: diff --git a/host/docs/transport.rst b/host/docs/transport.rst deleted file mode 100644 index 88f787893..000000000 --- a/host/docs/transport.rst +++ /dev/null @@ -1,165 +0,0 @@ -======================================================================== -UHD - Transport Application Notes -======================================================================== - -.. contents:: Table of Contents - ------------------------------------------------------------------------- -Introduction ------------------------------------------------------------------------- -A transport is the layer between the packet interface and a device IO -interface. The advanced user can pass optional parameters into the underlying -transport layer through the device address. These optional parameters control -how the transport object allocates memory, resizes kernel buffers, spawns -threads, etc. When not spcified, the transport layer will use values for these -parameters that are known to perform well on a variety of systems. The -transport parameters are defined below for the various transports in the UHD -software: - ------------------------------------------------------------------------- -UDP Transport (Sockets) ------------------------------------------------------------------------- -The UDP transport is implemented with user-space sockets. -This means standard Berkeley sockets API using send()/recv(). - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Transport parameters -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The following parameters can be used to alter the transport's default behavior: - -* **recv_frame_size:** The size of a single receive buffer in bytes -* **num_recv_frames:** The number of receive buffers to allocate -* **send_frame_size:** The size of a single send buffer in bytes -* **num_send_frames:** The number of send buffers to allocate - -**Note1:** -**num_recv_frames** does not affect performance. - -**Note2:** -**num_send_frames** does not affect performance. - -**Note3:** -**recv_frame_size** and **send_frame_size** can be used to -increase or decrease the maximum number of samples per packet. -The frame sizes default to an MTU of 1472 bytes per IP/UDP packet -and may be increased if permitted by your network hardware. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Flow control parameters -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The host-based flow control expects periodic update packets from the device. -These update packets inform the host of the last packet consumed by the device, -which allows the host to determine throttling conditions for the transmission of packets. -The following mechanisms affect the transmission of periodic update packets: - -* **ups_per_fifo:** The number of update packets for each FIFO's worth of bytes sent into the device -* **ups_per_sec:** The number of update packets per second (defaults to 20 updates per second) - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Resize socket buffers -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -It may be useful to increase the size of the socket buffers to -move the burden of buffering samples into the kernel or to -buffer incoming samples faster than they can be processed. -However, if your application cannot process samples fast enough, -no amount of buffering can save you. -The following parameters can be used to alter socket's buffer sizes: - -* **recv_buff_size:** The desired size of the receive buffer in bytes -* **send_buff_size:** The desired size of the send buffer in bytes - -**Note:** Large send buffers tend to decrease transmit performance. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Latency Optimization -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Latency is a measurement of the time it takes a sample to travel between the host and device. -Most computer hardware and software is bandwidth optimized, which may negatively affect latency. -If your application has strict latency requirements, please consider the following notes: - -**Note1:** -The time taken by the device to populate a packet is proportional to the sample rate. -Therefore, to improve receive latency, configure the transport for a smaller frame size. - -**Note2:** -For overall latency improvements, -look for "Interrupt Coalescing" settings for your OS and ethernet chipset. -It seems the Intel ethernet chipsets offer fine-grained control in Linux. -Also, consult: - -* http://publib.boulder.ibm.com/infocenter/pseries/v5r3/index.jsp?topic=/com.ibm.aix.prftungd/doc/prftungd/interrupt_coal.htm - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Linux specific notes -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -On Linux, the maximum buffer sizes are capped by the sysctl values -**net.core.rmem_max** and **net.core.wmem_max**. -To change the maximum values, run the following commands: -:: - - sudo sysctl -w net.core.rmem_max=<new value> - sudo sysctl -w net.core.wmem_max=<new value> - -Set the values permanently by editing **/etc/sysctl.conf**. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Windows specific notes -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -**UDP send fast-path:** -It is important to change the default UDP behavior such that -1500 byte packets still travel through the fast path of the sockets stack. -This can be adjusted with the FastSendDatagramThreshold registry key: - -* FastSendDatagramThreshold registry key documented here: - - * http://www.microsoft.com/windows/windowsmedia/howto/articles/optimize_web.aspx#appendix_e - -* Double click and run <install-path>/share/uhd/FastSendDatagramThreshold.reg -* A system reboot is recommended after the registry key change. - -**Power profile:** -The Windows power profile can seriously impact instantaneous bandwidth. -Application can take time to ramp-up to full performance capability. -It is recommended that users set the power profile to "high performance". - ------------------------------------------------------------------------- -USB Transport (LibUSB) ------------------------------------------------------------------------- -The USB transport is implemented with LibUSB. -LibUSB provides an asynchronous API for USB bulk transfers. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Transport parameters -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The following parameters can be used to alter the transport's default behavior: - -* **recv_frame_size:** The size of a single receive transfers in bytes -* **num_recv_frames:** The number of simultaneous receive transfers -* **send_frame_size:** The size of a single send transfers in bytes -* **num_send_frames:** The number of simultaneous send transfers - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Setup Udev for USB (Linux) -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -On Linux, Udev handles USB plug and unplug events. -The following commands install a Udev rule -so that non-root users may access the device: - -:: - - cd <install-path>/lib/uhd/utils - sudo cp uhd-usrp.rules /etc/udev/rules.d/ - sudo udevadm control --reload-rules - sudo udevadm trigger - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Install USB driver (Windows) -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -A driver package must be installed to use a USB-based product with UHD software: - -* Download the driver from the UHD wiki page `here <http://files.ettus.com/binaries/misc/erllc_uhd_winusb_driver.zip>`_. -* Unzip the file into a known location. We will refer to this as the **<directory>**. -* Open the device manager and plug in the USRP device. You will see an unrecognized USB device in the device manager. -* Right click on the unrecognized USB device and select update/install driver software (may vary for your OS). -* In the driver installation wizard, select "browse for driver", browse to the **<directory>**, and select the **.inf** file. -* Continue through the installation wizard until the driver is installed. diff --git a/host/docs/uhd_find_devices.1 b/host/docs/uhd_find_devices.1 index 405111a00..dfd5c0751 100644 --- a/host/docs/uhd_find_devices.1 +++ b/host/docs/uhd_find_devices.1 @@ -2,7 +2,7 @@ .SH NAME uhd_find_devices \- USRP Hardware Driver Discovery Utility .SH DESCRIPTION -Find UHD-supporting Software Radio Peripherals attached by USB, +Find UHD-supporting Ettus Research products attached by USB, network or embedded configuration. .LP The UHD package is the universal hardware driver for Ettus Research @@ -16,7 +16,7 @@ the UHD driver standalone or with 3rd party applications. --args \fIarg\fR .IP "This help information:" --help -.SH IDENTIFYING USRP DEVICES +.SH IDENTIFYING DEVICES .sp Devices are addressed through key/value string pairs. These string pairs can be used to narrow down the search for a specific device or group of devices. @@ -28,36 +28,42 @@ Every device has several ways of identifying it on the host system. .SS Identifying by hardware identifier .sp -All USRP devices can be found through their hardware series identifier, which match to USRP +All Ettus Research devices can be found through their hardware series identifier, which match to devices as follows: -Argument | Device +Argument | Device -type=usrp1 | USRP1 +type=usrp1 | USRP1 -type=usrp2 | USRP2, USRP N200, USRP N210 +type=usrp2 | USRP2, USRP N200, USRP N210 -type=b100 | USRP B100 +type=b100 | USRP B100 -type=e100 | USRP E100, USRP E110 +type=b200 | USRP B200, USRP B210 + +type=e100 | USRP E100, USRP E110 + +type=x300 | USRP X300, USRP X310 + +type=octoclock | OctoClock .SS Identifying by serial number -All USRP devices are given a unique serial number, which can be used to identify a device as follows: +All Ettus Research devices are given a unique serial number, which can be used to identify a device as follows: serial=12345678 .SS Identifying by IP address -USRP2, USRP N200, and USRP N210 devices connected to the host machine can all be found through their +USRP2, USRP N200, USRP N210, USRP X300, USRP X310, and OctoClock devices connected to the host machine can all be found through their IP addresses, as follows: addr=192.168.10.2 .SS Identifying by name -Users have the option of giving their USRP devices short names using the usrp_burn_mb_eeprom utility -in lib/uhd/utils. Devices that have been given a name can be identified as follows: +Users have the option of giving their devices short names using the usrp_burn_mb_eeprom and octoclock_burn_eeprom +utilities in lib/uhd/utils. Devices that have been given a name can be identified as follows: name=foo diff --git a/host/docs/uhd_images_downloader.1 b/host/docs/uhd_images_downloader.1 index e6cd7d978..19f109ec5 100644 --- a/host/docs/uhd_images_downloader.1 +++ b/host/docs/uhd_images_downloader.1 @@ -33,7 +33,7 @@ GR-UHD documentation: .LP Other UHD programs: .sp -usrp2_card_burner(1) usrp_n2xx_simple_net_burner(1) +usrp2_card_burner(1) usrp_n2xx_simple_net_burner(1) usrp_x3xx_fpga_burner(1) octoclock_firmware_burner(1) .SH AUTHOR This manual page was written by Maitland Bottoms and Nicholas Corgan for the Debian project (but may be used by others). diff --git a/host/docs/uhd_usrp_probe.1 b/host/docs/uhd_usrp_probe.1 index d26408ce6..178027aea 100644 --- a/host/docs/uhd_usrp_probe.1 +++ b/host/docs/uhd_usrp_probe.1 @@ -47,8 +47,12 @@ type=usrp2 | USRP2, USRP N200, USRP N210 type=b100 | USRP B100 +type=b200 | USRP B200, USRP B210 + type=e100 | USRP E100, USRP E110 +type=x300 | USRP X300, USRP X310 + .SS Identifying by serial number All USRP devices are given a unique serial number, which can be used to identify a device as follows: @@ -57,7 +61,7 @@ serial=12345678 .SS Identifying by IP address -USRP2, USRP N200, and USRP N210 devices connected to the host machine can all be found through their +USRP2, USRP N200, USRP N210, USRP X300, and USRP X310 devices connected to the host machine can all be found through their IP addresses, as follows: addr=192.168.10.2 diff --git a/host/docs/usrp1.dox b/host/docs/usrp1.dox new file mode 100644 index 000000000..9dfdf02c5 --- /dev/null +++ b/host/docs/usrp1.dox @@ -0,0 +1,95 @@ +/*! \page page_usrp1 USRP1 Device Manual + +\tableofcontents + +\section usrp1_features Comparative features list + +- Hardware Capabilities: + - 2 transceiver card slots + - 64 MHz fixed clock rate +- FPGA Capabilities: + - 2 RX DDC chains in FPGA + - 2 TX DUC chains in FPGA (no TX CORDIC -\> uses DAC) + - sc16 sample modes - RX & TX + - Up to 8 MHz of RF BW with 16-bit samples + - sc8 sample mode - RX only + - Up to 16 MHz of RF BW with 8-bit samples + +\section usrp1_imgs Specify a Non-standard Image + +The standard USRP1 images installer comes with two FPGA images: +- **usrp1_fpga.rbf:** 2 DDCs + 2 DUCs +- **usrp1_fpga_4rx.rbf:** 4 DDCs + 0 DUCs + +By default, the USRP1 uses the FPGA image with 2 DDCs and 2 DUCs. +However, a device address parameter can be used to override the FPGA +image selection to use an alternate or a custom FPGA image. See the +images application notes for installing custom images. + +Example device address string representations to specify non-standard +firmware and/or FPGA images: + + fpga=usrp1_fpga_4rx.rbf + + -- OR -- + + fw=usrp1_fw_custom.ihx + + -- OR -- + + fpga=usrp1_fpga_4rx.rbf, fw=usrp1_fw_custom.ihx + +\section usrp1_emul Missing and Emulated Features + +The USRP1 FPGA does not have the necessary space to support the advanced +streaming capabilities that are possible with the newer USRP devices. +Some of these features are emulated in software to support the API. + +\subsection usrp1_emul_list List of emulated features + +- Setting the current device time +- Getting the current device time +- Transmitting at a specific time +- Transmitting a specific number of samples +- Receiving at a specific time +- Receiving a specific number of samples +- End of burst flags for transmit/receive +- Notification on late stream command +- Notification on late transmit packet +- Notification on underflow or overflow +- Notification on broken chain error + +<b>Note:</b> These emulated features rely on the host system's clock for +timed operations and therefore may not have sufficient precision for the +application. + +\subsection usrp1_emul_listmissing List of missing features + +- Start of burst flags for transmit/receive + +\section usrp1_hw Hardware Setup Notes + +\subsection usrp1_hw_extclk External clock modification + +The USRP device can be modified to accept an external clock reference instead of the 64MHz onboard reference. + - Solder SMA (**LTI-SASF54GT**) connector to **J2001**. + - Move 0 ohm 0603 resistor **R2029** to **R2030**. + - Move 0.01uF 0603 capacitor **C925** to **C926**. + - Remove 0.01uF 0603 capacitor **C924**. + +The new external clock needs to be a square wave between +7dBm and +15dBm. + +After the hardware modification, the user should burn the setting into +the EEPROM, so UHD software can initialize with the correct clock rate. +Run the following commands to record the setting into the EEPROM: + + cd <install-path>/lib/uhd/utils + ./usrp_burn_mb_eeprom --args=<optional device args> --values="mcr=<rate>" + +The user may override the clock rate specified in the EEPROM by using a +device address: Example: + + uhd_usrp_probe --args="mcr=52e6" + +*/ +// vim:ft=doxygen: diff --git a/host/docs/usrp1.rst b/host/docs/usrp1.rst index be74fe00a..ecf90502b 100644 --- a/host/docs/usrp1.rst +++ b/host/docs/usrp1.rst @@ -102,7 +102,7 @@ Run the following commands to record the setting into the EEPROM: :: cd <install-path>/lib/uhd/utils - ./usrp_burn_mb_eeprom --args=<optional device args> --key=mcr --val=<rate> + ./usrp_burn_mb_eeprom --args=<optional device args> --values="mcr=<rate>" The user may override the clock rate specified in the EEPROM by using a device address: Example: diff --git a/host/docs/usrp2.dox b/host/docs/usrp2.dox new file mode 100644 index 000000000..e1be733c0 --- /dev/null +++ b/host/docs/usrp2.dox @@ -0,0 +1,424 @@ +/*! \page page_usrp2 USRP2 and N2x0 Series Device Manual + +\tableofcontents + +\section usrp2_features Comparative features list + +- Hardware Capabilities: + - 1 transceiver card slot + - External PPS reference input + - External 10 MHz reference input + - MIMO cable shared reference + - Fixed 100 MHz clock rate + - Internal GPSDO option (N2x0 only) +- FPGA Capabilities: + - 2 RX DDC chains in FPGA + - 1 TX DUC chain in FPGA + - Timed commands in FPGA (N2x0 only) + - Timed sampling in FPGA + - 16-bit and 8-bit sample modes (sc8 and sc16) + - Up to 25 MHz of RF BW with 16-bit samples + - Up to 50 MHz of RF BW with 8-bit samples + +\section usrp2_load Load the Images onto the SD card (USRP2 only) + +<b>Warning!</b> Use `usrp2_card_burner` with caution. If you specify +the wrong device node, you could overwrite your hard drive. Make sure +that `--dev=` specifies the SD card. + +<b>Warning!</b> It is possible to use 3rd party SD cards with the USRP2. +However, certain types of SD cards will not interface with the CPLD: + +- Cards can be SDHC, which is not a supported interface. +- Cards can have unexpected timing characteristics. + +For these reasons, we recommend that you use the SD card that was +supplied with the USRP2. + +\subsection usrp2_load_cardburner Use the card burner tool (UNIX) + + sudo <install-path>/lib/uhd/utils/usrp2_card_burner_gui.py + + -- OR -- + + cd <install-path>/lib/uhd/utils + sudo ./usrp2_card_burner.py --dev=/dev/sd<XXX> --fpga=<path_to_fpga_image> + sudo ./usrp2_card_burner.py --dev=/dev/sd<XXX> --fw=<path_to_firmware_image> + +Use the `--list` option to get a list of possible raw devices. The +list result will filter out disk partitions and devices too large to be +the sd card. The list option has been implemented on Linux, Mac OS X, +and Windows. + +\subsection usrp2_load_cardburnerwin Use the card burner tool (Windows) + + <path_to_python.exe> <install-path>/lib/uhd/utils/usrp2_card_burner_gui.py + +\section usrp2_loadflash Load the Images onto the On-board Flash (USRP-N Series only) + +The USRP-N Series can be reprogrammed over the network to update or +change the firmware and FPGA images. When updating images, always burn +both the FPGA and firmware images before power cycling. This ensures +that when the device reboots, it has a compatible set of images to boot +into. + +\subsection usrp2_loadflash_netburner Use the net burner tool + +Use default images: + + usrp_n2xx_simple_net_burner --addr=<IP address> + +Use custom-built images: + + usrp_n2xx_simple_net_burner --addr=<IP address> --fw=<firmware path> --fpga=<FPGA path> + +<b>Note:</b> Different hardware revisions require different FPGA images. +Determine the revision number from the sticker on the rear of the +chassis. Use this number to select the correct FPGA image for your +device. + +For users who would prefer a graphical utility, a Python-based +alternative exists. + +\subsection usrp2_loadflash_gui Use the graphical net burner tool (Linux) + + <install-path>/lib/uhd/utils/usrp_n2xx_net_burner_gui.py + +\subsection usrp2_loadflash_guiwin Use the graphical net burner tool (Windows) + + <path_to_python.exe> <install-path>/lib/uhd/utils/usrp_n2xx_net_burner_gui.py + +\subsection usrp2_loadflash_brick Device recovery and bricking + +Its possible to put the device into an unusable state by loading bad +images. Fortunately, the USRP-N Series can be booted into a safe +(read-only) image. Once booted into the safe image, the user can once +again load images onto the device. + +The safe-mode button is a pushbutton switch (S2) located inside the +enclosure. To boot into the safe image, hold-down the safe-mode button +while power-cycling the device. Continue to hold-down the button until +the front-panel LEDs blink and remain solid. + +When in safe-mode, the USRP-N device will always have the IP address **192.168.10.2**. + +\section usrp2_network Setup Networking + +The USRP2 only supports Gigabit Ethernet and will not work with a 10/100 +Mbps interface. However, a 10/100 Mbps interface can be connected +indirectly to a USRP2 through a Gigabit Ethernet switch. + +\subsection usrp2_network_setuphost Setup the host interface + +The USRP2 communicates at the IP/UDP layer over the gigabit ethernet. +The default IP address of the USRP2 is **192.168.10.2**. You will need +to configure the host's Ethernet interface with a static IP address to +enable communication. An address of **192.168.10.1** and a subnet mask +of **255.255.255.0** is recommended. + +On a Linux system, you can set a static IP address very easily by using +the 'ifconfig' command: + + sudo ifconfig <interface> 192.168.10.1 + +Note that `interface` is usually something like **eth0**. You can +discover the names of the network interfaces in your computer by running **ifconfig** +without any parameters: + + ifconfig -a + +<b>Note:</b> When using UHD software, if an IP address for the USRP2 is not +specified, the software will use UDP broadcast packets to locate the +USRP2. On some systems, the firewall will block UDP broadcast packets. +It is recommended that you change or disable your firewall settings. + +\subsection usrp2_network_multidev Multiple devices per host + +For maximum throughput, one Ethernet interface per USRP2 is recommended, +although multiple devices may be connected via a Gigabit Ethernet +switch. In any case, each Ethernet interface should have its own subnet, +and the corresponding USRP2 device should be assigned an address in that +subnet. Example: + +- Configuration for USRP2 device 0: + - Ethernet interface IPv4 address: **192.168.10.1** + - Ethernet interface subnet mask: **255.255.255.0** + - USRP2 device IPv4 address: **192.168.10.2** + +- Configuration for USRP2 device 1: + - Ethernet interface IPv4 address: **192.168.20.1** + - Ethernet interface subnet mask: **255.255.255.0** + - USRP2 device IPv4 address: **192.168.20.2** + +\subsection usrp2_network_changeip Change the USRP2's IP address + +You may need to change the USRP2's IP address for several reasons: +- to satisfy your particular network configuration +- to use multiple USRP2s on the same host computer +- to set a known IP address into USRP2 (in case you forgot) + +#### Method 1 + +To change the USRP2's IP address, you must know the +current address of the USRP2, and the network must be setup properly as +described above. Run the following commands: : + + cd <install-path>/lib/uhd/utils + ./usrp_burn_mb_eeprom --args=<optional device args> --values="ip-addr=192.168.10.3" + +#### Method 2 (Linux Only) + +This method assumes that you do not know the +IP address of your USRP2. It uses raw Ethernet packets to bypass the +IP/UDP layer to communicate with the USRP2. Run the following commands: + + cd <install-path>/lib/uhd/utils + sudo ./usrp2_recovery.py --ifc=eth0 --new-ip=192.168.10.3 + +\section usrp2_commprob Communication Problems + +When setting up a development machine for the first time, you may have +various difficulties communicating with the USRP device. The following +tips are designed to help narrow down and diagnose the problem. + +\subsection usrp2_commprob_ctrlresponse RuntimeError: no control response + +This is a common error that occurs when you have set the subnet of your +network interface to a different subnet than the network interface of +the USRP device. For example, if your network interface is set to **192.168.20.1**, +and the USRP device is **192.168.10.2** (note the +difference in the third numbers of the IP addresses), you will likely +see a 'no control response' error message. + +Fixing this is simple - just set the your host PC's IP address to the +same subnet as that of your USRP device. Instructions for setting your +IP address are in the previous section of this documentation. + +\subsection usrp2_commprob_firewall Firewall issues + +When the IP address is not specified, the device discovery broadcasts +UDP packets from each ethernet interface. Many firewalls will block the +replies to these broadcast packets. If disabling your system's firewall +or specifying the IP address yields a discovered device, then your +firewall may be blocking replies to UDP broadcast packets. If this is +the case, we recommend that you disable the firewall or create a rule to +allow all incoming packets with UDP source port **49152**. + +\subsection usrp2_commprob_ping Ping the device + +The USRP device will reply to ICMP echo requests. A successful ping +response means that the device has booted properly and that it is using +the expected IP address. + + ping 192.168.10.2 + +\subsection usrp2_commprob_uart Monitor the serial output + +Read the serial port to get debug verbose output from the embedded +microcontroller. The microcontroller prints useful information about IP +addresses, MAC addresses, control packets, fast-path settings, and +bootloading. Use a standard USB to 3.3v-level serial converter at 230400 +baud. Connect **GND** to the converter ground, and connect **TXD** to +the converter receive. The **RXD** pin can be left unconnected as this +is only a one-way communication. + +- **USRP2:** Serial port located on the rear edge +- **N210:** Serial port located on the left side + +\subsection usrp2_commprob_wireshark Monitor the host network traffic + +Use Wireshark to monitor packets sent to and received from the device. + +\section usrp2_addr Addressing the Device + +\subsection usrp2_addr_single Single device configuration + +In a single-device configuration, the USRP device must have a unique +IPv4 address on the host computer. The USRP can be identified through +its IPv4 address, resolvable hostname, or by other means. See the +application notes on \ref page_identification. +Please note that this addressing scheme should also be used with the **multi_usrp** +interface. + +Example device address string representation for a USRP2 with IPv4 +address **192.168.10.2**: + + addr=192.168.10.2 + +\subsection usrp2_ Multiple device configuration + +In a multi-device configuration, each USRP device must have a unique +IPv4 address on the host computer. The device address parameter keys +must be suffixed with the device index. Each parameter key should be of +the format \<key\>\<index\>. Use this addressing scheme with the uhd::usrp::multi_usrp +interface. + +- The order in which devices are indexed corresponds to the indexing + of the transmit and receive channels. +- The key indexing provides the same granularity of device + identification as in the single device case. + +Example device address string representation for 2 USRP2s with IPv4 +addresses **192.168.10.2** and **192.168.20.2**: + + addr0=192.168.10.2, addr1=192.168.20.2 + +\section usrp2_mimocable Using the MIMO Cable + +The MIMO cable allows two USRP devices to share reference clocks, time +synchronization, and the Ethernet interface. One of the devices will +sync its clock and time references to the MIMO cable. This device will +be referred to as the slave, and the other device, the master. + +- The slave device acquires the clock and time references from the + master device. +- The master and slave may be used individually or in a multi-device + configuration. +- External clocking is optional and should only be supplied to the + master device. + +\subsection usrp2_mimocable_shared Shared Ethernet mode + +In shared Ethernet mode, only one device in the configuration can be +attached to the Ethernet. + +- Clock reference, time reference, and data are communicated over the + MIMO cable. +- Master and slave must have different IPv4 addresses in the same + subnet. + +\subsection usrp2_mimocable_dual Dual Ethernet mode + +In dual Ethernet mode, both devices in the configuration must be +attached to the Ethernet. + +- Only clock reference and time reference are communicated over the + MIMO cable. +- The master and slave must have different IPv4 addresses in different + subnets. + +\subsection usrp2_mimocable_cfgslave Configuring the slave + +In order for the slave to synchronize to the master over MIMO cable, the +following clock configuration must be set on the slave device: : + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} + usrp->set_time_source("mimo", slave_index); + usrp->set_clock_source("mimo", slave_index); +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +\section usrp2_altstream Alternative stream destination + +It is possible to program the USRP device to send RX packets to an +alternative IP/UDP destination. + +\subsection usrp2_altstream_subnet Set the subnet and gateway + +To use an alternative streaming destination, the device needs to be able +to determine if the destination address is within its subnet, and ARP +appropriately. Therefore, the user should ensure that subnet and gateway +addresses have been programmed into the device's EEPROM. + +Run the following commands: + + cd <install-path>/lib/uhd/utils + ./usrp_burn_mb_eeprom --args=<optional device args> --values="subnet=255.255.255.0, gateway=192.168.10.2" + +\subsection usrp2_altstream_rxstream Create a receive streamer + +Set the stream args "addr" and "port" values to the alternative +destination. Packets will be sent to this destination when the user +issues a stream command. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} + //create a receive streamer, host type does not matter + uhd::stream_args_t stream_args("fc32"); + + //resolvable address and port for a remote udp socket + stream_args.args["addr"] = "192.168.10.42"; + stream_args.args["port"] = "12345"; + + //create the streamer + uhd::rx_streamer::sptr rx_stream = usrp->get_rx_stream(stream_args); + + //issue stream command + uhd::stream_cmd_t stream_cmd(uhd::stream_cmd_t::STREAM_MODE_NUM_SAMPS_AND_DONE); + stream_cmd.num_samps = total_num_samps; + stream_cmd.stream_now = true; + usrp->issue_stream_cmd(stream_cmd); +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +<b>Note:</b> Calling `recv()` on this streamer object should yield a timeout. + +\section usrp2_hw Hardware Setup Notes + +\subsection usrp2_hw_leds Front panel LEDs + +The LEDs on the front panel can be useful in debugging hardware and +software issues. The LEDs reveal the following about the state of the +device: + +- **LED A:** transmitting +- **LED B:** MIMO cable link +- **LED C:** receiving +- **LED D:** firmware loaded +- **LED E:** reference lock +- **LED F:** CPLD loaded + +\subsection usrp2_hw_refclk Ref Clock - 10 MHz + +Using an external 10 MHz reference clock, a square wave will offer the +best phase noise performance, but a sinusoid is acceptable. The +reference clock requires the following power level: + +- **USRP2** 5 to 15 dBm +- **N2XX** 0 to 15 dBm + +\subsection usrp2_hw_pps PPS - Pulse Per Second + +Using a PPS signal for timestamp synchronization requires a square wave +signal with the following amplitude: + +- **USRP2** 5Vpp +- **N2XX** 3.3 to 5Vpp + +Test the PPS input with the following app: + +- `<args>` are device address arguments (optional if only one USRP + device is on your machine) + + cd <install-path>/lib/uhd/examples + ./test_pps_input --args=\<args\> + +\subsection usrp2_hw_gpsdo Internal GPSDO + +Please see \ref page_gpsdo for information on configuring and using the internal GPSDO. + +\section usrp2_misc Miscellaneous + +\subsection usrp2_misc_sensors Available Sensors + +The following sensors are available for the USRP2/N-Series motherboards; +they can be queried through the API. + +- **mimo_locked** - clock reference locked over the MIMO cable +- **ref_locked** - clock reference locked (internal/external) +- other sensors are added when the GPSDO is enabled + +\subsection usrp2_misc_multirx Multiple RX channels + +There are two complete DDC chains in the FPGA. In the single channel +case, only one chain is ever used. To receive from both channels, the +user must set the **RX** subdevice specification. This hardware has only +one daughterboard slot, which has been aptly named slot **A**. + +In the following example, a TVRX2 is installed. Channel 0 is sourced +from subdevice **RX1**, and channel 1 is sourced from subdevice **RX2** +(**RX1** and **RX2** are the antenna ports on the TVRX2 daughterboard): + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} + usrp->set_rx_subdev_spec("A:RX1 A:RX2"); +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +*/ +// vim:ft=doxygen: diff --git a/host/docs/usrp2.rst b/host/docs/usrp2.rst index 361d98f01..1070a23fc 100644 --- a/host/docs/usrp2.rst +++ b/host/docs/usrp2.rst @@ -192,7 +192,7 @@ Run the following commands: :: cd <install-path>/lib/uhd/utils - ./usrp_burn_mb_eeprom --args=<optional device args> --key=ip-addr --val=192.168.10.3 + ./usrp_burn_mb_eeprom --args=<optional device args> --values="ip-addr=192.168.10.3" **Method 2 (Linux Only):** This method assumes that you do not know the IP address of your USRP2. @@ -360,8 +360,7 @@ Run the following commands: :: cd <install-path>/lib/uhd/utils - ./usrp_burn_mb_eeprom --args=<optional device args> --key=subnet --val=255.255.255.0 - ./usrp_burn_mb_eeprom --args=<optional device args> --key=gateway --val=192.168.10.1 + ./usrp_burn_mb_eeprom --args=<optional device args> --values="subnet=255.255.255.0,gateway=192.168.10.1" ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Create a receive streamer diff --git a/host/docs/usrp_b100.dox b/host/docs/usrp_b100.dox new file mode 100644 index 000000000..c61d17f02 --- /dev/null +++ b/host/docs/usrp_b100.dox @@ -0,0 +1,96 @@ +/*! \page page_usrp_b100 USRP-B100 Series Device Manual + +\tableofcontents + +\section b100_features Comparative features list + +- Hardware Capabilities: + - 1 transceiver card slot + - External PPS reference input + - External 10 MHz reference input + - Configurable clock rate (defaults 64 MHz) +- FPGA Capabilities: + - 1 RX DDC chain in FPGA + - 1 TX DUC chain in FPGA + - Timed commands in FPGA + - Timed sampling in FPGA + - sc8 and sc16 sample modes + - Up to 8 MHz of RF BW with 16-bit samples + - Up to 16 MHz of RF BW with 8-bit samples + +\section b100_imgs Specify a Non-standard Image + +UHD software will automatically select the USRP B100 images from the +installed images package. The image selection can be overridden with the +`--fpga=` and `--fw=` device address parameters. + +Example device address string representations to specify non-standard +images: + + fpga=usrp_b100_fpga_2rx.bin + + -- OR -- + + fw=usrp_b100_fw.ihx + +\section b100_mcr Changing the Master Clock Rate + +The master clock rate of the B100 feeds both the FPGA DSP and the codec +chip. Hundreds of rates between 32 MHz and 64 MHz are available. A few +notable rates are: + +- **64 MHz:** maximum rate of the codec chip +- **61.44 MHz:** good for UMTS/WCDMA applications +- **52 MHz:** good for GSM applications + +\subsection b100_mcr_vcxo Set 61.44 MHz - uses external VCXO + +To use the 61.44 MHz clock rate, the USRP embedded will require one +jumper to be moved, and X4 must be populated with a 61.44 MHz +oscillator. + +- **J15** is a three pin header, move the jumper to (pin1, pin2) +- **357LB3I061M4400** is the recommended oscillator for X4 + +<b>Note:</b> See instructions below to communicate the desired clock rate +into UHD software. + +\subsection b100_mcr_vco Set other rates - uses internal VCO + +To use other clock rates, the jumper will need to be in the default +position. + +- **J15** is a three pin header, move the jumper to (pin2, pin3) + +To communicate the desired clock rate into UHD software, specify the +special device address argument, where the key is +**master_clock_rate** and the value is a rate in Hz. Example: : + + uhd_usrp_probe --args="master_clock_rate=52e6" + +\section b100_hw Hardware setup notes + +\subsection b100_hw_leds Front panel LEDs + +The LEDs on the front panel can be useful in debugging hardware and +software issues. The LEDs reveal the following about the state of the +device: + +- **LED A:** transmitting +- **LED B:** FPGA loaded +- **LED C:** receiving +- **LED D:** FPGA loaded +- **LED E:** reference lock +- **LED F:** board power + +\section b100_misc Miscellaneous + +\subsection b100_misc_sensors Available Sensors + +The following sensors are available; they can be queried through the +API. + +- **ref_locked:** clock reference locked (internal/external) + +*/ +// vim:ft=doxygen: diff --git a/host/docs/usrp_b100.rst b/host/docs/usrp_b100.rst deleted file mode 100644 index 223ad5a90..000000000 --- a/host/docs/usrp_b100.rst +++ /dev/null @@ -1,107 +0,0 @@ -======================================================================== -UHD - USRP-B100 Series Device Manual -======================================================================== - -.. contents:: Table of Contents - ------------------------------------------------------------------------- -Comparative features list ------------------------------------------------------------------------- - -**Hardware Capabilities:** - * 1 transceiver card slot - * External PPS reference input - * External 10 MHz reference input - * Configurable clock rate (defaults 64 MHz) - -**FPGA Capabilities:** - * 1 RX DDC chain in FPGA - * 1 TX DUC chain in FPGA - * Timed commands in FPGA - * Timed sampling in FPGA - * sc8 and sc16 sample modes - - * Up to 8 MHz of RF BW with 16-bit samples - * Up to 16 MHz of RF BW with 8-bit samples - ------------------------------------------------------------------------- -Specify a Non-standard Image ------------------------------------------------------------------------- -UHD software will automatically select the USRP B100 images from the installed images package. -The image selection can be overridden with the **--fpga=** and **--fw=** device address parameters. - -Example device address string representations to specify non-standard images: - -:: - - fpga=usrp_b100_fpga_2rx.bin - - -- OR -- - - fw=usrp_b100_fw.ihx - ------------------------------------------------------------------------- -Changing the Master Clock Rate ------------------------------------------------------------------------- -The master clock rate of the B100 feeds both the FPGA DSP and the codec chip. -Hundreds of rates between 32 MHz and 64 MHz are available. -A few notable rates are: - -* **64 MHz:** maximum rate of the codec chip -* **61.44 MHz:** good for UMTS/WCDMA applications -* **52 MHz:** good for GSM applications - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Set 61.44 MHz - uses external VCXO -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -To use the 61.44 MHz clock rate, the USRP embedded will require one jumper to be moved, -and X4 must be populated with a 61.44 MHz oscillator. - -* **J15** is a three pin header, move the jumper to (pin1, pin2) -* **357LB3I061M4400** is the recommended oscillator for X4 - -**Note:** See instructions below to communicate the desired clock rate into UHD software. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Set other rates - uses internal VCO -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -To use other clock rates, the jumper will need to be in the default position. - -* **J15** is a three pin header, move the jumper to (pin2, pin3) - -To communicate the desired clock rate into UHD software, -specify the special device address argument, -where the key is **master_clock_rate** and the value is a rate in Hz. -Example: -:: - - uhd_usrp_probe --args="master_clock_rate=52e6" - ------------------------------------------------------------------------- -Hardware setup notes ------------------------------------------------------------------------- - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Front panel LEDs -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The LEDs on the front panel can be useful in debugging hardware and software issues. -The LEDs reveal the following about the state of the device: - -* **LED A:** transmitting -* **LED B:** FPGA loaded -* **LED C:** receiving -* **LED D:** FPGA loaded -* **LED E:** reference lock -* **LED F:** board power - ------------------------------------------------------------------------- -Miscellaneous ------------------------------------------------------------------------- - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Available Sensors -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The following sensors are available; -they can be queried through the API. - -* **ref_locked:** clock reference locked (internal/external) diff --git a/host/docs/usrp_b200.dox b/host/docs/usrp_b200.dox new file mode 100644 index 000000000..93ea9b2c6 --- /dev/null +++ b/host/docs/usrp_b200.dox @@ -0,0 +1,167 @@ +/*! \page page_usrp_b200 USRP-B2x0 Series Device Manual + +\tableofcontents + +\section b200_features Comparative features list - B200 + +- Hardware Capabilities: + - Integrated RF frontend (70 MHz - 6 GHz) + - External PPS reference input + - External 10 MHz reference input + - Configurable clock rate + - Internal GPSDO option + - B210 Only: + - MICTOR Debug Connector + - JTAG Connector +- FPGA Capabilities: + - Timed commands in FPGA + - Timed sampling in FPGA + +\section b200_imgs Specify a Non-standard Image + +UHD software will automatically select the USRP B2X0 images from the +installed images package. The image selection can be overridden with the +`fpga` and `fw` device address parameters. + +Example device address string representations to specify non-standard +images: + + fpga=usrp_b200_fpga.bin + + -- OR -- + + fw=usrp_b200_fw.hex + +\section b200_mcr Changing the Master Clock Rate + +The master clock rate feeds the RF frontends and the DSP chains. Users +may select non-default clock rates to acheive integer decimations or +interpolations in the DSP chains. The default master clock rate defaults +to 32 MHz, but can be set to any rate between 5 MHz and 61.44 MHz. + +The user can set the master clock rate through the usrp API call +uhd::usrp::multi_usrp::set_master_clock_rate(), or the clock rate can be set through the +device arguments, which many applications take: : + + uhd_usrp_probe --args="master_clock_rate=52e6" + +\section b200_fe RF Frontend Notes + +The B200 features an integrated RF frontend. + +\subsection b200_fe_tuning Frontend tuning + +The RF frontend has individually tunable receive and transmit chains. On +the B200, there is one transmit and one receive RF frontend. On the +B210, both transmit and receive can be used in a MIMO configuration. For +the MIMO case, both receive frontends share the RX LO, and both transmit +frontends share the TX LO. Each LO is tunable between 50 MHz and 6 GHz. + +\subsection b200_fe_gain Frontend gain + +All frontends have individual analog gain controls. The receive +frontends have 73 dB of available gain; and the transmit frontends have +89.5 dB of available gain. Gain settings are application specific, but +it is recommended that users consider using at least half of the +available gain to get reasonable dynamic range. + +\section Hardware Reference + +\subsection LED Indicators + +Below is a table of the LED indicators and their meanings: + +<table> + <tr> + <th>Component ID</th><th>Description</th><th>Details</th> + </tr> + <tr> + <td>LED600</td> <td>Power Indicator</td> <td>off = no power applied<br> + red = power applied (external or USB)</td> + </tr> + <tr> + <td>LED800</td> <td>Channel 2 RX2 Activity</td> <td>off = no power applied<br> + green = receiving</td> + </tr> + <tr> + <td>LED801</td> <td>Channel 2 TX/RX Activity</td> <td>off = no activity<br> + green = receiving<br> + red = transmitting<br> + orange = switching between transmitting and receiving</td> + </tr> + <tr> + <td>LED802</td> <td>Channel 1 TX/RX Activity</td> <td>off = no activity + green = receiving<br> + red = transmitting<br> + orange = switching between transmitting and receiving</td> + </tr> + <tr> + <td>LED803</td> <td>Channel 1 RX2 Activity</td> <td>off = no power applied<br> + green = receiving</td> + </tr> + <tr> + <td>LED100</td> <td>GPS lock indicator</td> <td>off = no lock<br> + green = lock</td> + </tr> +</table> + +TX LED indicators are on when transimitting data and off when no samples are +available to transmit. RX LED indicators are on when sending samples to the +host and off when unable to do so. This means that TX/RX activity LED +indicators will blink off in a temporary transmit underflow or receive overflow +condition, indicating that the host is not sending or receiving samples fast +enough. The host will be notified of the condition and output a "U" or "O" as +well. + +\subsection External Connections + +Below is a table showing the external connections and respective power information: + +<table> +<tr> + <th>Component ID</th> <th>Description</th> <th> Details</th> +</tr> +<tr> + <td>J601</td> <td>External Power</td> <td>6 V<br>3 A</td> +</tr> +<tr> + <td>J701</td> <td>USB Connector</td> <td>USB 3.0</td> +</tr> +<tr> + <td>J104</td> <td>External PPS Input</td> <td>1.8 V - 5 V</td> +</tr> +<tr> + <td>J101</td> <td>GPS Antenna</td> <td>GPSDO will supply nominal voltage to antenna.</td> +</tr> +<tr> + <td>J100</td> <td>External 10 MHz Input</td> <td>+15 dBm max</td +</tr> +<tr> + <td>J800</td> <td>RF B: TX/RX</td> <td>TX power +20dBm max<br> + RX power -15dBm max</td> +</tr> +<tr> + <td>J802</td> <td>RF B: RX2</td> <td>RX power -15dBm max</td> +</tr> +<tr> + <td>J803</td> <td>RF A: RX2</td> <td>RX power -15dBm max</td> +</tr> +<tr> + <td>J801</td> <td>RF A: TX/RX</td> <td>TX power +20dBm max<br> + RX power -15dBm max</td> +</tr> +</table> + +\subsection b200_switches On-Board Connectors and Switches + +Below is a table showing the on-board connectors and switches: + +Component ID | Description | Details +--------------|----------------------------|---------------------------------------------------------- + J502* | Mictor Connector | Interface to FPGA for I/O and inspection. + J503* | JTAG Header | Interface to FPGA for programming and debugging. + S700 | FX3 Hard Reset Switch | - + +*/ + +// vim:ft=doxygen: diff --git a/host/docs/usrp_b200.rst b/host/docs/usrp_b200.rst deleted file mode 100644 index 327bbb6df..000000000 --- a/host/docs/usrp_b200.rst +++ /dev/null @@ -1,152 +0,0 @@ -======================================================================== -UHD - USRP-B2x0 Series Device Manual -======================================================================== - -.. contents:: Table of Contents - ------------------------------------------------------------------------- -Comparative features list - B200 ------------------------------------------------------------------------- - -**Hardware Capabilities:** - * Integrated RF frontend (70 MHz - 6 GHz) - * External PPS reference input - * External 10 MHz reference input - * Configurable clock rate - * Internal GPSDO option - * B210 Only: - - * MICTOR Debug Connector - * JTAG Connector - -**FPGA Capabilities:** - * Timed commands in FPGA - * Timed sampling in FPGA - ------------------------------------------------------------------------- -Specify a Non-standard Image ------------------------------------------------------------------------- -UHD software will automatically select the USRP B2X0 images from the installed images package. -The image selection can be overridden with the **fpga** and **fw** device address parameters. - -Example device address string representations to specify non-standard images: - -:: - - fpga=usrp_b200_fpga.bin - - -- OR -- - - fw=usrp_b200_fw.hex - ------------------------------------------------------------------------- -Changing the Master Clock Rate ------------------------------------------------------------------------- -The master clock rate feeds the RF frontends and the DSP chains. -Users may select non-default clock rates to acheive integer decimations or interpolations in the DSP chains. -The default master clock rate defaults to 32 MHz, but can be set to any rate between 5 MHz and 61.44 MHz. - -The user can set the master clock rate through the usrp API call set_master_clock_rate(), -or the clock rate can be set through the device arguments, which many applications take: -:: - - uhd_usrp_probe --args="master_clock_rate=52e6" - ------------------------------------------------------------------------- -RF Frontend Notes ------------------------------------------------------------------------- -The B200 features and integrated RF frontend. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Frontend tuning -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The RF frontend has individually tunable receive and transmit chains. -On the B200, there is one transmit and one receive RF frontend. -On the B210, both transmit and receive can be used in a MIMO configuration. -For the MIMO case, both receive frontends share the RX LO, -and both transmit frontends share the TX LO. -Each LO is tunable between 50 MHz and 6 GHz. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Frontend gain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -All frontends have individual analog gain controls. -The receive frontends have 73 dB of available gain; -and the transmit frontends have 89.5 dB of available gain. -Gain settings are application specific, -but it is recommended that users consider using at least -half of the available gain to get reasonable dynamic range. - ------------------------------------------------------------------------- -Hardware Reference ------------------------------------------------------------------------- - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -LED Indicators -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Below is a table of the LED indicators and their meanings: - -=============== ======================== ======================================================== -Component ID Description Details -=============== ======================== ======================================================== - LED600 Power Indicator | off = no power applied - | red = power applied (external or USB) - LED800 Channel 2 RX2 Activity | off = no activity - | green = receiving - LED801 Channel 2 TX/RX Activity | off = no activity - | green = receiving - | red = transmitting - | orange = switching between transmitting and receiving - LED802 Channel 1 TX/RX Activity | off = no activity - | green = receiving - | red = transmitting - | orange = switching between transmitting and receiving - LED803 Channel 1 RX2 Activity | off = no activity - | green = receiving - LED100 GPS lock indicator | off = no lock - | green = lock -=============== ======================== ======================================================== - -TX LED indicators are on when transimitting data and off when no samples are available to transmit. RX LED indicators are on when sending samples to the host and off when unable to do so. This means that TX/RX activity LED indicators will blink off in a temporary transmit underflow or receive overflow condition, indicating that the host is not sending or receiving samples fast enough. The host will be notified of the condition and output a "U" or "O" as well. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -External Connections -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Below is a table showing the external connections and respective power information: - -=============== ======================== ======================================================== -Component ID Description Details -=============== ======================== ======================================================== - J601 External Power | 6 V - | 3 A - J701 USB Connector | USB 3.0 - J104 External PPS Input | 1.8 V - 5 V - J101 GPS Antenna | GPSDO will supply nominal voltage to antenna. - J100 External 10 MHz Input | +15 dBm max - J800 RF B: TX/RX | TX power +20dBm max - | RX power -15dBm max - J802 RF B: RX2 | RX power -15dBm max - J803 RF A: RX2 | RX power -15dBm max - J801 RF A: TX/RX | TX power +20dBm max - | RX power -15dBm max -=============== ======================== ======================================================== - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -On-Board Connectors and Switches -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Below is a table showing the on-board connectors and switches: - -=============== ======================== ======================================================== -Component ID Description Details -=============== ======================== ======================================================== - J502* Mictor Connector | Interface to FPGA for I/O and inspection. - J503* JTAG Header | Interface to FPGA for programming and debugging. - S700 FX3 Hard Reset Switch -=============== ======================== ======================================================== - -\* B210 Only - - diff --git a/host/docs/usrp_e1x0.dox b/host/docs/usrp_e1x0.dox new file mode 100644 index 000000000..c73e6ed42 --- /dev/null +++ b/host/docs/usrp_e1x0.dox @@ -0,0 +1,136 @@ +/*! \page page_usrp_e1x0 USRP-E1x0 Series Device Manual + +\tableofcontents + +\section e1x0_features Comparative features list + +- Hardware Capabilities: + - 1 transceiver card slot + - Internal PPS reference input + - Internal 10 MHz reference input + - Configurable clock rate (defaults to 64 MHz) + - Internal GPSDO option +- FPGA Capabilities: + - 2 RX DDC chains in FPGA + - 1 TX DUC chain in FPGA + - Timed commands in FPGA + - Timed sampling in FPGA + - sc8 and sc16 sample modes + - Up to 8 MHz of RF BW with 16-bit samples + - Up to 16 MHz of RF BW with 8-bit samples + +\section e1x0_imgs Specify a Non-standard Image + +UHD software will automatically select the USRP-Embedded FPGA image from +the installed images package. The FPGA image selection can be overridden +with the `fpga` device address parameter. + +Example device address string representations to specify non-standard +FPGA image: + + fpga=usrp_e100_custom.bin + +\section e1x0_mcr Changing the Master Clock Rate + +The master clock rate of the USRP-Embedded feeds both the FPGA DSP and +the codec chip. Hundreds of rates between 32 MHz and 64 MHz are +available. A few notable rates are: + +- **64 MHz:** maximum rate of the codec chip +- **61.44 MHz:** good for UMTS/WCDMA applications +- **52 MHz:** good for GSM applications + +\subsection e1x0_mcr_extvcxo Set 61.44MHz - uses external VCXO + +To use the 61.44 MHz clock rate with the USRP-Embedded, two jumpers must +be moved on the device. + +- **J16** is a two pin header; remove the jumper (or leave it on pin1 + only). +- **J15** is a three pin header; move the jumper to (pin1, pin2). + +**Note:** See instructions below to communicate the desired clock rate +to UHD software. + +\subsection e1x0_intvco Set other rates - uses internal VCO + +To use other clock rates, the jumpers will need to be in the default +position. + +- **J16** is a two pin header; move the jumper to (pin1, pin2). +- **J15** is a three pin header; move the jumper to (pin2, pin3). + +To communicate the desired clock rate into UHD software, specify the a +special device address argument, where the key is +`master_clock_rate` and the value is a rate in Hz. Example: + + uhd_usrp_probe --args="master_clock_rate=52e6" + +\section e1x0_clksync Clock Synchronization + +\subsection e1x0_clksync_ref Ref Clock - 10MHz + +The E1xx has a 10MHz TCXO which can be used to discipline the flexible +clocking by selecting `REF_INT` for the uhd::clock_config_t. + +Alternately, an external 10MHz reference clock can be supplied by +soldering a connector. + +- Connector **J10** (REF_IN) needs MCX connector **WM5541-ND** or + similar. +- Square wave will offer the best phase noise performance, but + sinusoid is acceptable. +- **Power level:** 0 to 15dBm +- Select `REF_SMA` in uhd::clock_config_t. + +\subsection e1x0_clksync_pps PPS - Pulse Per Second + +An external PPS signal for timestamp synchronization can be supplied by +soldering a connector. + +- Connector **J13** (PPS) needs MCX connector **WM5541-ND** or + similar. +- Requires a square wave signal. +- **Amplitude:** 3.3 to 5 Vpp + +Test the PPS input with the following app (`<args>` are device +address arguments, optional if only one USRP device is on your machine): + + cd <install-path>/lib/uhd/examples + ./test_pps_input --args=<args> + +\subsection e1x0_clksync_gpsdo Internal GPSDO + +Please see the \ref page_gpsdo for +information on configuring and using the internal GPSDO. + +UHD software will always try to detect an installed GPSDO at runtime. It +is not necessary to burn a special EEPROM value for GPSDO detection. + +\section e1x0_hw Hardware Setup Notes + +\subsection e1x0_hw_leds Front panel LEDs + +The LEDs on the front panel can be useful in debugging hardware and +software issues. The LEDs reveal the following about the state of the +device: + +- **LED A:** transmitting +- **LED B:** PPS signal +- **LED C:** receiving +- **LED D:** FPGA loaded +- **LED E:** reference lock +- **LED F:** board power + +\section e1x0_misc Miscellaneous + +\subsection e1x0_misc_sensors Available Sensors + +The following sensors are available; they can be queried through the +API. + +- **ref_locked:** clock reference locked (internal/external) +- other sensors are added when the GPSDO is enabled + +*/ +// vim:ft=doxygen: diff --git a/host/docs/usrp_e1x0.rst b/host/docs/usrp_e1x0.rst deleted file mode 100644 index ea2d05a3c..000000000 --- a/host/docs/usrp_e1x0.rst +++ /dev/null @@ -1,156 +0,0 @@ -======================================================================== -UHD - USRP-E1x0 Series Device Manual -======================================================================== - -.. contents:: Table of Contents - ------------------------------------------------------------------------- -Comparative features list ------------------------------------------------------------------------- - -**Hardware Capabilities:** - * 1 transceiver card slot - * Internal PPS reference input - * Internal 10 MHz reference input - * Configurable clock rate (defaults to 64 MHz) - * Internal GPSDO option - -**FPGA Capabilities:** - * 2 RX DDC chains in FPGA - * 1 TX DUC chain in FPGA - * Timed commands in FPGA - * Timed sampling in FPGA - * sc8 and sc16 sample modes - - * Up to 8 MHz of RF BW with 16-bit samples - * Up to 16 MHz of RF BW with 8-bit samples - ------------------------------------------------------------------------- -Specify a Non-standard Image ------------------------------------------------------------------------- -UHD software will automatically select the USRP-Embedded FPGA image from the -installed images package. The FPGA image selection can be overridden with the -**fpga** device address parameter. - -Example device address string representations to specify non-standard FPGA -image: - -:: - - fpga=usrp_e100_custom.bin - ------------------------------------------------------------------------- -Changing the Master Clock Rate ------------------------------------------------------------------------- -The master clock rate of the USRP-Embedded feeds both the FPGA DSP and the codec -chip. Hundreds of rates between 32 MHz and 64 MHz are available. A few notable -rates are: - -* **64 MHz:** maximum rate of the codec chip -* **61.44 MHz:** good for UMTS/WCDMA applications -* **52 MHz:** good for GSM applications - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Set 61.44MHz - uses external VCXO -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -To use the 61.44 MHz clock rate with the USRP-Embedded, two jumpers must be moved -on the device. - -* **J16** is a two pin header; remove the jumper (or leave it on pin1 only). -* **J15** is a three pin header; move the jumper to (pin1, pin2). - -**Note:** See instructions below to communicate the desired clock rate to UHD software. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Set other rates - uses internal VCO -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -To use other clock rates, the jumpers will need to be in the default position. - -* **J16** is a two pin header; move the jumper to (pin1, pin2). -* **J15** is a three pin header; move the jumper to (pin2, pin3). - -To communicate the desired clock rate into UHD software, -specify the a special device address argument, -where the key is **master_clock_rate** and the value is a rate in Hz. -Example: -:: - - uhd_usrp_probe --args="master_clock_rate=52e6" - ------------------------------------------------------------------------- -Clock Synchronization ------------------------------------------------------------------------- - - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Ref Clock - 10MHz -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The E1xx has a 10MHz TCXO which can be used to discipline the flexible clocking -by selecting **REF_INT** for the **clock_config_t**. - -Alternately, an external 10MHz reference clock can be supplied by soldering -a connector. - -* Connector **J10** (REF_IN) needs MCX connector **WM5541-ND** or similar. -* Square wave will offer the best phase noise performance, but sinusoid is acceptable. -* **Power level:** 0 to 15dBm -* Select **REF_SMA** in **clock_config_t**. - - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -PPS - Pulse Per Second -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -An external PPS signal for timestamp synchronization can be supplied by soldering -a connector. - -* Connector **J13** (PPS) needs MCX connector **WM5541-ND** or similar. -* Requires a square wave signal. -* **Amplitude:** 3.3 to 5 Vpp - -Test the PPS input with the following app (**<args>** are device address -arguments, optional if only one USRP device is on your machine): - -:: - - cd <install-path>/lib/uhd/examples - ./test_pps_input --args=<args> - - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Internal GPSDO -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Please see the `Internal GPSDO Application Notes <./gpsdo.html>`_ -for information on configuring and using the internal GPSDO. - -UHD software will always try to detect an installed GPSDO at runtime. -It is not necessary to burn a special EEPROM value for GPSDO detection. - ------------------------------------------------------------------------- -Hardware Setup Notes ------------------------------------------------------------------------- - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Front panel LEDs -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The LEDs on the front panel can be useful in debugging hardware and software -issues. The LEDs reveal the following about the state of the device: - -* **LED A:** transmitting -* **LED B:** PPS signal -* **LED C:** receiving -* **LED D:** FPGA loaded -* **LED E:** reference lock -* **LED F:** board power - ------------------------------------------------------------------------- -Miscellaneous ------------------------------------------------------------------------- - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Available Sensors -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The following sensors are available; -they can be queried through the API. - -* **ref_locked:** clock reference locked (internal/external) -* other sensors are added when the GPSDO is enabled diff --git a/host/docs/usrp_n2xx_simple_net_burner.1 b/host/docs/usrp_n2xx_simple_net_burner.1 index ca63e5698..85538ee22 100644 --- a/host/docs/usrp_n2xx_simple_net_burner.1 +++ b/host/docs/usrp_n2xx_simple_net_burner.1 @@ -19,9 +19,9 @@ This program works best when only an IP address is specified. .IP "Custom FPGA Filepath:" --fpga=\fI"filepath"\fR .IP "Don't burn firmware:" ---no_fw +--no-fw .IP "Don't burn FPGA:" ---no_fpga +--no-fpga .IP "Automatically reboot USRP device after burning" --auto_reboot .IP "List all USRP devices without burning" @@ -41,7 +41,7 @@ GR-UHD documentation: .LP Other UHD programs: .sp -uhd_images_downloader(1) usrp2_card_burner(1) usrp_x3xx_fpga_burner(1) +uhd_images_downloader(1) usrp2_card_burner(1) usrp_x3xx_fpga_burner(1) octoclock_firmware_burner(1) .SH AUTHOR This manual page was written by Nicholas Corgan for the Debian project (but may be used by others). diff --git a/host/docs/usrp_x3x0.dox b/host/docs/usrp_x3x0.dox new file mode 100644 index 000000000..0b46f0d16 --- /dev/null +++ b/host/docs/usrp_x3x0.dox @@ -0,0 +1,627 @@ +/*! \page page_usrp_x3x0 X3x0 Series Device Manual + +\tableofcontents + +\section x3x0_feature_list Comparative features list + +- Hardware Capabilities: + - 2 transceiver card slots (can do 2x2 MIMO out of the box) + - Dual SFP+ Transceivers (can be used with 1 GigE, 10 GigE) + - PCI Express over cable (MXI) gen1 x4 + - External PPS input & output + - External 10 MHz input & output + - Expandable via 2nd SFP+ interface + - Supported master clock rates: 200 MHz, 184.32 MHz, 120 MHz + - External GPIO Connector with UHD API control + - External USB Connection for built-in JTAG debugger + - Internal GPSDO option + - Kintex-7 FPGA (X310: XC7K410T, X300: XC7K325T) +- FPGA Capabilities: + - 2 RX DDC chains in FPGA + - 2 TX DUC chain in FPGA + - Timed commands in FPGA + - Timed sampling in FPGA + - 16-bit and 8-bit sample modes (sc8 and sc16) + - Up to 120 MHz of RF bandwidth with 16-bit samples + +\section x3x0_getting_started Getting started + +This will run you through the first steps relevant to get your USRP X300/X310 +up and running. Here, we assume you will connect your USRP using Gigabit Ethernet (1GigE), +as this interface is readily available in most computers. For 10 Gigabit Ethernet (10GigE) or +PCI Express (PCIe), see the corresponding sections in this manual page. + +\subsection x3x0_getting_started_assembling Assembling the X300/X310 kit + +Before you can start using your USRP, you might have to assemble the hardware, +if this has not yet happened. Make sure you are grounded (e.g. by touching a radiator) +in order not to damage sensitive electronics through static discharge! + +1. Unscrew the top of your X300/X310 (there are 2 screws which can be easily loosened + using a small Phillips screwdriver). +2. Insert the daughterboards by inserting them into the slots and optionally screwing + them onto the motherboard. +3. Connect the RF connectors on the daughterboards to the front panel. In order to avoid + confusion, make sure the internal connections match the labels on the front panel (i.e. + TX/RX is connected to TX/RX). +4. If you have purchased an internal GPSDO, follow the instructions on + \ref page_gpsdo_x3x0 to insert the GPSDO. Note that you + will need an external GPS antenna connected to the rear GPS ANT connector in order to + make use of GPS, although your USRP will still be usable without. +5. Connect the 1 GigE SFP+ transceiver into the Ethernet port 0 and connect the X300/X310 with + your computer. +6. Connect the power supply and switch on the USRP. + +\subsection x3x0_getting_started_connectivity Network Connectivity + +The next step is to make sure your computer can talk to the USRP. An otherwise unconfigured +USRP device will have the IP address 192.168.10.2 when using 1GigE. +It is recommended to directly connect your USRP to the computer at first, +and to set the IP address on your machine to 192.168.10.1. +See \ref x3x0_setup_network_host_interface on details how to change your machine's IP address. + +<b>Note</b>: If you are running an automatic IP configuration service such as Network Manager, make +sure it is either deactivated or configured to not change the network device! This can, in extreme cases, +lead to you bricking the USRP! + +If your network configuration is correct, running `uhd_find_devices` will find your USRP +and print some information about it. You will also be able to ping the USRP by running: + + ping 192.168.10.2 + +on the command line. At this point, you should also run: + + uhd_usrp_probe --args addr=192.168.10.2 + +to make sure all of your components (daughterboards, GPSDO) are correctly detected and usable. + +\subsection x3x0_getting_started_fpga_update Updating the FPGA + +If the output from `uhd_find_devices` and `uhd_usrp_probe` didn't show any warnings, you +can skip this step. However, if there were errors regarding the FPGA version compatibility +number, you will have to update the FPGA image before you can start using your USRP. + +1. Download the current UHD images. You can use the `uhd_images_downloader` script provided + with UHD (see also \ref page_images). +2. Use the `usrp_x3xx_fpga_burner` utility to update the FPGA image. On the command line, run: + + usrp_x3xx_fpga_burner --addr=192.168.10.2 --type=HGS + + If you have installed the images to a non-standard location, you might need to run (change the filename according to your device): + + usrp_x3xx_fpga_burner --addr=192.168.10.2 --fpga-path <path_to_images>/usrp_x310_fpga_HGS.bit + + The process of updating the FPGA image will take several minutes. Make sure the process of flashing the image does not get interrupted. + +See \ref x3x0_flash for more details. + +When your FPGA is up to date, power-cycle the device and re-run `uhd_usrp_probe`. There should +be no more warnings at this point, and all components should be correctly detected. Your USRP is now +ready for development! + +\section x3x0_hw Hardware Setup + +\subsection x3x0_hw_1gige Gigabit Ethernet (1 GigE) + +- Prior to installing the module, the host PC can remain powered on. +- Plug a 1 Gigabit SFP Transceiver into Ethernet Port 0 on the USRP X300/X310 device. +- Use the Ethernet cable to connect the SFP+ transciever on the device to the host computer. For maximum throughput, Ettus Research recommends that you connect each device to its own dedicated Gigabit Ethernet interface on the host computer. +- Connect the AC/DC power supply to the device and plug the supply into a wall outlet. +- The OS will automatically recognize the device (e.g. when running `uhd_find_devices`). + +\subsection x3x0_hw_10gige Ten Gigabit Ethernet (10 GigE) + +### Installing the Host Ethernet Interface + +Ettus Research recommends the Intel Ethernet Converged Network Adapter X520-DA2 interface for communication with the USRP X300/X310 device. +Installation instructions for this interface are available on the official Intel website. + +### Installing the USRP X300/X310 + +- Prior to installing the module, the host PC can remain powered on. +- Use a 10 Gigabit SFP+ cable to connect Ethernet Port 1 on the USRP X300/X310 device to the host computer. For maximum throughput, Ettus Research recommends that you connect the device to its own dedicated Ten Gigabit, Ettus Research recommended Ethernet interface on the host computer. +- Connect the AC/DC power supply to the device and plug the supply into a wall outlet. +- The OS will automatically recognize the device (e.g. when running `uhd_find_devices`). + +The LEDs on the front panel can be useful in debugging hardware and software issues (see \ref x3x0_hw_fpanel) + +\subsection x3x0_hw_pcie PCI Express (Desktop) + +<b>Important Note: The USRP X-Series provides PCIe connectivity over MXI cable. +We will use the 'MXI' nomenclature for the rest of this manual.</b> + +### Installing the PCIe Kernel Drivers + +In order to use the USRP X-Series on a PCIe-over-MXI connection, you need to +install the NI RIO drivers on your system. Please follow the insructions here: +\ref page_ni_rio_kernel + +### Installing the PCI Express Interface Kit + +Follow the instructions listed in the <a href="http://www.ni.com/pdf/manuals/371976c.pdf">Set Up Your MXI-Express x4 System</a> +document to setup the NI PCIe-8371 module. + +### Installing the USRP X300/X310 + +- Prior to installing the module, make sure that the PC is powered off. +- Using a MXI-Express Cable connect the USRP X300/X310 to the NI PCIe-8371. +- Connect the AC/DC power supply to the device and plug the supply into a wall outlet. +- Power on the USRP X300/X310 device using the power switch located in the bottom-right corner of the front panel. +- Power on the PC (The OS automatically recognizes the new device) + +<b>Note:</b> The USRP device is not hot-pluggable over PCI Express. Any connection changes with only be detected by your +computer after a successful reboot. + +### Troubleshooting + +Two possible failure modes are your computer not booting when connected to your +USRP device through MXI-Express, and Windows not properly discovering your +devices (for example, there is a yellow exclamation point on a PCI to PCI +bridge in Windows Device Manager, despite drivers for all devices being +installed). These situations often are due to programming errors in PCI Express +device configuration of the BIOS. To use this software, you need a MXI-Express +device that supports Mode 1 operation. +Refer to <a href="http://download.ni.com/support/softlib//PXI/MXIe%20Compatibility%20Software/1.5.0/readme.html#SupportedHardware">NI MXI-Express BIOS Compatibility Software Readme</a> +for more information. + +The BIOS Compatibility Software can be downloaded for Windows from the <a href="http://www.ni.com/download/mxi-express-bios-compatibility-software-1.5/3764/en/"> MXI-Express BIOS Compatibility Software page</a>. + +\subsection x3x0_hw_pcie_laptop PCI Express (Laptop) + +<b>Important Note: The USRP X-Series provides PCIe connectivity over MXI cable +We will use the 'MXI' nomenclature for the rest of this manual.</b> + +### Installing the PCIe Kernel Drivers + +In order to use the USRP X-Series on a PCIe-over-MXI connection, you need to +install the NI RIO drivers on your system. Please follow the insructions here: +\ref page_ni_rio_kernel + +### Installing the PCI Express Card + +Follow the instructions listed in the “Installing an NI ExpressCard-8360 Host Card†section of the +<a href="http://www.ni.com/pdf/manuals/373259d.pdf#page=10">Set Up Your MXI-Express x1 System</a> +document to setup the NI ExpressCard-8360B module. + +### Installing the USRP X300/X310 + +Because a laptop computer is not grounded, follow this procedure to safely connect a laptop +computer to your USRP device. + +- Connect the AC/DC power supply to the device and plug the supply into a wall outlet. Ensure that the USRP device is powered off. +- Touch the NI ExpressCard-8360B and a metal part of the USRP device simultaneously. Do not install the NI ExpressCard-8360B into the laptop computer yet. +- Connect the cable to the NI ExpressCard-8360B and USRP. +- Plug the NI ExpressCard-8360B into an available ExpressCard slot. If your laptop computer is already running (or hibernating, suspended, etc.) when you install an NI ExpressCard-8360B, you must reboot to detect the USRP. Otherwise, the USRP is detected when you start your computer. + +\b Note: The USRP device is not hot-pluggable over PCI Express. Any connection changes will only be detected by your computer after a successful reboot. + +\section x3x0_jtag On-Board JTAG Programmer + +The USRP X3x0 includes an on-board JTAG programmer, built into the motherboard. +To connect to this JTAG device, simply connect your computer to the USB JTAG +port on the front of the X3x0 device. You may now use the JTAG programmer in +the same way you would use any other, including: + +- <a href="http://www.xilinx.com/support/download/index.htm">Xilinx Programming Tools (ISE, iMPACT)</a> +- <a href="http://www.xilinx.com/tools/cspro.htm">Xilinx Chipscope</a> +- <a href="https://www.digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2">Digilent ADEPT</a> + +In order to use the JTAG programmer with the Xilinx tools, the Digilent drivers and plugin have to be installed first. +Although recent versions of ISE ship with the driver, it has to still be manually installed. + +\b Note: Sometimes the ISE shipped versions are newer than the ones available via Digilent's website. It is therefore advisable to +use the ISE provided plugin and drivers. + +To install first locate your ISE installation path on a Linux system (default is `/opt/Xilinx/<Version>`): + + sudo <ise install path>/ISE_DS/common/bin/lin64/digilent/install_digilent.sh + +Afterwards either reboot or force udev to reload its rules by: + + sudo udevadm control --reload + +The USRP-X series device should now be usable with all the tools mentioned above. + +\section x3x0_load_fpga_imgs Load FPGA Images onto the Device + +The USRP-X Series device ships with a bitstream pre-programmed in the flash, +which is automatically loaded onto the FPGA during device power-up. However, +a new FPGA image can be configured over the PCI Express interface or the +on-board USB-JTAG programmer. This process can be seen as a "one-time load", in +that if you power-cycle the device, it will not retain the FPGA image. + +Please note that this process is *different* than replacing the FPGA image +stored in the flash, which will then be automatically loaded the next time the +device is reset. + +\subsection x3x0_load_fpga_imgs_fpga_flavours FPGA Image Flavors + +The USRP-X Series devices contains two SFP+ ports for the two Ethernet channels. +Because the SFP+ ports support both 1 Gigabit (SFP) and 10 Gigabit (SFP+) +transceivers, several FPGA images are shipped with UHD to determine the +behavior of the above interfaces. + +|  FPGA Image Flavor |  SFP+ Port 0 Interface |  SFP+ Port 1 Interface | +|---------------------|------------------------|------------------------| +|  HGS (Default) |  1 Gigabit Ethernet |  10 Gigabit Ethernet  | +|  XGS  |  10 Gigabit Ethernet |  10 Gigabit Ethernet  | + +FPGA images are shipped in 2 formats: + +- **LVBITX**: LabVIEW FPGA configuration bitstream format (for use over PCI Express and Ethernet) +- **BIT**: Xilinx configuration bitstream format (for use over Ethernet and JTAG) + +To get the latest images, simply use the uhd_images_downloader script. On Unix systems, use this command: + + sudo uhd_images_downloader + +On Windows, use: + + <path_to_python.exe> <install-path>/bin/uhd_images_downloader.py + + +\subsection x3x0_load_fpga_imgs_pcie Use PCI Express to load FPGA images + +UHD requires a valid LabVIEW FPGA configuration bitstream file (LVBITX) to use the USRP-X Series +device over the PCI Express bus. LabVIEW FPGA is \b not required to use UHD with a USRP-X Series device. +Because FPGA configuration is a part of normal operation over PCI Express, there is no setup required +before running UHD. + +The \e fpga tag can be set in the optional device args passed to indicate the FPGA image flavor to UHD. +If the above tag is specified, UHD will attempt to load the FPGA image with the requested flavor from the +UHD images directory. If the tag is not specified, UHD will automatically detect the flavor of the image +and attempt to load the corresponding configuration bitstream onto the device. Note that if UHD detects +that the requested image is already loaded onto the FPGA then it will not reload it. + +\subsection x3x0_load_fpga_imgs_jtag Use JTAG to load FPGA images + +The USRP-X Series device features an on-board USB-JTAG programmer that can be accessed on the front-panel +of the device. The iMPACT tool in the <a href="http://www.xilinx.com/support/download/index.htm">Xilinx Programming Tools (ISE, iMPACT)</a> package can be used to load an image over the JTAG interface. This can be useful for unbricking devices. + +If you have iMPACT installed, you can use the `impact_jtag_programmer.sh` tool to install images. Make sure your X3x0 is powered on and connected to your computer using the front panel USB JTAG connector (USB 2.0 is fine for this). Then run the tool: + + <path_to_uhd_tools>/impact_jtag_programmer.sh --fpga-path=<fpga_image_path> + +\section x3x0_flash Load the Images onto the On-board Flash + +To change the FPGA image stored in the on-board flash, the USRP-X Series device +can be reprogrammed over the network or PCI Express. Once you have programmed an +image into the flash, that image will be automatically loaded on the FPGA +during the device boot-up sequence. + +\b Note: +Different hardware revisions require different FPGA images. +Determine the revision number from the sticker on the rear of the device. +If you are manually specifying an FPGA path, the utility will not try to +detect your device information, and you will need to use this number to +select which image to burn. + +\b Note: +The burner utility will default to using the appropriate BIT file if no custom +FPGA image path is specified, but it is compatible with BIN, BIT, and LVBITX +images. + +\subsection x3x0_flash_burner_tool Use the burner tool over Ethernet + + Automatic FPGA path, detect image type: + usrp_x3xx_fpga_burner --addr=<IP address> + + Automatic FPGA path, select image type: + usrp_x3xx_fpga_burner --addr=<IP address> --type=<HGS or XGS> + + Manual FPGA path: + usrp_x3xx_fpga_burner --addr=<IP address> --fpga-path=<path to FPGA image> + +\subsection x3x0_flash_burner_tool_pcie Use the burner tool over PCI Express + + Automatic FPGA path, detect image type: + usrp_x3xx_fpga_burner --resource=<NI-RIO resource> + + Automatic FPGA path, select image type: + usrp_x3xx_fpga_burner --resource=<NI-RIO resource> --type=<HGS or XGS> + + Manual FPGA path: + usrp_x3xx_fpga_burner --resource=<NI-RIO resource> --fpga-path=<path to FPGA image> + +\subsection x3x0_flash_bricking Device recovery and bricking +It is possible to put the device into an unusable state by loading bad images ("bricking"). +Fortunately, the USRP-X Series device can be loaded with a good image temporarily using the USB-JTAG interface. +Once booted into the safe image, the user can once again load images onto the device over Ethernet or PCI Express. + +\section x3x0_setup_network Setup Networking +The USRP-X Series only supports Gigabit and Ten Gigabit Ethernet and will not work with a 10/100 Mbps interface. + +<b>Please note that 10 Gigabit Ethernet defines the protocol, not necessary the +medium. For example, you may use 10GigE over optical with optical SFP+ +transceiver modules.</b> + +\subsection x3x0_setup_network_host_interface Setup the host interface + +The USRP-X Series communicates at the IP/UDP layer over the Gigabit and Ten Gigabit Ethernet. +The default IP address for the USRP X300/X310 device depends on the Ethernet Port and interface used. +You must configure the host Ethernet interface with a static IP address on the same subnet as the connected +device to enable communication, as shown in the following table: + +  Ethernet Interface | USRP Ethernet Port |  Default USRP IP Address |  Host Static IP Address | Host Static Subnet Mask | Address EEPROM key +---------------------|-------------------------|--------------------------|-------------------------|-------------------------|------------------- +  Gigabit |  Port 0 (HGS Image) |  192.168.10.2 | 192.168.10.1 | 255.255.255.0 | `ip-addr0` +  Ten Gigabit |  Port 0 (XGS Image) |  192.168.30.2 | 192.168.30.1 | 255.255.255.0 | `ip-addr2` +  Ten Gigabit |  Port 1 (HGS/XGS Image) |  192.168.40.2 | 192.168.40.1 | 255.255.255.0 | `ip-addr3` + +As you can see, the X300/X310 actually stores different IP addresses, which all address the device differently: Each combination of Ethernet port and interface type (i.e., Gigabit or Ten Gigabit) has its own IP address. As an example, when addressing the device through 1 Gigabit Ethernet on its first port (Port 0), the relevant IP address is the one stored in the EEPROM with key `ip-addr0`, or 192.168.10.2 by default. + +See \ref x3x0cfg_hostpc_netcfg_ip on details how to change your machine's IP address and MTU size to work well with the X300. + +\subsection x3x0_setup_network_multidevs Multiple devices per host + +For maximum throughput, one Ethernet interface per USRP is recommended, +although multiple devices may be connected via an Ethernet switch. +In any case, each Ethernet interface should have its own subnet, +and the corresponding USRP device should be assigned an address in that subnet. +Example: + +### Configuration for USRP-X Series device 0: + +- Ethernet interface IPv4 address: `192.168.10.1` +- Ethernet interface subnet mask: `255.255.255.0` +- USRP-X Series device IPv4 address: `192.168.10.2` + +### Configuration for USRP-X Series device 1: + +- Ethernet interface IPv4 address: `192.168.110.1` +- Ethernet interface subnet mask: `255.255.255.0` +- USRP-X Series device IPv4 address: `192.168.110.2` + +\subsection x3x0_setup_change_ip Change the USRP's IP address + +You may need to change the USRP's IP address for several reasons: +- to satisfy your particular network configuration +- to use multiple USRP-X Series devices on the same host computer +- to set a known IP address into USRP (in case you forgot) + +To change the USRP's IP address, +you must know the current address of the USRP, +and the network must be setup properly as described above. +You must also know which IP address of the X300 you want to change, as identified by their address EEPROM key (e.g. `ip-addr0`, see the table above). +Run the following commands: + +\b UNIX: + + cd <install-path>/lib/uhd/utils + ./usrp_burn_mb_eeprom --args=<optional device args> --values="ip-addr0=192.168.10.3" + +\b Windows: + + cd <install-path>\lib\uhd\utils + usrp_burn_mb_eeprom.exe --args=<optional device args> --values="ip-addr0=192.168.10.3" + +You must power-cycle the device before you can use this new address. + +\section x3x0_addressing Addressing the Device + +\subsection x3x0_addressing_singledev Single device configuration + +In a single-device configuration, +the USRP device must have a unique IPv4 address on the host computer. +The USRP can be identified through its IPv4 address, resolvable hostname, NI-RIO resource name or by other means. +See the application notes on \ref page_identification. +Use this addressing scheme with the uhd::usrp::multi_usrp interface (not a typo!). + +Example device address string representation for a USRP-X Series device with IPv4 address 192.168.10.2: + + addr=192.168.10.2 + +Example device address string representation for a USRP-X Series device with RIO resource name `RIO0` over PCI Express: + + resource=RIO0 + +\subsection x3x0_addressing_multidevcfg Multiple device configuration + +In a multi-device configuration, +each USRP device must have a unique IPv4 address on the host computer. +The device address parameter keys must be suffixed with the device index. +Each parameter key should be of the format \<key\>\<index\>. +Use this addressing scheme with the uhd::usrp::multi_usrp interface. + +- The order in which devices are indexed corresponds to the indexing of the transmit and receive channels. +- The key indexing provides the same granularity of device identification as in the single device case. + +Example device address string representation for 2 USRPs with IPv4 addresses **192.168.10.2** and **192.168.20.2**: + + addr0=192.168.10.2, addr1=192.168.20.2 + + +\section x3x0_comm_problems Communication Problems + +When setting up a development machine for the first time, +you may have various difficulties communicating with the USRP device. +The following tips are designed to help narrow down and diagnose the problem. + +\subsection x3x0_comm_problems_runtimeerr RuntimeError: no control response + +This is a common error that occurs when you have set the subnet of your network +interface to a different subnet than the network interface of the USRP device. For +example, if your network interface is set to **192.168.20.1**, and the USRP device is **192.168.10.2** +(note the difference in the third numbers of the IP addresses), you +will likely see a 'no control response' error message. + +Fixing this is simple - just set the your host PC's IP address to the same +subnet as that of your USRP device. Instructions for setting your IP address are in the +previous section of this documentation. + +\subsection x3x0_comm_problems_firewall Firewall issues + +When the IP address is not specified, +the device discovery broadcasts UDP packets from each Ethernet interface. +Many firewalls will block the replies to these broadcast packets. +If disabling your system's firewall +or specifying the IP address yields a discovered device, +then your firewall may be blocking replies to UDP broadcast packets. +If this is the case, we recommend that you disable the firewall +or create a rule to allow all incoming packets with UDP source port **49152**. + +\subsection x3x0_comm_problems_ping Ping the device +The USRP device will reply to ICMP echo requests ("ping"). +A successful ping response means that the device has booted properly +and that it is using the expected IP address. + + ping 192.168.10.2 + +\subsection x3x0_comm_problems_not_enumerated USRP device not enumerated (Linux) + +UHD requires the RIO device manager service to be running in order to +communicate with an X-Series USRP over PCIe. This service is installed as +a part of the USRP RIO (or NI-USRP) installer. On Linux, the service is not +started at system boot time, and is left to the user to control. To start it, +run the following command: + + sudo niusrprio_pcie start + +If the device still does not enumerate after starting the device manager, make sure that the host computer +has successfully detected it. You can do so by running the following command: + + lspci -k -d 1093:c4c4 + +A device similar to the following should be detected: + + $ lspci -k -d 1093:c4c4 + 04:00.0 Signal processing controller: National Instruments ... + Subsystem: National Instruments Device 76ca + Kernel driver in use: niusrpriok_shipped + +- A USRP X300 should appear with 'Subsystem: National Instruments Device 7736' +- A USRP X310 should appear with 'Subsystem: National Instruments Device 76ca' + +\subsection x3x0_comm_problems_not_enumerated_win USRP device not enumerated (Windows) + +UHD requires the RIO device manager service to be running in order to +communicate with an X-Series USRP over PCIe. +This service is installed as a part of the USRP RIO (or NI-USRP) installer. On Windows, it can be found in +the **Services** section in the Control Panel and it is started at system boot time. To ensure that the +service is indeed started, navigate to the Services tag in the Windows Task Manager and ensure that the +status of **niusrpriorpc** is "Running". + +If the device still does not enumerate after starting the device manager, make sure that the host computer +has successfully detected it. You can do so by checking if your device shows up in the Windows Device Manager. + +\subsection x3x0_comm_problems_monitor Monitor the host network traffic +Use Wireshark to monitor packets sent to and received from the device. + +\subsection x3x0_comm_problems_leds Observe Ethernet port LEDs +When there is network traffic arriving at the Ethernet port, LEDs will light up. +You can use this to make sure the network connection is correctly set up, e.g. +by pinging the USRP and making sure the LEDs start to blink. + +\section x3x0_hw Hardware Notes + +\subsection x3x0_hw_fpanel Front Panel + +\image html x3x0_fp_overlay.png "X3x0" + +- **JTAG**: USB connector for the on-board USB-JTAG programmer +- **RF A Group** + + **TX/RX LED**: Indicates that data is streaming on the TX/RX channel on daughterboard A + + **RX2 LED**: Indicates that data is streaming on the RX2 channel on daughterboard A +- **REF**: Indicates that the external Reference Clock is locked +- **PPS**: Indicates a valid PPS signal by pulsing once per second +- **AUX I/O**: Front panel GPIO connector. +- **GPS**: Indicates that GPS reference is locked +- **LINK**: Indicates that the host computer is communicating with the device (Activity) + +- **RF B Group** + + **TX/RX LED**: Indicates that data is streaming on the TX/RX channel on daughterboard B + + **RX2 LED**: Indicates that data is streaming on the RX2 channel on daughterboard B +- **PWR**: Power switch + +\subsection x3x0_hw_rear_panel Rear Panel + +\image html x3x0_rp_overlay.png "X3x0 Rear Panel" + +- **PWR**: Connector for the USRP-X Series power supply +- **1G/10G ETH**: SFP+ ports for Ethernet interfaces +- **REF OUT**: Output port for the exported reference clock +- **REF IN**: Reference clock input +- **PCIe x4**: Connector for Cabled PCI Express link +- **PPS/TRIG OUT**: Output port for the PPS signal +- **PPS/TRIG IN**: Input port for the PPS signal +- **GPS**: Connection for the GPS antenna + +\subsection x3x0_hw_x3x0_hw_ref10M Ref Clock - 10 MHz + +Using an external 10 MHz reference clock, a square wave will offer the best phase +noise performance, but a sinusoid is acceptable. The power level of the reference clock cannot exceed +15 dBm. + +\subsection x3x0_hw_pps PPS - Pulse Per Second +Using a PPS signal for timestamp synchronization requires a square wave signal with the following a 5Vpp amplitude. + +To test the PPS input, you can use the following tool from the UHD examples: + +- `<args>` are device address arguments (optional if only one USRP device is on your machine) + + cd <install-path>/lib/uhd/examples + ./test_pps_input --args=\<args\> + +\subsection x3x0_hw_gpsdo Internal GPSDO + +Please see \ref page_gpsdo_x3x0 for information on configuring and using the internal GPSDO. + +\subsection x3x0_hw_gpio Front Panel GPIO + +### Connector + +\image html x3x0_gpio_conn.png "X3x0 GPIO Connector" + +### Pin Mapping + +- Pin 1: +3.3V +- Pin 2: Data[0] +- Pin 3: Data[1] +- Pin 4: Data[2] +- Pin 5: Data[3] +- Pin 6: Data[4] +- Pin 7: Data[5] +- Pin 8: Data[6] +- Pin 9: Data[7] +- Pin 10: Data[8] +- Pin 11: Data[9] +- Pin 12: Data[10] +- Pin 13: Data[11] +- Pin 14: 0V +- Pin 15: 0V + + +Please see the \ref page_gpio_api for information on configuring and using the GPIO bus. + +\subsection x3x0_hw_chipscope Debugging custom FPGA designs with Xilinx Chipscope + +Xilinx chipscope allows for debugging custom FPGA designs similar to a logic analyzer. +USRP-X series devices can be used with Xilinx chipscope using the onboard USB JTAG connector. + +Further information on how to use Chipscope can be found in the Xilinx Chipscope Pro Software and Cores User Guide (UG029). + +\section x3x0_misc Miscellaneous + +\subsection x3x0_misc_multirx Multiple RX channels + +There are two complete DDC and DUC DSP chains in the FPGA. In the single channel case, +only one chain is ever used. To receive from both channels, the user must set the **RX** or **TX** +subdevice specification. + +In the following example, a TVRX2 is installed. +Channel 0 is sourced from subdevice **RX1**, +and channel 1 is sourced from subdevice **RX2** (**RX1** and **RX2** are antenna connectors on the TVRX2 daughterboard). + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} +usrp->set_rx_subdev_spec("A:RX1 A:RX2"); +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +\subsection x3x0_misc_sensors Available Sensors + +The following sensors are available for the USRP-X Series motherboards; +they can be queried through the API. + +- **ref_locked** - clock reference locked (internal/external) +- Other sensors are added when the GPSDO is enabled + +*/ +// vim:ft=doxygen: diff --git a/host/docs/usrp_x3x0.rst b/host/docs/usrp_x3x0.rst deleted file mode 100644 index 7dd322dbf..000000000 --- a/host/docs/usrp_x3x0.rst +++ /dev/null @@ -1,747 +0,0 @@ -=============================== -UHD - X3x0 Series Device Manual -=============================== - -.. contents:: Table of Contents - -------------------------- -Comparative features list -------------------------- - -**Hardware Capabilities:** - * 2 transceiver card slots (can do 2x2 MIMO out of the box) - * Dual SFP+ Transceivers (can be used with 1 GigE, 10 GigE) - * PCI Express over cable (MXI) gen1 x4 - * External PPS input & output - * External 10 MHz input & output - * Expandable via 2nd SFP+ interface - * Supported master clock rates: 200 MHz, 184.32 MHz - * External GPIO Connector with UHD API control - * External USB Connection for built-in JTAG debugger - * Internal GPSDO option - * Kintex-7 FPGA (X310: XC7K410T, X300: XC7K325T) - -**FPGA Capabilities:** - * 2 RX DDC chains in FPGA - * 2 TX DUC chain in FPGA - * Timed commands in FPGA - * Timed sampling in FPGA - * 16-bit and 8-bit sample modes (sc8 and sc16) - * Up to 120 MHz of RF bandwidth with 16-bit samples - ---------------- -Getting started ---------------- - -This will run you through the first steps relevant to get your USRP X300/X310 -up and running. Here, we assume you will connect your USRP using Gigabit Ethernet (1GigE), -as this interface is readily available in most computers. For 10 Gigabit Ethernet (10GigE) or -PCI Express (PCIe), see the corresponding sections in this manual page. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Assembling the X300/X310 kit -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Before you can start using your USRP, you might have to assemble the hardware, -if this has not yet happened. Make sure you are grounded (e.g. by touching a radiator) -in order not to damage sensitive electronics through static discharge! - -1. Unscrew the top of your X300/X310 (there are 2 screws which can be easily loosened - using a small Phillips screwdriver). -2. Insert the daughterboards by inserting them into the slots and optionally screwing - them onto the motherboard. -3. Connect the RF connectors on the daughterboards to the front panel. In order to avoid - confusion, make sure the internal connections match the labels on the front panel (i.e. - TX/RX is connected to TX/RX). -4. If you have purchased an internal GPSDO, follow the instructions on - `the internal GPSDO manual page <./gpsdo_x3x0.html>`_ to insert the GPSDO. Note that you - will need an external GPS antenna connected to the rear GPS ANT connector in order to - make use of GPS, although your USRP will still be usable without. -5. Connect the 1 GigE SFP+ transceiver into the Ethernet port 0 and connect the X300/X310 with - your computer. -6. Connect the power supply and switch on the USRP. - -^^^^^^^^^^^^^^^^^^^^ -Network Connectivity -^^^^^^^^^^^^^^^^^^^^ - -The next step is to make sure your computer can talk to the USRP. An otherwise -unconfigured USRP device will have the IP address 192.168.10.2 when using -1GigE. It is recommended to directly connect your USRP to the computer at -first, and to set the IP address on your machine to 192.168.10.1. - -See the `system configuration manual <./usrp_x3x0_config.html>`_ on details how -to change your machine's IP address. - -**Note**: If you are running an automatic IP configuration service such as -Network Manager, make sure it is either deactivated or configured to not manage -the network interface! This can, in extreme cases, lead to you bricking the -USRP! - -If your network configuration is correct, running ``uhd_find_devices`` will find your USRP -and print some information about it. You will also be able to ping the USRP by running:: - - ping 192.168.10.2 - -on the command line. At this point, you should also run:: - - uhd_usrp_probe --args addr=192.168.10.2 - -to make sure all of your components (daughterboards, GPSDO) are correctly detected and usable. - -^^^^^^^^^^^^^^^^^^^^^^^^^ -Updating the FPGA Image -^^^^^^^^^^^^^^^^^^^^^^^^^ - -If the output from ``uhd_find_devices`` and ``uhd_usrp_probe`` didn't show any -warnings, you can skip this step. However, if there were errors regarding the -FPGA version compatibility number (compat number), you will have to upate the -FPGA image before you can start using your USRP. - -1. Download the current UHD images. You can use the ``uhd_images_downloader`` script provided - with UHD (see also `FPGA Image Flavors`_). -2. Use the ``usrp_x3xx_fpga_burner`` utility to update the FPGA image. On the command line, run:: - - usrp_x3xx_fpga_burner --addr=192.168.10.2 --type=HGS - - If you have installed the images to a non-standard location, you might need to run (change the filename according to your device):: - - usrp_x3xx_fpga_burner --addr=192.168.10.2 --fpga-path <path_to_images>/usrp_x310_fpga_HGS.bit - - The process of updating the FPGA image will take several minutes. Make sure the process of flashing the image does not get interrupted. - -See `Load the Images onto the On-board Flash`_ for more details. - -When your FPGA image is up to date, power-cycle the device and re-run -``uhd_usrp_probe``. There should be no errors at this point, and all components -should be correctly detected. Your USRP is now ready for development! - --------------- -Hardware Setup --------------- - -^^^^^^^^^^^^^^^^^^^^^^^^^ -Gigabit Ethernet (1 GigE) -^^^^^^^^^^^^^^^^^^^^^^^^^ - -Installing the USRP X300/X310 -::::::::::::::::::::::::::::: -* Prior to installing the module, the host PC can remain powered on. -* Plug a 1 Gigabit SFP Transceiver into Ethernet Port 0 on the USRP X300/X310 device. -* Use the Ethernet cable to connect the SFP+ transciever on the device to the host computer. For maximum throughput, Ettus Research recommends that you connect each device to its own dedicated Gigabit Ethernet interface on the host computer. -* Connect the AC/DC power supply to the device and plug the supply into a wall outlet. -* The OS will automatically recognize the device (e.g. when running uhd_find_devices). - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Ten Gigabit Ethernet (10 GigE) -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Installing the Host Ethernet Interface -:::::::::::::::::::::::::::::::::::::: -Ettus Research recommends the Intel Ethernet Converged Network Adapter X520-DA2 interface for communication with the USRP X300/X310 device. -Installation instructions for this interface are available on the official Intel website. - -Installing the USRP X300/X310 -::::::::::::::::::::::::::::: -* Prior to installing the module, the host PC can remain powered on. -* Use a 10 Gigabit SFP+ cable to connect Ethernet Port 1 on the USRP X300/X310 device to the host computer. For maximum throughput, Ettus Research recommends that you connect the device to its own dedicated Ten Gigabit, Ettus Research recommended Ethernet interface on the host computer. -* Connect the AC/DC power supply to the device and plug the supply into a wall outlet. -* The OS will automatically recognize the device (e.g. when running uhd_find_devices). - -The LEDs on the front panel can be useful in debugging hardware and software issues (see Section "Front Panel") - -^^^^^^^^^^^^^^^^^^^^^ -PCI Express (Desktop) -^^^^^^^^^^^^^^^^^^^^^ -*Important Note: The USRP X-Series provides PCIe connectivity over MXI cable. -We will use the 'MXI' nomenclature for the rest of this manual.* - -Installing the PCI Express Interface Kit -:::::::::::::::::::::::::::::::::::::::: -Follow the instructions listed in the `Set Up Your MXI-Express x4 System <http://www.ni.com/pdf/manuals/371976c.pdf>`_ -document to setup the NI PCIe-8371 module. - -Installing the USRP X300/X310 -::::::::::::::::::::::::::::: -* Prior to installing the module, make sure that the PC is powered off. -* Using a MXI-Express Cable connect the USRP X300/X310 to the NI PCIe-8371. -* Connect the AC/DC power supply to the device and plug the supply into a wall outlet. -* Power on the USRP X300/X310 device using the power switch located in the bottom-right corner of the front panel. -* Power on the PC (The OS automatically recognizes the new device) - -NOTE: The USRP device is not hot-pluggable over PCI Express. Any connection changes with only be detected by your -computer after a successful reboot. - -Troubleshooting -::::::::::::::: -Two possible failure modes are your computer not booting when connected to your -USRP device through MXI-Express, and Windows not properly discovering your -devices (for example, there is a yellow exclamation point on a PCI to PCI -bridge in Windows Device Manager, despite drivers for all devices being -installed). These situations often are due to programming errors in PCI Express -device configuration of the BIOS. To use this software, you need a MXI-Express -device that supports Mode 1 operation. -Refer to `NI MXI-Express BIOS Compatibility Software Readme <http://download.ni.com/support/softlib//PXI/MXIe%20Compatibility%20Software/1.5.0/readme.html#SupportedHardware>`_ -for more information. - -The BIOS Compatibility Software can be downloaded for Windows from the `MXI-Express BIOS Compatibility Software <http://www.ni.com/download/mxi-express-bios-compatibility-software-1.5/3764/en/>`_ page - -^^^^^^^^^^^^^^^^^^^^ -PCI Express (Laptop) -^^^^^^^^^^^^^^^^^^^^ -*Important Note: The USRP X-Series provides PCIe connectivity over MXI cable. -We will use the 'MXI' nomenclature for the rest of this manual.* - -Installing the PCI Express Card -::::::::::::::::::::::::::::::: -Follow the instructions listed in the “Installing an NI ExpressCard-8360 Host Card†section of the -`Set Up Your MXI-Express x1 System <http://www.ni.com/pdf/manuals/373259d.pdf#page=10>`_ -document to setup the NI ExpressCard-8360B module. - -Installing the USRP X300/X310 -::::::::::::::::::::::::::::: -Because a laptop computer is not grounded, follow this procedure to safely connect a laptop -computer to your USRP device. - -* Connect the AC/DC power supply to the device and plug the supply into a wall outlet. Ensure that the USRP device is powered off. -* Touch the NI ExpressCard-8360B and a metal part of the USRP device simultaneously. Do not install the NI ExpressCard-8360B into the laptop computer yet. -* Connect the cable to the NI ExpressCard-8360B and USRP. -* Plug the NI ExpressCard-8360B into an available ExpressCard slot. If your laptop computer is already running (or hibernating, suspended, etc) when you install an NI ExpressCard-8360B, you must reboot to detect the USRP. Otherwise, the USRP is detected when you start your computer. - -NOTE: The USRP device is not hot-pluggable over PCI Express. Any connection changes will only be detected by your computer after a successful reboot. - --------------------------------- -On-Board JTAG Programmer --------------------------------- -The USRP X3x0 includes an on-board JTAG programmer, built into the motherboard. -To connect to this JTAG device, simply connect your computer to the USB JTAG -port on the front of the X3x0 device. You may now use the JTAG programmer in -the same way you would use any other, including: - -* `Xilinx Programming Tools (ISE, iMPACT) <http://www.xilinx.com/support/download/index.htm>`_ -* `Xilinx Chipscope <http://www.xilinx.com/tools/cspro.htm>`_ -* `Digilent ADEPT <https://www.digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2>`_ - -In order to use the JTAG programmer with the Xilinx tools, the Digilent drivers and plugin have to be installed first. -Although recent versions of ISE ship with the driver, it has to still be manually installed. - -Note: Sometimes the ISE shipped versions are newer than the ones available via Digilent's website. It is therefore advisable to -use the ISE provided plugin and drivers. - -To install first locate your ISE installation path (default is /opt/Xilinx/<Version>). - -**LINUX** -:: - - sudo <ise install path>/ISE_DS/common/bin/lin64/digilent/install_digilent.sh - -Afterwards either reboot or force udev to reload its rules by: -:: - - sudo udevadm control --reload - -The USRP-X series device should now be usable with all the tools mentioned above. - --------------------------------- -Load FPGA Images onto the Device --------------------------------- -The USRP-X Series device ships with a bitstream pre-programmed in the flash, -which is automatically loaded onto the FPGA during device power-up. However, -a new FPGA image can be configured over the PCI Express interface or the -on-board USB-JTAG programmer. This process can be seen as a "one-time load", in -that if you power-cycle the device, it will not retain the FPGA image. - -Please note that this process is *different* than replacing the FPGA image -stored in the flash, which will then be automatically loaded the next time the -device is reset. - -^^^^^^^^^^^^^^^^^^ -FPGA Image Flavors -^^^^^^^^^^^^^^^^^^ -The USRP-X Series devices contains two SFP+ ports for the two Ethernet channels. -Because the SFP+ ports support both 1 Gigabit (SFP) and 10 Gigabit (SFP+) -transceivers, several FPGA images are shipped with UHD to determine the -behavior of the above interfaces. - -+---------------------+------------------------+------------------------+ -|  FPGA Image Flavor |  SFP+ Port 0 Interface |  SFP+ Port 1 Interface | -+=====================+========================+========================+ -|  HGS (Default) |  1 Gigabit Ethernet |  10 Gigabit Ethernet  | -+---------------------+------------------------+------------------------+ -|  XGS  |  10 Gigabit Ethernet |  10 Gigabit Ethernet  | -+---------------------+------------------------+------------------------+ - -FPGA images are shipped in 2 formats: - -* **LVBITX**: LabVIEW FPGA configuration bitstream format (for use over PCI Express and Ethernet) -* **BIT**: Xilinx configuration bitstream format (for use over Ethernet and JTAG) - -To get the latest images, simply use the uhd_images_downloader script: - -**UNIX:** - -:: - - sudo uhd_images_downloader - -**Windows:** - -:: - - <path_to_python.exe> <install-path>/bin/uhd_images_downloader.py - - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Use PCI Express to load FPGA images -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -UHD requires a valid LabVIEW FPGA configuration bitstream file (LVBITX) to use the USRP-X Series -device over the PCI Express bus. LabVIEW FPGA is **NOT** required to use UHD with a USRP-X Series device. -Because FPGA configuration is a part of normal operation over PCI Express, there is no setup required -before running UHD. - -The **fpga** tag can be set in the optional device args passed to indicate the FPGA image flavor to UHD. -If the above tag is specified, UHD will attempt to load the FPGA image with the requested flavor from the -UHD images directory. If the tag is not specified, UHD will automatically detect the flavor of the image -and attempt to load the corresponding configuration bitstream onto the device. Note that if UHD detects -that the requested image is already loaded onto the FPGA then it will not reload it. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Use JTAG to load FPGA images -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The USRP-X Series device features an on-board USB-JTAG programmer that can be accessed on the front-panel -of the device. The iMPACT tool in the `Xilinx Programming Tools <http://www.xilinx.com/support/download/index.htm>`_ package can be used to load an image over -the JTAG interface. This can be useful for unbricking devices. - -If you have iMPACT installed, you can use the impact_jtag_programmer.sh tool to install images. Make sure your X3x0 is powered on and connected to your computer using the front panel USB JTAG connector (USB 2.0 is fine for this). Then run the tool: - -:: - - <path_to_uhd_tools>/impact_jtag_programmer.sh --fpga-path=<fpga_image_path> - ---------------------------------------- -Load the Images onto the On-board Flash ---------------------------------------- -To change the FPGA image stored in the on-board flash, the USRP-X Series device -can be reprogrammed over the network or PCI Express. Once you have programmed an -image into the flash, that image will be automatically loaded on the FPGA -during the device boot-up sequence. - -**Note:** -Different hardware revisions require different FPGA images. -Determine the revision number from the sticker on the rear of the device. -If you are manually specifying an FPGA path, the utility will not try to -detect your device information, and you will need to use this number to -select which image to burn. - -**Note:** -The burner utility will default to using the appropriate BIT file if no custom -FPGA image path is specified, but it is compatible with BIN, BIT, and LVBITX -images. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Use the burner tool over Ethernet -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -:: - - Automatic FPGA path, detect image type: - usrp_x3xx_fpga_burner --addr=<IP address> - - Automatic FPGA path, select image type: - usrp_x3xx_fpga_burner --addr=<IP address> --type=<HGS or XGS> - - Manual FPGA path: - usrp_x3xx_fpga_burner --addr=<IP address> --fpga-path=<path to FPGA image> - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Use the burner tool over PCI Express -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -:: - - Automatic FPGA path, detect image type: - usrp_x3xx_fpga_burner --resource=<NI-RIO resource> - - Automatic FPGA path, select image type: - usrp_x3xx_fpga_burner --resource=<NI-RIO resource> --type=<HGS or XGS> - - Manual FPGA path: - usrp_x3xx_fpga_burner --resource=<NI-RIO resource> --fpga-path=<path to FPGA image> - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Device recovery and bricking -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -It is possible to put the device into an unusable state by loading bad images ("bricking"). -Fortunately, the USRP-X Series device can be loaded with a good image temporarily using the USB-JTAG interface. -Once booted into the safe image, the user can once again load images onto the device over Ethernet or PCI Express. - ----------------- -Setup Networking ----------------- -The USRP-X Series only supports Gigabit and Ten Gigabit Ethernet and will not work with a 10/100 Mbps interface. - -**Please note that 10 Gigabit Ethernet defines the protocol, not necessary the -medium. For example, you may use 10GigE over optical with optical SFP+ -transceiver modules.** - -^^^^^^^^^^^^^^^^^^^^^^^^ -Setup the host interface -^^^^^^^^^^^^^^^^^^^^^^^^ -The USRP-X Series communicates at the IP/UDP layer over the Gigabit and Ten Gigabit Ethernet. -The default IP address for the USRP X300/X310 device depends on the Ethernet Port and interface used. -You must configure the host Ethernet interface with a static IP address on the same subnet as the connected -device to enable communication, as shown in the following table: - -+---------------+-------------------------+----------------+----------------+---------------+---------------+ -|  Ethernet | USRP |  Default USRP |  Host Static  | Host Static | Address | -| Interface | Ethernet Port | IP Address | IP Address | Subnet Mask | EEPROM key | -+===============+=========================+================+================+===============+===============+ -|  Gigabit |  Port 0 (HGS Image) |  192.168.10.2 | 192.168.10.1 | 255.255.255.0 | ``ip-addr0`` | -+---------------+-------------------------+----------------+----------------+---------------+---------------+ -|  Ten Gigabit |  Port 0 (XGS Image) |  192.168.30.2 | 192.168.30.1 | 255.255.255.0 | ``ip-addr2`` | -+---------------+-------------------------+----------------+----------------+---------------+---------------+ -|  Ten Gigabit |  Port 1 (HGS/XGS Image) |  192.168.40.2 | 192.168.40.1 | 255.255.255.0 | ``ip-addr3`` | -+---------------+-------------------------+----------------+----------------+---------------+---------------+ - -As you can see, the X300/X310 actually stores different IP addresses, which all address the device differently: Each combination of Ethernet port and interface type (i.e., Gigabit or Ten Gigabit) has its own IP address. As an example, when addressing the device through 1 Gigabit Ethernet on its first port (Port 0), the relevant IP address is the one stored in the EEPROM with key ``ip-addr0``, or 192.168.10.2 by default. - -See the `system configuration manual <./usrp_x3x0_config.html>`_ on details -how to change your machine's IP address and MTU size to work well with the X300. - -^^^^^^^^^^^^^^^^^^^^^^^^^ -Multiple devices per host -^^^^^^^^^^^^^^^^^^^^^^^^^ -For maximum throughput, one Ethernet interface per USRP is recommended, -although multiple devices may be connected via an Ethernet switch. -In any case, each Ethernet interface should have its own subnet, -and the corresponding USRP device should be assigned an address in that subnet. -Example: - -**Configuration for USRP-X Series device 0:** - -* Ethernet interface IPv4 address: **192.168.10.1** -* Ethernet interface subnet mask: **255.255.255.0** -* USRP-X Series device IPv4 address: **192.168.10.2** - -**Configuration for USRP-X Series device 1:** - -* Ethernet interface IPv4 address: **192.168.110.1** -* Ethernet interface subnet mask: **255.255.255.0** -* USRP-X Series device IPv4 address: **192.168.110.2** - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Change the USRP's IP address -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -You may need to change the USRP's IP address for several reasons: - -* to satisfy your particular network configuration -* to use multiple USRP-X Series devices on the same host computer -* to set a known IP address into USRP (in case you forgot) - -To change the USRP's IP address, -you must know the current address of the USRP, -and the network must be setup properly as described above. -You must also know which IP address of the X300 you want to change, as identified by their address EEPROM key (e.g. ``ip-addr0``, see the table above). -Run the following commands: - -**UNIX:** - -:: - - cd <install-path>/lib/uhd/utils - ./usrp_burn_mb_eeprom --args=<optional device args> --key=ip-addr0 --val=192.168.10.3 - -**Windows:** - -:: - - cd <install-path>\lib\uhd\utils - usrp_burn_mb_eeprom.exe --args=<optional device args> --key=ip-addr0 --val=192.168.10.3 - ---------------------- -Addressing the Device ---------------------- - -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Single device configuration -^^^^^^^^^^^^^^^^^^^^^^^^^^^ -In a single-device configuration, -the USRP device must have a unique IPv4 address on the host computer. -The USRP can be identified through its IPv4 address, resolvable hostname, NI-RIO resource name or by other means. -See the application notes on `device identification <./identification.html>`_. -Use this addressing scheme with the **multi_usrp** interface (not a typo!). - -Example device address string representation for a USRP-X Series device with IPv4 address **192.168.10.2**: - -:: - - addr=192.168.10.2 - -Example device address string representation for a USRP-X Series device with RIO resource name **RIO0** over PCI Express: - -:: - - resource=RIO0 - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Multiple device configuration -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -In a multi-device configuration, -each USRP device must have a unique IPv4 address on the host computer. -The device address parameter keys must be suffixed with the device index. -Each parameter key should be of the format <key><index>. -Use this addressing scheme with the **multi_usrp** interface. - -* The order in which devices are indexed corresponds to the indexing of the transmit and receive channels. -* The key indexing provides the same granularity of device identification as in the single device case. - -Example device address string representation for 2 USRPs with IPv4 addresses **192.168.10.2** and **192.168.20.2**: - -:: - - addr0=192.168.10.2, addr1=192.168.20.2 - - ----------------------- -Communication Problems ----------------------- -When setting up a development machine for the first time, -you may have various difficulties communicating with the USRP device. -The following tips are designed to help narrow down and diagnose the problem. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -RuntimeError: no control response -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -This is a common error that occurs when you have set the subnet of your network -interface to a different subnet than the network interface of the USRP device. For -example, if your network interface is set to **192.168.20.1**, and the USRP device is -**192.168.10.2** (note the difference in the third numbers of the IP addresses), you -will likely see a 'no control response' error message. - -Fixing this is simple - just set the your host PC's IP address to the same -subnet as that of your USRP device. Instructions for setting your IP address are in the -previous section of this documentation. - -^^^^^^^^^^^^^^^ -Firewall issues -^^^^^^^^^^^^^^^ -When the IP address is not specified, -the device discovery broadcasts UDP packets from each Ethernet interface. -Many firewalls will block the replies to these broadcast packets. -If disabling your system's firewall -or specifying the IP address yields a discovered device, -then your firewall may be blocking replies to UDP broadcast packets. -If this is the case, we recommend that you disable the firewall -or create a rule to allow all incoming packets with UDP source port **49152**. - -^^^^^^^^^^^^^^^ -Ping the device -^^^^^^^^^^^^^^^ -The USRP device will reply to ICMP echo requests ("ping"). -A successful ping response means that the device has booted properly -and that it is using the expected IP address. - -:: - - ping 192.168.10.2 - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -USRP device not enumerated (Linux) -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -UHD requires the RIO device manager service to be running in order to -communicate with an X-Series USRP over PCIe. This service is installed as -a part of the USRP RIO (or NI-USRP) installer. On Linux, the service is not -started at system boot time, and is left to the user to control. To start it, -run the following command: - -:: - - sudo niusrprio_pcie start - -If the device still does not enumerate after starting the device manager, make sure that the host computer -has successfully detected it. You can do so by running the following command: - -:: - - lspci -k -d 1093:c4c4 - -A device similar to the following should be detected: - -:: - - $ lspci -k -d 1093:c4c4 - 04:00.0 Signal processing controller: National Instruments ... - Subsystem: National Instruments Device 76ca - Kernel driver in use: niusrpriok_shipped - -* A USRP X300 should appear with 'Subsystem: National Instruments Device 7736' -* A USRP X310 should appear with 'Subsystem: National Instruments Device 76ca' - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -USRP device not enumerated (Windows) -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -UHD requires the RIO device manager service to be running in order to -communicate with an X-Series USRP over PCIe. -This service is installed as a part of the USRP RIO (or NI-USRP) installer. On Windows, it can be found in -the **Services** section in the Control Panel and it is started at system boot time. To ensure that the -service is indeed started, navigate to the Services tag in the Windows Task Manager and ensure that the -status of **niusrpriorpc** is "Running". - -If the device still does not enumerate after starting the device manager, make sure that the host computer -has successfully detected it. You can do so by checking if your device shows up in the Windows Device Manager. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Monitor the host network traffic -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Use Wireshark to monitor packets sent to and received from the device. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Observe Ethernet port LEDs -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -When there is network traffic arriving at the Ethernet port, LEDs will light up. -You can use this to make sure the network connection is correctly set up, e.g. -by pinging the USRP and making sure the LEDs start to blink. - --------------- -Hardware Notes --------------- - -^^^^^^^^^^^ -Front Panel -^^^^^^^^^^^ - -.. image:: ./res/x3x0_fp_overlay.png - :scale: 80% - :align: left - -* **JTAG**: USB connector for the on-board USB-JTAG programmer -* **RF A Group** - - * **TX/RX LED**: Indicates that data is streaming on the TX/RX channel on daughterboard A - * **RX2 LED**: Indicates that data is streaming on the RX2 channel on daughterboard A - -* **REF**: Indicates that the external Reference Clock is locked -* **PPS**: Indicates a valid PPS signal by pulsing once per second -* **AUX I/O**: Front panel GPIO connector. -* **GPS**: Indicates that GPS reference is locked -* **LINK**: Indicates that the host computer is communicating with the device (Activity) - -* **RF B Group** - - * **TX/RX LED**: Indicates that data is streaming on the TX/RX channel on daughterboard B - * **RX2 LED**: Indicates that data is streaming on the RX2 channel on daughterboard B - -* **PWR**: Power switch - -^^^^^^^^^^ -Rear Panel -^^^^^^^^^^ - -.. image:: ./res/x3x0_rp_overlay.png - :scale: 80% - :align: left - - -* **PWR**: Connector for the USRP-X Series power supply -* **1G/10G ETH**: SFP+ ports for Ethernet interfaces -* **REF OUT**: Output port for the exported reference clock -* **REF IN**: Reference clock input -* **PCIe x4**: Connector for Cabled PCI Express link -* **PPS/TRIG OUT**: Output port for the PPS signal -* **PPS/TRIG IN**: Input port for the PPS signal -* **GPS**: Connection for the GPS antenna - -^^^^^^^^^^^^^^^^^^ -Ref Clock - 10 MHz -^^^^^^^^^^^^^^^^^^ -Using an external 10 MHz reference clock, a square wave will offer the best phase -noise performance, but a sinusoid is acceptable. The power level of the reference clock cannot exceed +15 dBm. - -^^^^^^^^^^^^^^^^^^^^^^ -PPS - Pulse Per Second -^^^^^^^^^^^^^^^^^^^^^^ -Using a PPS signal for timestamp synchronization requires a square wave signal with the following a 5Vpp amplitude. - -To test the PPS input, you can use the following tool from the UHD examples: - -* **<args>** are device address arguments (optional if only one USRP device is on your machine) - -:: - - cd <install-path>/lib/uhd/examples - ./test_pps_input --args=<args> - -^^^^^^^^^^^^^^ -Internal GPSDO -^^^^^^^^^^^^^^ -Please see the `Internal GPSDO Application Notes <./gpsdo_x3x0.html>`_ -for information on configuring and using the internal GPSDO. - -^^^^^^^^^^^^^^^^ -Front Panel GPIO -^^^^^^^^^^^^^^^^ - -Connector -::::::::: - -.. image:: ./res/x3x0_gpio_conn.png - :scale: 75% - :align: left - -Pin Mapping -::::::::::: - -* Pin 1: +3.3V -* Pin 2: Data[0] -* Pin 3: Data[1] -* Pin 4: Data[2] -* Pin 5: Data[3] -* Pin 6: Data[4] -* Pin 7: Data[5] -* Pin 8: Data[6] -* Pin 9: Data[7] -* Pin 10: Data[8] -* Pin 11: Data[9] -* Pin 12: Data[10] -* Pin 13: Data[11] -* Pin 14: 0V -* Pin 15: 0V - - -Please see the `GPIO API Notes <./gpio_api.html>`_ for information on configuring and using the GPIO bus. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Debugging custom FPGA designs with Xilinx Chipscope -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Xilinx chipscope allows for debugging custom FPGA designs similar to a logic analyzer. -USRP-X series devices can be used with Xilinx chipscope using the onboard USB JTAG connector. - -Further information on how to use Chipscope can be found in the Xilinx Chipscope Pro Software and Cores User Guide (UG029). - -------------- -Miscellaneous -------------- - -^^^^^^^^^^^^^^^^^^^^ -Multiple RX channels -^^^^^^^^^^^^^^^^^^^^ -There are two complete DDC and DUC DSP chains in the FPGA. In the single channel case, -only one chain is ever used. To receive from both channels, the user must set the **RX** or **TX** -subdevice specification. - -In the following example, a TVRX2 is installed. -Channel 0 is sourced from subdevice **RX1**, -and channel 1 is sourced from subdevice **RX2** (**RX1** and **RX2** are antenna connectors on the TVRX2 daughterboard). - -:: - - usrp->set_rx_subdev_spec("A:RX1 A:RX2"); - - -^^^^^^^^^^^^^^^^^ -Available Sensors -^^^^^^^^^^^^^^^^^ -The following sensors are available for the USRP-X Series motherboards; -they can be queried through the API. - -* **ref_locked** - clock reference locked (internal/external) -* Other sensors are added when the GPSDO is enabled diff --git a/host/docs/usrp_x3x0_config.dox b/host/docs/usrp_x3x0_config.dox new file mode 100644 index 000000000..935e4cc1c --- /dev/null +++ b/host/docs/usrp_x3x0_config.dox @@ -0,0 +1,277 @@ +/*! \page page_usrp_x3x0_config System Configuration for USRP X3x0 Series + +\tableofcontents + +\section x3x0cfg_hostpc Configuring your Host PC + +The USRP X3x0 is capable of delivering very fast sample rates to the +host PC, and even high-powered desktops can have trouble keeping up at +the higher rates. You can improve the performance of your host by +configuring a number of settings that affect the performance of your +computer. + +These are: + +- Kernel Version +- Network Configuration +- Power Management Configuration +- Real-Time & Priority Scheduling +- Building with ORC & Volk + +These items are covered in more detail, below. + +\subsection x3x0cfg_hostpc_kernel Kernel Version + +Performance issues may be encountered with Linux kernels earlier than +3.11. Ettus Research strongly recommends using kernel version 3.11 or +higher for high sample rates. + +\subsection x3x0cfg_hostpc_netcfg Network Configuration + +When using Ethernet interfaces to communicate with the device, it is +necessary to configure a number of facets regarding your network +connection. + +\subsubsection x3x0cfg_hostpc_netcfg_nwmgr Configuring NetworkManager + +Fedora and Ubuntu both use NetworkManager to manage network connections. +Unfortunately, NetworkManager often tries to take control of a +connection and will disconnect the interface. + +You should open your NetworkManager configuration and tell it to ignore +the network interface you are using. **This is not the same as simply +setting a static IP address.** You *must* tell NetworkManager to ignore +the interface. + +\subsubsection x3x0cfg_hostpc_netcfg_ip Configuring the host's IP address + +On a Linux system, you can add a static IP address very easily by using the 'ip' command: + + sudo ip addr add 192.168.10.1/24 dev <interface> + +Note that `<interface>` is usually something like `eth0`. You can discover the +names of the network interfaces in your computer by running: + + ip addr show + +\subsubsection x3x0cfg_hostpc_netcfg_sockbuff Configuring the Socket Buffers + +It is necessary to increase the maximum size of the socket buffers to +avoid potential overflows and underruns at high sample rates. Add the +following entries into /etc/sysctl.conf (root privileges required): + + net.core.rmem_max=33554432 + net.core.wmem_max=33554432 + +Either restart the system or issue the following commands: + + sudo sysctl -w net.core.rmem_max=33554432 + sudo sysctl -w net.core.wmem_max=33554432 + +\subsubsection x3x0cfg_hostpc_netcfg_mtu Configuring the MTU + +In order to achieve maximum performance, we recommend setting the MTU +size to 9000 for 10 GigE and 1500 for 1 GigE. It is possible to use +smaller MTUs, but this can affect performance. With some NICs, setting +the MTU too high can also cause issues. To set the MTU to 9000, you can +use the following command: + + sudo ifconfig <interface> mtu 9000 # For 10 GigE + sudo ifconfig <interface> mtu 1500 # For 1 GigE + +Using these MTUs will set the frame sizes for UHD communication to 8000 +and 1472, respectively. + +In some cases, specifying the frame size manually by adding the argument +`<send/recv>_frame_size=1472` can solve issues. Note that a frame +size of 1472 will limit the available sampling rate, although this is +not a problem on 1 GigE. + +\subsubsection x3x0cfg_hostpc_netcfg_firewall Configuring the Firewall + +Many Linux distributions come installed with a Firewall, by default. The +Firewall will often interfere with your ability to communicate with your +USRP. You should configure your firewall to "trust" the interface you +are using. Setting this properly depends on your OS and firewall +configuration method. + +When using UHD software, if an IP address for the USRP-X Series device is not specified, +the software will use UDP broadcast packets to locate the USRP-X Series device. +On some systems, the firewall will block UDP broadcast packets. +It is recommended that you change or disable your firewall settings. + +\subsubsection x3x0cfg_hostpc_netcfg_if Interface Configuration File (Fedora) + +On Fedora systems, you can configure the network interface mostly from +one place (with the exception of the socket buffers). Each interface on +your system should have a file in: + + /etc/sysconfig/network-scripts/ + +As an example, if your 1GigE interface is "em1", your "ifcfg-em1" +configuration file should look something like this, when configured for +use with a USRP X3xx: + + TYPE="Ethernet" + BOOTPROTO="none" + IPADDR0="192.168.10.1" + DEFROUTE="yes" + IPV4_FAILURE_FATAL="no" + IPV6INIT="no" + IPV6_FAILURE_FATAL="no" + NAME="em1" + UUID="<specific to your device>" + ONBOOT="no" + HWADDR"<specific to your device>" + PEERDNS="yes" + PEERROUTES="yes" + ZONE="trusted" + MTU="9000" + NM_MANAGED="no" + +The above file was generated and modified on a Fedora 20 system. + +\subsection x3x0cfg_hostpc_pwr Power Management + +Power management on the host system attempts to save power by reducing +clock frequencies or even powering off devices while not in use. This +can lead to significant performance issues when trying to operate at +high sample rates. Ettus Research strongly recommends disabling all +power management. + +\subsubsection x3x0cfg_hostpc_pwr_cpugov Setting the CPU Governors + +In Linux, the CPU governors dictate the frequency at which the CPU +operates and attempt to reduce the CPU frequencies at certain times to +save power. When running at high sample rates, reduction of CPU +frequencies can cause significant performance issues. To prevent those +issues, set the governor to "performance". + +\b Ubuntu: + +1. Install cpufrequtils: + + sudo apt-get install cpufrequtils + +2. Edit `/etc/init.d/cpufrequtils` and set `GOVERNOR="performance"` on the + appropriate line (run as root): + + sed s/^GOVERNOR=.*$/GOVERNOR=\"performance\"/g /etc/init.d/cpufrequtils > /etc/init.d/cpufrequtils + +3. Restart cpufrequtils: + + sudo /etc/init.d/cpufrequtils restart + +\b Fedora: + + sudo cpupower frequency-set -g performance + +\subsection x3x0cfg_hostpc_rtprio Real-Time & Priority Scheduling + +Enabling real-time and priority scheduling can improve the total +processing throughput of your application. Priority scheduling should be +enabled for UHD, and real-time scheduling can be enabled by your +application. + +\subsubsection x3x0cfg_hostpc_rtprio_thread Thread Priority Scheduling with UHD + +For information regarding how to enable priority scheduling for UHD on +your system, please see \ref page_general. + +\subsubsection x3x0cfg_hostpc_rtprio_app Real-Time Scheduling in your Application + +Please note that turning on real-time scheduling in your application +**may lock up your computer** if the processor cannot keep up with the +application. You should generally avoid using real-time scheduling +unless you need to. + +Real-time scheduling is enabled via different methods depending on your +application and operating system. In GNU Radio Companion, it can be +turned on in each individual flowgraph. + +\subsection x3x0cfg_hostpc_volk Building with ORC & Volk + +Especially when running high-performance applications, processing +performance can be dramatically improved by SIMD instructions. UHD uses +ORC to provide SIMD capability, and GNU Radio includes a SIMD library +called "Volk". These should both be used to guarantee optimum +performance. + +\subsubsection x3x0cfg_hostpc_volk_orc Compiling UHD with ORC + +ORC, the <a href="http://code.entropywave.com/orc/">Oil Runtime Compiler</a>, +is a third-party compiler that UHD uses to create efficient SIMD code for +your particular computer. ORC is generally easily installed from your +OS's package manager. + +On Fedora: + + $ sudo yum update; sudo yum install orc-compiler orc-devel + +On Ubuntu: + + $ sudo apt-get update; sudo apt-get install liborc-<version> liborc-<version>-dev + +After installing ORC, when building UHD from source, you should see +"ORC" as one of the configured UHD components. + + -- ###################################################### + -- # UHD enabled components + -- ###################################################### + -- * LibUHD + <cut for brevity> + -- * ORC + +\subsubsection x3x0cfg_hostpc_volk_volk Compiling GNURadio with Volk + +If you are using GNURadio to build applications, you should compile +GNURadio with Volk. For instructions on how to do this, +<a href="http://gnuradio.org/redmine/projects/gnuradio/wiki/Volk">refer to the GNURadio wiki</a>. + +\section x3x0cfg_hosthw Host PC Hardware Selection + +\subsection x3x0cfg_hosthw_mb Motherboard + +Testing has shown that some motherboards do not provide enough PCIe bus +bandwidth to support higher sample rates. Motherboards with PCIe 3.0 are +required and the PCIe architecture of the motherboard should be +carefully considered. Slots with dedicated PCIe lanes should be used for +PCIe or 10GbE cards that will be connected to the X3x0 device. + +\subsection x3x0cfg_hosthw_10gige 10GbE NIC + +Intel or Myricom 10GbE NICs are recommended. Mellanox, SolarFlare, and +Chelsio 10GbE NICs are not currently recommended. The Ethernet card +should be plugged into the slot that has the most direct connection with +the CPU (PCIe lanes are not shared with another slot). Refer to the +motherboard manual for more information on PCIe architecture. + +\section x3x0cfg_hosthw_troubleshooting Troubleshooting Performance Issues + +The output on the host console provides indicators of performance issues +in the form of single upper-case letters. The following table lists the +letters, their meanings, and possible causes: + + Indicator |Meaning | Possible Causes + -----------|----------------------|--------------------------------------------------------------------------------- + O |Overflow on RX |- Data is not being consumed by user's application fast enough.<br>- CPU governor or other power management not configured correctly. + D |Dropped packet on RX |- Network hardware failure. (Check host NIC, cable, switch, etc...)<br>- PCIe bus on host cannot sustain throughput. (Check ethtool -S \<interface\>).<br>- CPU governor or other power management not configured correctly.<br>- Frame size might not work with the current NIC's MTU. + U |Underflow on TX |- Samples are not being produced by user's application fast enough.<br>- CPU governor or other power management not configured correctly. + L |Late packet (usually on MIMO TX)|- Samples are not being produced by user's application fast enough.<br>- CPU governor or other power management not configured correctly.<br>- Incorrect/invalid time_spec provided. + S |Sequence error on TX |- Network hardware failure. (Check host NIC, cable, switch, etc...)<br>- Frame size might not work with the current NIC's MTU. + +\subsection x3x0cfg_hosthw_troubleshooting_eth Troubleshooting Ethernet Issues + +1. First, check `ifconfig <interface>` to see if there are any errors + reported on the interface. If there are errors, it is most likely a + network hardware problem. +2. Next, check the output of `ethtool -S <interface>`. The output is + driver-specific, but may give important clues as to what may be + happening. For example, a high value on rx_missed_errors for an + Intel NIC indicates that the bus (i.e. PCIe) is not keeping up. +3. Finally, Wireshark can be used to validate the traffic between the + host and device and make sure there is no unwanted traffic on the + interface. + +*/ +// vim:ft=doxygen: diff --git a/host/docs/usrp_x3x0_config.rst b/host/docs/usrp_x3x0_config.rst deleted file mode 100644 index 4be247b04..000000000 --- a/host/docs/usrp_x3x0_config.rst +++ /dev/null @@ -1,319 +0,0 @@ -======================================================================== -UHD - System Configuration for USRP X3x0 Series -======================================================================== - -.. contents:: Table of Contents - ------------------------------------------------------------------------- -Configuring your Host PC ------------------------------------------------------------------------- - -The USRP X3x0 is capable of delivering very fast sample rates to the host PC, -and even high-powered desktops can have trouble keeping up at the higher rates. -You can improve the performance of your host by configuring a number of -settings that affect the performance of your computer. - -These are: - - * Kernel Version - * Network Configuration - * Power Management Configuration - * Real-Time & Priority Scheduling - * Building with ORC & Volk - -These items are covered in more detail, below. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Kernel Version -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Performance issues may be encountered with Linux kernels earlier than 3.11. -Ettus Research strongly recommends using kernel version 3.11 or higher for high -sample rates. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Network Configuration -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -When using Ethernet interfaces to communicate with the device, it is necessary -to configure a number of facets regarding your network connection. - -Configuring NetworkManager -------------------------------------- -Fedora and Ubuntu both use NetworkManager to manage network connections. -Unfortunately, NetworkManager often tries to take control of a connection and -will disconnect the interface. - -You should open your NetworkManager configuration and tell it to ignore the -network interface you are using. **This is not the same as simply setting -a static IP address.** You *must* tell NetworkManager to ignore the interface. - -Changing the host's IP address -------------------------------------- - -On a Linux system, you can add a static IP address very easily by using the -'ip' command: - -:: - - sudo ip addr add 192.168.10.1/24 dev <interface> - -Note that **<interface>** is usually something like **eth0**. You can discover the -names of the network interfaces in your computer by running: - -:: - - ip addr show - -Configuring the Socket Buffers -------------------------------------- -It is necessary to increase the maximum size of the socket buffers to avoid -potential overflows and underruns at high sample rates. Add the following -entries into /etc/sysctl.conf (root privileges required): - -:: - - net.core.rmem_max=33554432 - net.core.wmem_max=33554432 - -Either restart the system or issue the following commands: - -:: - - sudo sysctl -w net.core.rmem_max=33554432 - sudo sysctl -w net.core.wmem_max=33554432 - - -Configuring the MTU -------------------------------------- -In order to achieve maximum performance, we recommend setting the MTU size to -9000 for 10 GigE and 1500 for 1 GigE. It is possible to use smaller MTUs, but this -can affect performance. With some NICs, setting the MTU too high can also cause issues. -To set the MTU to 9000, you can use the following command: - -:: - - sudo ifconfig <interface> mtu 9000 # For 10 GigE - sudo ifconfig <interface> mtu 1500 # For 1 GigE - -Using these MTUs will set the frame sizes for UHD communication to 8000 and 1472, -respectively. - -In some cases, specifying the frame size manually by adding the argument -"<send/recv>_frame_size=1472" can solve issues. Note that a frame size of 1472 will limit -the available sampling rate, although this is not a problem on 1 GigE. - - -Configuring the Firewall -------------------------------------- -Many Linux distributions come installed with a Firewall, by default. The -Firewall will often interfere with your ability to communicate with your USRP. -You should configure your firewall to "trust" the interface you are using. -Setting this properly depends on your OS and firewall configuration method. - -When using UHD software, if an IP address for the USRP-X Series device is not specified, -the software will use UDP broadcast packets to locate the USRP-X Series device. -On some systems, the firewall will block UDP broadcast packets. -It is therefore recommended that you change or disable your firewall settings. - -Interface Configuration File (Fedora) -------------------------------------- -On Fedora systems, you can configure the network interface mostly from one -place (with the exception of the socket buffers). Each interface on your system -should have a file in: - -:: - - /etc/sysconfig/network-scripts/ - -As an example, if your 1GigE interface is "em1", your "ifcfg-em1" configuration -file should look something like this, when configured for use with a USRP X3xx: - -:: - - TYPE="Ethernet" - BOOTPROTO="none" - IPADDR0="192.168.10.1" - DEFROUTE="yes" - IPV4_FAILURE_FATAL="no" - IPV6INIT="no" - IPV6_FAILURE_FATAL="no" - NAME="em1" - UUID="<specific to your device>" - ONBOOT="no" - HWADDR"<specific to your device>" - PEERDNS="yes" - PEERROUTES="yes" - ZONE="trusted" - MTU="9000" - NM_MANAGED="no" - -The above file was generated and modified on a "Fedora 20" system. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Power Management -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Power management on the host system attempts to save power by reducing clock -frequencies or even powering off devices while not in use. This can lead to -significant performance issues when trying to operate at high sample rates. -Ettus Research strongly recommends disabling all power management. - - -Setting the CPU Governors -------------------------------------- -In Linux, the CPU governors dictate the frequency at which the CPU operates and -attempt to reduce the CPU frequencies at certain times to save power. When -running at high sample rates, reduction of CPU frequencies can cause -significant performance issues. To prevent those issues, set the governor to -"performance". - -**Ubuntu:** -1. Install cpufrequtils: - -:: - - sudo apt-get install cpufrequtils - -2. Edit /etc/init.d/cpufrequtils and set GOVERNOR="performance" on the appropriate line (run as root): - -:: - - sed s/^GOVERNOR=.*$/GOVERNOR=\"performance\"/g /etc/init.d/cpufrequtils > /etc/init.d/cpufrequtils - -3. Restart cpufrequtils: - -:: - - sudo /etc/init.d/cpufrequtils restart - -**Fedora:** - -:: - - sudo cpupower frequency-set -g performance - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Real-Time & Priority Scheduling -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Enabling real-time and priority scheduling can improve the total processing -throughput of your application. Priority scheduling should be enabled for UHD, -and real-time scheduling can be enabled by your application. - -Thread Priority Scheduling with UHD -------------------------------------- -For information regarding how to enable priority scheduling for UHD on your -system, please see the `General UHD Notes <./general.html#threading-notes>`_. - -Real-Time Scheduling in your Application ----------------------------------------- -Please note that turning on real-time scheduling in your application **may lock -up your computer** if the processor cannot keep up with the application. You -should generally avoid using real-time scheduling unless you need to. - -Real-time scheduling is enabled via different methods depending on your -application and operating system. In GNU Radio Companion, it can be turned on in -each individual flowgraph. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Building with ORC & Volk -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Especially when running high-performance applications, processing performance -can be dramatically improved by SIMD instructions. UHD uses ORC to provide SIMD -capability, and GNU Radio includes a SIMD library called "Volk". These should -both be used to guarantee optimum performance. - -Compiling UHD with ORC -------------------------------------- -ORC, the `Oil Runtime Compiler <http://code.entropywave.com/orc/>`_, is -a third-party compiler that UHD uses to create efficient SIMD code for your -particular computer. ORC is generally easily installed from your OS's package -manager. - -On Fedora: - -:: - - $ sudo yum update; sudo yum install orc-compiler orc-devel - -On Ubuntu: - -:: - - $ sudo apt-get update; sudo apt-get install liborc-<version> liborc-<version>-dev - -After installing ORC, when building UHD from source, you should see "ORC" as -one of the configured UHD components. - -:: - - -- ###################################################### - -- # UHD enabled components - -- ###################################################### - -- * LibUHD - <cut for brevity> - -- * ORC - -Compiling GNURadio with Volk -------------------------------------- -If you are using GNURadio to build applications, you should compile GNURadio -with Volk. For instructions on how to do this, `refer to the GNURadio wiki -<http://gnuradio.org/redmine/projects/gnuradio/wiki/Volk>`_. - - ------------------------------------------------------------------------- -Host PC Hardware Selection ------------------------------------------------------------------------- -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Motherboard -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Testing has shown that some motherboards do not provide enough PCIe bus -bandwidth to support higher sample rates. Motherboards with PCIe 3.0 are -required and the PCIe architecture of the motherboard should be carefully -considered. Slots with dedicated PCIe lanes should be used for PCIe or 10GbE -cards that will be connected to the X3x0 device. - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -10GbE NIC -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Intel or Myricom 10GbE NICs are recommended. Mellanox, SolarFlare, and Chelsio -10GbE NICs are not currently recommended. The Ethernet card should be plugged -into the slot that has the most direct connection with the CPU (PCIe lanes are -not shared with another slot). Refer to the motherboard manual for more -information on PCIe architecture. - ------------------------------------------------------------------------- -Troubleshooting Performance Issues ------------------------------------------------------------------------- -The output on the host console provides indicators of performance issues in the -form of single upper-case letters. The following table lists the letters, -their meanings, and possible causes: - -========= ====================== ==================================================================== -Indicator Meaning Possible Causes -========= ====================== ==================================================================== -O Overflow on RX - Data is not being consumed by user's application fast enough. - - CPU governor or other power management not configured correctly. -D Dropped packet on RX - Network hardware failure. (Check host NIC, cable, switch, etc...) - - PCIe bus on host cannot sustain throughput. (Check ethtool -S <interface>). - - CPU governor or other power management not configured correctly. - - Frame size might not work with the current NIC's MTU. -U Underflow on TX - Samples are not being produced by user's application fast enough. - - CPU governor or other power management not configured correctly. -L Late packet - Samples are not being produced by user's application fast enough. - (usually on MIMO TX) - CPU governor or other power management not configured correctly. - - Incorrect/invalid time_spec provided. -S Sequence error on TX - Network hardware failure. (Check host NIC, cable, switch, etc...) - - Frame size might not work with the current NIC's MTU. -========= ====================== ==================================================================== - -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Troubleshooting Ethernet Issues -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -1. First, check 'ifconfig <interface>' to see if there are any errors reported - on the interface. If there are errors, it is most likely a network hardware - problem. -2. Next, check the output of 'ethtool -S <interface>'. The output is - driver-specific, but may give important clues as to what may be happening. - For example, a high value on rx_missed_errors for an Intel NIC indicates - that the bus (i.e. PCIe) is not keeping up. -3. Finally, Wireshark can be used to validate the traffic between the host and - device and make sure there is no unwanted traffic on the interface. - diff --git a/host/docs/usrp_x3xx_fpga_burner.1 b/host/docs/usrp_x3xx_fpga_burner.1 index 5c1b085b7..f07e52401 100644 --- a/host/docs/usrp_x3xx_fpga_burner.1 +++ b/host/docs/usrp_x3xx_fpga_burner.1 @@ -47,7 +47,7 @@ GR-UHD documentation: .LP Other UHD programs: .sp -uhd_images_downloader(1) usrp2_card_burner(1) usrp_n2xx_simple_net_burner(1) +uhd_images_downloader(1) usrp2_card_burner(1) usrp_n2xx_simple_net_burner(1) octoclock_firmware_burner(1) .SH AUTHOR This manual page was written by Nicholas Corgan for the Debian project (but may be used by others). diff --git a/host/examples/CMakeLists.txt b/host/examples/CMakeLists.txt index 4f394bbef..1e6f2f013 100644 --- a/host/examples/CMakeLists.txt +++ b/host/examples/CMakeLists.txt @@ -1,5 +1,5 @@ # -# Copyright 2010-2013 Ettus Research LLC +# Copyright 2010-2014 Ettus Research LLC # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -39,6 +39,10 @@ SET(example_sources fpgpio.cpp ) +IF(ENABLE_OCTOCLOCK) + LIST(APPEND example_sources test_clock_synch.cpp) +ENDIF(ENABLE_OCTOCLOCK) + #for each source: build an executable and install FOREACH(example_source ${example_sources}) GET_FILENAME_COMPONENT(example_name ${example_source} NAME_WE) diff --git a/host/examples/benchmark_rate.cpp b/host/examples/benchmark_rate.cpp index 9e9aa67e9..03d8f3477 100644 --- a/host/examples/benchmark_rate.cpp +++ b/host/examples/benchmark_rate.cpp @@ -215,7 +215,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ //create a usrp device std::cout << std::endl; - uhd::device_addrs_t device_addrs = uhd::device::find(args); + uhd::device_addrs_t device_addrs = uhd::device::find(args, uhd::device::USRP); if (not device_addrs.empty() and device_addrs.at(0).get("type", "") == "usrp1"){ std::cerr << "*** Warning! ***" << std::endl; std::cerr << "Benchmark results will be inaccurate on USRP1 due to insufficient features.\n" << std::endl; diff --git a/host/examples/test_clock_synch.cpp b/host/examples/test_clock_synch.cpp new file mode 100644 index 000000000..7a4226345 --- /dev/null +++ b/host/examples/test_clock_synch.cpp @@ -0,0 +1,165 @@ +// +// Copyright 2014 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#include <iostream> + +#include <boost/format.hpp> +#include <boost/program_options.hpp> +#include <boost/thread/thread.hpp> + +#include <uhd/device.hpp> +#include <uhd/exception.hpp> +#include <uhd/usrp_clock/multi_usrp_clock.hpp> +#include <uhd/types/time_spec.hpp> +#include <uhd/usrp/multi_usrp.hpp> +#include <uhd/utils/safe_main.hpp> +#include <uhd/utils/thread_priority.hpp> + +namespace po = boost::program_options; + +using namespace uhd::usrp_clock; +using namespace uhd::usrp; + +void wait_for_pps(multi_usrp::sptr usrp, size_t chan, double timeout){ + boost::uint32_t last_pps_time = usrp->get_time_last_pps(chan).get_full_secs(); + boost::uint32_t system_time = uhd::time_spec_t::get_system_time().get_full_secs(); + boost::uint32_t exit_time = system_time + timeout; + bool detected_pps = false; + + //Otherwise, this would hang if the USRP doesn't detect any PPS + while(uhd::time_spec_t::get_system_time().get_full_secs() < exit_time){ + boost::uint32_t time_now = usrp->get_time_last_pps(chan).get_full_secs(); + if(last_pps_time < time_now){ + detected_pps = true; + break; + } + else last_pps_time = time_now; + } + if(not detected_pps) throw uhd::runtime_error(str(boost::format("%s did not detect a PPS signal.") + % usrp->get_usrp_tx_info()["mboard_serial"])); + +} + +void get_usrp_time(multi_usrp::sptr usrp, size_t chan, std::vector<boost::uint32_t> *times){ + wait_for_pps(usrp, chan, 2); + (*times)[chan] = usrp->get_time_now(chan).get_full_secs(); +} + +int UHD_SAFE_MAIN(int argc, char *argv[]){ + uhd::set_thread_priority_safe(); + + //Variables to be set by command line options + std::string clock_args, usrp_args; + boost::uint32_t max_interval, num_tests; + + //Set up program options + po::options_description desc("Allowed options"); + desc.add_options() + ("help", "Display this help message") + ("clock-args", po::value<std::string>(&clock_args), "Clock device arguments") + ("usrp-args", po::value<std::string>(&usrp_args), "USRP device arguments") + ("max-interval", po::value<boost::uint32_t>(&max_interval)->default_value(10000), "Maximum interval between comparisons (in ms)") + ("num-tests", po::value<boost::uint32_t>(&num_tests)->default_value(10), "Number of times to compare device times") + ; + po::variables_map vm; + po::store(po::parse_command_line(argc, argv, desc), vm); + po::notify(vm); + + //Print the help message + if (vm.count("help")){ + std::cout << std::endl << "Test Clock Synchronization" << std::endl << std::endl; + + std::cout << "This example shows how to use a clock device to" << std::endl + << "synchronize the time on multiple USRP devices." << std::endl << std::endl; + + std::cout << desc << std::endl; + return EXIT_SUCCESS; + } + + //Create a Multi-USRP-Clock device (currently OctoClock only) + std::cout << boost::format("\nCreating the Clock device with: %s") % clock_args << std::endl; + multi_usrp_clock::sptr clock = multi_usrp_clock::make(clock_args); + + //Make sure Clock configuration is correct + if(clock->get_sensor("gps_detected").value == "false"){ + throw uhd::runtime_error("No GPSDO detected on Clock."); + } + if(clock->get_sensor("using_ref").value != "internal"){ + throw uhd::runtime_error("Clock must be using an internal reference."); + } + + //Create a Multi-USRP device + std::cout << boost::format("\nCreating the USRP device with: %s") % usrp_args << std::endl; + multi_usrp::sptr usrp = multi_usrp::make(usrp_args); + + //Store USRP device serials for useful output + std::vector<std::string> serials; + for(size_t ch = 0; ch < usrp->get_num_mboards(); ch++){ + serials.push_back(usrp->get_usrp_tx_info(ch)["mboard_serial"]); + } + + std::cout << std::endl << "Checking USRP devices for lock." << std::endl; + bool all_locked = true; + for(size_t ch = 0; ch < usrp->get_num_mboards(); ch++){ + std::string ref_locked = usrp->get_mboard_sensor("ref_locked",ch).value; + std::cout << boost::format(" * %s: %s") % serials[ch] % ref_locked << std::endl; + + if(ref_locked != "true") all_locked = false; + } + if(not all_locked) std::cout << std::endl << "WARNING: One or more devices not locked." << std::endl; + + //Get GPS time to initially set USRP devices + std::cout << std::endl << "Querying Clock for time and setting USRP times..." << std::endl << std::endl; + boost::uint32_t clock_time = clock->get_time(); + usrp->set_time_unknown_pps(uhd::time_spec_t(double(clock_time+2))); + + //Wait for next PPS to start polling + wait_for_pps(usrp, 0, 2); + + srand(time(NULL)); + + std::cout << boost::format("\nRunning %d comparisons at random intervals.") % num_tests << std::endl << std::endl; + boost::uint32_t num_matches = 0; + for(size_t i = 0; i < num_tests; i++){ + //Wait random time before querying + boost::uint16_t wait_time = rand() % max_interval; + boost::this_thread::sleep(boost::posix_time::milliseconds(wait_time)); + + //Get all times before output + std::vector<boost::uint32_t> usrp_times(usrp->get_num_mboards()); + boost::thread_group thread_group; + clock_time = clock->get_time(); + for(size_t j = 0; j < usrp->get_num_mboards(); j++){ + thread_group.create_thread(boost::bind(&get_usrp_time, usrp, j, &usrp_times)); + } + //Wait for threads to complete + thread_group.join_all(); + + std::cout << boost::format("Comparison #%d") % (i+1) << std::endl; + bool all_match = true; + std::cout << boost::format(" * Clock time: %d") % clock_time << std::endl; + for(size_t j = 0; j < usrp->get_num_mboards(); j++){ + std::cout << boost::format(" * %s time: %d") % serials[j] % usrp_times[j] << std::endl; + if(usrp_times[j] != clock_time) all_match = false; + } + if(all_match) num_matches++; + } + + std::cout << std::endl << boost::format("Number of matches: %d/%d") % num_matches % num_tests << std::endl; + + return EXIT_SUCCESS; +} diff --git a/host/examples/test_dboard_coercion.cpp b/host/examples/test_dboard_coercion.cpp index e23390506..cf6c08359 100644 --- a/host/examples/test_dboard_coercion.cpp +++ b/host/examples/test_dboard_coercion.cpp @@ -362,7 +362,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ //Create a USRP device std::cout << std::endl; - uhd::device_addrs_t device_addrs = uhd::device::find(args); + uhd::device_addrs_t device_addrs = uhd::device::find(args, uhd::device::USRP); std::cout << boost::format("Creating the USRP device with: %s...") % args << std::endl; uhd::usrp::multi_usrp::sptr usrp = uhd::usrp::multi_usrp::make(args); std::cout << std::endl << boost::format("Using Device: %s") % usrp->get_pp_string() << std::endl; diff --git a/host/examples/transport_hammer.cpp b/host/examples/transport_hammer.cpp index 3f233b2a5..32e344e3e 100644 --- a/host/examples/transport_hammer.cpp +++ b/host/examples/transport_hammer.cpp @@ -213,7 +213,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ //create a usrp device std::cout << std::endl; - uhd::device_addrs_t device_addrs = uhd::device::find(args); + uhd::device_addrs_t device_addrs = uhd::device::find(args, uhd::device::USRP); if (not device_addrs.empty() and device_addrs.at(0).get("type", "") == "usrp1"){ std::cerr << "*** Warning! ***" << std::endl; std::cerr << "Results will be inaccurate on USRP1 due to insufficient features.\n" << std::endl; diff --git a/host/include/uhd/CMakeLists.txt b/host/include/uhd/CMakeLists.txt index 2827cb826..318577b7c 100644 --- a/host/include/uhd/CMakeLists.txt +++ b/host/include/uhd/CMakeLists.txt @@ -1,5 +1,5 @@ - -# Copyright 2010-2011,2013 Ettus Research LLC +# +# Copyright 2010-2011,2013-2014 Ettus Research LLC # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -15,10 +15,10 @@ # along with this program. If not, see <http://www.gnu.org/licenses/>. # - ADD_SUBDIRECTORY(transport) ADD_SUBDIRECTORY(types) ADD_SUBDIRECTORY(usrp) +ADD_SUBDIRECTORY(usrp_clock) ADD_SUBDIRECTORY(utils) UHD_INSTALL(FILES diff --git a/host/include/uhd/device.hpp b/host/include/uhd/device.hpp index b54ffc5f7..5b4a2fe07 100644 --- a/host/include/uhd/device.hpp +++ b/host/include/uhd/device.hpp @@ -1,5 +1,5 @@ // -// Copyright 2010-2011 Ettus Research LLC +// Copyright 2010-2011,2014 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -32,8 +32,8 @@ namespace uhd{ class property_tree; //forward declaration /*! - * The usrp device interface represents the usrp hardware. - * The api allows for discovery, configuration, and streaming. + * The device interface represents the hardware. + * The API allows for discovery, configuration, and streaming. */ class UHD_API device : boost::noncopyable{ @@ -42,6 +42,13 @@ public: typedef boost::function<device_addrs_t(const device_addr_t &)> find_t; typedef boost::function<sptr(const device_addr_t &)> make_t; + //! Device type, used as a filter in make + enum device_filter_t { + ANY, + USRP, + CLOCK + }; + /*! * Register a device into the discovery and factory system. * @@ -50,32 +57,35 @@ public: */ static void register_device( const find_t &find, - const make_t &make + const make_t &make, + const device_filter_t filter ); /*! - * \brief Find usrp devices attached to the host. + * \brief Find devices attached to the host. * * The hint device address should be used to narrow down the search * to particular transport types and/or transport arguments. * * \param hint a partially (or fully) filled in device address - * \return a vector of device addresses for all usrps on the system + * \param filter an optional filter to exclude USRP or clock devices + * \return a vector of device addresses for all devices on the system */ - static device_addrs_t find(const device_addr_t &hint); + static device_addrs_t find(const device_addr_t &hint, device_filter_t filter = ANY); /*! - * \brief Create a new usrp device from the device address hint. + * \brief Create a new device from the device address hint. * * The make routine will call find and pick one of the results. * By default, the first result will be used to create a new device. * Use the which parameter as an index into the list of results. * * \param hint a partially (or fully) filled in device address + * \param filter an optional filter to exclude USRP or clock devices * \param which which address to use when multiple are found * \return a shared pointer to a new device instance */ - static sptr make(const device_addr_t &hint, size_t which = 0); + static sptr make(const device_addr_t &hint, device_filter_t filter = ANY, size_t which = 0); /*! \brief Make a new receive streamer from the streamer arguments * @@ -94,10 +104,14 @@ public: //! Get access to the underlying property structure uhd::property_tree::sptr get_tree(void) const; + //! Get device type + device_filter_t get_device_type() const; + #include <uhd/device_deprecated.ipp> protected: uhd::property_tree::sptr _tree; + device_filter_t _type; }; } //namespace uhd diff --git a/host/include/uhd/usrp_clock/CMakeLists.txt b/host/include/uhd/usrp_clock/CMakeLists.txt new file mode 100644 index 000000000..7cd5aa9d3 --- /dev/null +++ b/host/include/uhd/usrp_clock/CMakeLists.txt @@ -0,0 +1,23 @@ +# +# Copyright 2014 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +UHD_INSTALL(FILES + octoclock_eeprom.hpp + multi_usrp_clock.hpp + DESTINATION ${INCLUDE_DIR}/uhd/octoclock + COMPONENT headers +) diff --git a/host/include/uhd/usrp_clock/multi_usrp_clock.hpp b/host/include/uhd/usrp_clock/multi_usrp_clock.hpp new file mode 100644 index 000000000..0b50b32ae --- /dev/null +++ b/host/include/uhd/usrp_clock/multi_usrp_clock.hpp @@ -0,0 +1,105 @@ +// +// Copyright 2014 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#ifndef INCLUDED_UHD_MULTI_USRP_CLOCK_HPP +#define INCLUDED_UHD_MULTI_USRP_CLOCK_HPP + +#include <string> +#include <vector> + +#include <uhd/config.hpp> +#include <uhd/device.hpp> +#include <uhd/types/device_addr.hpp> +#include <uhd/types/sensors.hpp> + +namespace uhd{ namespace usrp_clock{ + +/*! + * The Multi-USRP-Clock device class: + * + * This class facilitates ease-of-use for must use-case scenarios when + * using clock devices with UHD. This class can be used with a + * single clock device or with multiple clock devices connected to the same + * host. + * + * To create a multi_usrp_clock out of a single USRP Clock: + * + * <pre> + * device_addr_t dev; + * dev["addr"] = 192.168.10.3; + * multi_usrp_clock::sptr clock = multi_usrp_clock::make(dev); + * </pre> + * + * To create a multi_usrp_clock out of multiple clock devices: + * + * <pre> + * device_addr_t dev; + * dev["addr0"] = 192.168.10.3; + * dev["addr1"] = 192.168.10.4; + * multi_usrp_clock::sptr clock = multi_usrp_clock::make(dev); + * </pre> + */ +class UHD_API multi_usrp_clock : boost::noncopyable { +public: + typedef boost::shared_ptr<multi_usrp_clock> sptr; + + /*! + * Make a new Multi-USRP-Clock from the given device address. + * \param dev_addr the device address + * \return a new Multi-USRP-Clock object + */ + static sptr make(const device_addr_t &dev_addr); + + /*! + * Return the underlying device. + * This allows direct access to the EEPROM and sensors. + * \return the device object within this Multi-USRP-Clock + */ + virtual device::sptr get_device(void) = 0; + + /*! + * Get a printable summary for this USRP Clock configuration. + * \return a printable string + */ + virtual std::string get_pp_string(void) = 0; + + //! Get the number of USRP Clocks in this configuration. + virtual size_t get_num_boards(void) = 0; + + //! Get time from device + virtual boost::uint32_t get_time(size_t board = 0) = 0; + + /*! + * Get a USRP Clock sensor value. + * \param name the name of the sensor + * \param board the board index (0 to M-1) + * \return a sensor value object + */ + virtual sensor_value_t get_sensor(const std::string &name, size_t board = 0) = 0; + + /*! + * Get a list of possible USRP Clock sensor names. + * \param board the board index (0 to M-1) + * \return a vector of sensor names + */ + virtual std::vector<std::string> get_sensor_names(size_t board = 0) = 0; +}; + +} //namespace +} //namespace + +#endif /* INCLUDED_UHD_MULTI_USRP_CLOCK_HPP */ diff --git a/host/include/uhd/usrp_clock/octoclock_eeprom.hpp b/host/include/uhd/usrp_clock/octoclock_eeprom.hpp new file mode 100644 index 000000000..a521000dd --- /dev/null +++ b/host/include/uhd/usrp_clock/octoclock_eeprom.hpp @@ -0,0 +1,61 @@ +// +// Copyright 2014 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#ifndef INCLUDED_UHD_USRP_CLOCK_OCTOCLOCK_EEPROM_HPP +#define INCLUDED_UHD_USRP_CLOCK_OCTOCLOCK_EEPROM_HPP + +#include <uhd/config.hpp> +#include <uhd/transport/udp_simple.hpp> +#include <uhd/types/dict.hpp> +#include <string> + +namespace uhd{ namespace usrp_clock{ + +/*! + * The OctoClock EEPROM object: + * Knows how to read and write the OctoClock EEPROM. + * The class inherits from a string, string dictionary. + * Use the dictionary interface to get and set values. + * Commit to the EEPROM to save changed settings. + */ +class UHD_API octoclock_eeprom_t : public uhd::dict<std::string, std::string>{ +public: + //! Make a new empty OctoClock EEPROM handler + octoclock_eeprom_t(void); + + /*! + * Make a new OctoClock EEPROM handler. + * \param transport the UDP transport to the OctoClock + */ + octoclock_eeprom_t(transport::udp_simple::sptr transport); + + /*! + * Write the contents of this object to the EEPROM. + */ + void commit() const; + +private: + transport::udp_simple::sptr xport; + void _load(); + void _store() const; + +}; + +} //namespace +} //namespace + +#endif /* INCLUDED_UHD_USRP_CLOCK_OCTOCLOCK_EEPROM_HPP */ diff --git a/host/lib/CMakeLists.txt b/host/lib/CMakeLists.txt index 4ca06af9a..eed8b642c 100644 --- a/host/lib/CMakeLists.txt +++ b/host/lib/CMakeLists.txt @@ -1,5 +1,5 @@ # -# Copyright 2010-2013 Ettus Research LLC +# Copyright 2010-2014 Ettus Research LLC # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -72,6 +72,7 @@ INCLUDE_SUBDIRECTORY(types) INCLUDE_SUBDIRECTORY(convert) INCLUDE_SUBDIRECTORY(transport) INCLUDE_SUBDIRECTORY(usrp) +INCLUDE_SUBDIRECTORY(usrp_clock) INCLUDE_SUBDIRECTORY(utils) ######################################################################## diff --git a/host/lib/device.cpp b/host/lib/device.cpp index ff5163f2d..bd7bf5637 100644 --- a/host/lib/device.cpp +++ b/host/lib/device.cpp @@ -1,5 +1,5 @@ // -// Copyright 2010-2011 Ettus Research LLC +// Copyright 2010-2011,2014 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -57,35 +57,38 @@ static size_t hash_device_addr( /*********************************************************************** * Registration **********************************************************************/ -typedef boost::tuple<device::find_t, device::make_t> dev_fcn_reg_t; +typedef boost::tuple<device::find_t, device::make_t, device::device_filter_t> dev_fcn_reg_t; // instantiate the device function registry container UHD_SINGLETON_FCN(std::vector<dev_fcn_reg_t>, get_dev_fcn_regs) void device::register_device( const find_t &find, - const make_t &make + const make_t &make, + const device_filter_t filter ){ UHD_LOGV(always) << "registering device" << std::endl; - get_dev_fcn_regs().push_back(dev_fcn_reg_t(find, make)); + get_dev_fcn_regs().push_back(dev_fcn_reg_t(find, make, filter)); } /*********************************************************************** * Discover **********************************************************************/ -device_addrs_t device::find(const device_addr_t &hint){ +device_addrs_t device::find(const device_addr_t &hint, device_filter_t filter){ boost::mutex::scoped_lock lock(_device_mutex); device_addrs_t device_addrs; BOOST_FOREACH(const dev_fcn_reg_t &fcn, get_dev_fcn_regs()){ try{ - device_addrs_t discovered_addrs = fcn.get<0>()(hint); - device_addrs.insert( - device_addrs.begin(), - discovered_addrs.begin(), - discovered_addrs.end() - ); + if(filter == ANY or fcn.get<2>() == filter){ + device_addrs_t discovered_addrs = fcn.get<0>()(hint); + device_addrs.insert( + device_addrs.begin(), + discovered_addrs.begin(), + discovered_addrs.end() + ); + } } catch(const std::exception &e){ UHD_MSG(error) << "Device discovery error: " << e.what() << std::endl; @@ -98,16 +101,18 @@ device_addrs_t device::find(const device_addr_t &hint){ /*********************************************************************** * Make **********************************************************************/ -device::sptr device::make(const device_addr_t &hint, size_t which){ +device::sptr device::make(const device_addr_t &hint, device_filter_t filter, size_t which){ boost::mutex::scoped_lock lock(_device_mutex); typedef boost::tuple<device_addr_t, make_t> dev_addr_make_t; std::vector<dev_addr_make_t> dev_addr_makers; BOOST_FOREACH(const dev_fcn_reg_t &fcn, get_dev_fcn_regs()){ - BOOST_FOREACH(device_addr_t dev_addr, fcn.get<0>()(hint)){ - //append the discovered address and its factory function - dev_addr_makers.push_back(dev_addr_make_t(dev_addr, fcn.get<1>())); + if(filter == ANY or fcn.get<2>() == filter){ + BOOST_FOREACH(device_addr_t dev_addr, fcn.get<0>()(hint)){ + //append the discovered address and its factory function + dev_addr_makers.push_back(dev_addr_make_t(dev_addr, fcn.get<1>())); + } } } @@ -159,3 +164,7 @@ device::get_tree(void) const { return _tree; } + +device::device_filter_t device::get_device_type() const { + return _type; +} diff --git a/host/lib/usrp/b100/b100_impl.cpp b/host/lib/usrp/b100/b100_impl.cpp index baf2b6ae3..26b0a5aea 100644 --- a/host/lib/usrp/b100/b100_impl.cpp +++ b/host/lib/usrp/b100/b100_impl.cpp @@ -1,5 +1,5 @@ // -// Copyright 2012-2013 Ettus Research LLC +// Copyright 2012-2014 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -137,7 +137,7 @@ static device::sptr b100_make(const device_addr_t &device_addr){ } UHD_STATIC_BLOCK(register_b100_device){ - device::register_device(&b100_find, &b100_make); + device::register_device(&b100_find, &b100_make, device::USRP); } /*********************************************************************** @@ -148,6 +148,7 @@ b100_impl::b100_impl(const device_addr_t &device_addr){ b100_impl_constructor_begin: initialization_count++; + _type = device::USRP; _tree = property_tree::make(); //extract the FPGA path for the B100 diff --git a/host/lib/usrp/b100/usb_zero_copy_wrapper.cpp b/host/lib/usrp/b100/usb_zero_copy_wrapper.cpp index 451cdae50..d646fcc94 100644 --- a/host/lib/usrp/b100/usb_zero_copy_wrapper.cpp +++ b/host/lib/usrp/b100/usb_zero_copy_wrapper.cpp @@ -55,6 +55,7 @@ public: index++; //advances the caller's buffer //hold a copy of the buffer shared pointer + UHD_ASSERT_THROW(not _mrb); _mrb = mrb; //extract this packet's memory address and length in bytes @@ -199,7 +200,7 @@ public: } size_t get_num_recv_frames(void) const{ - return _internal_zc->get_num_recv_frames(); + return (_internal_zc->get_num_recv_frames()*_internal_zc->get_recv_frame_size())/this->get_recv_frame_size(); } size_t get_recv_frame_size(void) const{ diff --git a/host/lib/usrp/b200/CMakeLists.txt b/host/lib/usrp/b200/CMakeLists.txt index 3d8aad052..a08c4bd03 100644 --- a/host/lib/usrp/b200/CMakeLists.txt +++ b/host/lib/usrp/b200/CMakeLists.txt @@ -30,5 +30,6 @@ IF(ENABLE_B200) ${CMAKE_CURRENT_SOURCE_DIR}/b200_iface.cpp ${CMAKE_CURRENT_SOURCE_DIR}/b200_io_impl.cpp ${CMAKE_CURRENT_SOURCE_DIR}/b200_uart.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/b200_cores.cpp ) ENDIF(ENABLE_B200) diff --git a/host/lib/usrp/b200/b200_cores.cpp b/host/lib/usrp/b200/b200_cores.cpp new file mode 100644 index 000000000..19e637ef4 --- /dev/null +++ b/host/lib/usrp/b200/b200_cores.cpp @@ -0,0 +1,83 @@ +// +// Copyright 2013-2014 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#include "b200_cores.hpp" +#include "b200_regs.hpp" +#include "b200_impl.hpp" + +b200_local_spi_core::b200_local_spi_core( + uhd::wb_iface::sptr iface, + perif_t default_perif) : + _spi_core(spi_core_3000::make(iface, TOREG(SR_CORE_SPI), RB32_CORE_SPI)), + _current_perif(default_perif), + _last_perif(default_perif) +{ + change_perif(default_perif); +} + +boost::uint32_t b200_local_spi_core::transact_spi( + int which_slave, + const uhd::spi_config_t &config, + boost::uint32_t data, + size_t num_bits, + bool readback) +{ + boost::mutex::scoped_lock lock(_mutex); + return _spi_core->transact_spi(which_slave, config, data, num_bits, readback); +} + +void b200_local_spi_core::change_perif(perif_t perif) +{ + boost::mutex::scoped_lock lock(_mutex); + _last_perif = _current_perif; + _current_perif = perif; + + switch (_current_perif) { + case CODEC: + _spi_core->set_divider(B200_BUS_CLOCK_RATE/AD9361_SPI_RATE); + break; + case PLL: + _spi_core->set_divider(B200_BUS_CLOCK_RATE/ADF4001_SPI_RATE); + break; + } +} + +void b200_local_spi_core::restore_perif() +{ + change_perif(_last_perif); +} + +b200_ref_pll_ctrl::b200_ref_pll_ctrl(b200_local_spi_core::sptr spi) : + uhd::usrp::adf4001_ctrl(spi, ADF4001_SLAVENO), + _spi(spi) +{ +} + +void b200_ref_pll_ctrl::set_lock_to_ext_ref(bool external) +{ + _spi->change_perif(b200_local_spi_core::PLL); + adf4001_ctrl::set_lock_to_ext_ref(external); + _spi->restore_perif(); +} + + +b200_local_spi_core::sptr b200_local_spi_core::make( + uhd::wb_iface::sptr iface, b200_local_spi_core::perif_t default_perif) +{ + return sptr(new b200_local_spi_core(iface, default_perif)); +} + diff --git a/host/lib/usrp/b200/b200_cores.hpp b/host/lib/usrp/b200/b200_cores.hpp new file mode 100644 index 000000000..8a8900412 --- /dev/null +++ b/host/lib/usrp/b200/b200_cores.hpp @@ -0,0 +1,66 @@ +// +// Copyright 2013-2014 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#ifndef INCLUDED_B200_CORES_HPP +#define INCLUDED_B200_CORES_HPP + +#include "spi_core_3000.hpp" +#include "adf4001_ctrl.hpp" +#include <boost/thread/mutex.hpp> + +class b200_local_spi_core : boost::noncopyable, public uhd::spi_iface { + +public: + typedef boost::shared_ptr<b200_local_spi_core> sptr; + + enum perif_t { + CODEC, PLL + }; + + b200_local_spi_core(uhd::wb_iface::sptr iface, perif_t default_perif); + + virtual boost::uint32_t transact_spi( + int which_slave, + const uhd::spi_config_t &config, + boost::uint32_t data, + size_t num_bits, + bool readback); + + void change_perif(perif_t perif); + void restore_perif(); + + static sptr make(uhd::wb_iface::sptr iface, perif_t default_perif = CODEC); + +private: + spi_core_3000::sptr _spi_core; + perif_t _current_perif; + perif_t _last_perif; + boost::mutex _mutex; +}; + +class b200_ref_pll_ctrl : public uhd::usrp::adf4001_ctrl { +public: + typedef boost::shared_ptr<b200_ref_pll_ctrl> sptr; + + b200_ref_pll_ctrl(b200_local_spi_core::sptr spi); + void set_lock_to_ext_ref(bool external); + +private: + b200_local_spi_core::sptr _spi; +}; + +#endif /* INCLUDED_B200_CORES_HPP */ diff --git a/host/lib/usrp/b200/b200_iface.cpp b/host/lib/usrp/b200/b200_iface.cpp index efb9b3a35..820090959 100644 --- a/host/lib/usrp/b200/b200_iface.cpp +++ b/host/lib/usrp/b200/b200_iface.cpp @@ -57,15 +57,11 @@ const static boost::uint8_t B200_VREQ_GET_FPGA_HASH = 0x1D; const static boost::uint8_t B200_VREQ_SET_FW_HASH = 0x1E; const static boost::uint8_t B200_VREQ_GET_FW_HASH = 0x1F; const static boost::uint8_t B200_VREQ_LOOP = 0x22; -const static boost::uint8_t B200_VREQ_SPI_WRITE = 0x32; -const static boost::uint8_t B200_VREQ_SPI_READ = 0x42; const static boost::uint8_t B200_VREQ_FPGA_CONFIG = 0x55; const static boost::uint8_t B200_VREQ_FPGA_RESET = 0x62; const static boost::uint8_t B200_VREQ_GPIF_RESET = 0x72; const static boost::uint8_t B200_VREQ_GET_USB = 0x80; const static boost::uint8_t B200_VREQ_GET_STATUS = 0x83; -const static boost::uint8_t B200_VREQ_AD9361_CTRL_WRITE = 0x90; -const static boost::uint8_t B200_VREQ_AD9361_CTRL_READ = 0x91; const static boost::uint8_t B200_VREQ_FX3_RESET = 0x99; const static boost::uint8_t B200_VREQ_EEPROM_WRITE = 0xBA; const static boost::uint8_t B200_VREQ_EEPROM_READ = 0xBB; @@ -270,82 +266,6 @@ public: return recv_bytes; } - void transact_spi( - unsigned char *tx_data, - size_t num_tx_bits, - unsigned char *rx_data, - size_t num_rx_bits) { - int ret = 0; - boost::uint16_t tx_length = num_tx_bits / 8; - - if(tx_data[0] & 0x80) { - ret = fx3_control_write(B200_VREQ_SPI_WRITE, 0x00, \ - 0x00, tx_data, tx_length); - } else { - ret = fx3_control_write(B200_VREQ_SPI_READ, 0x00, \ - 0x00, tx_data, tx_length); - } - - if (ret < 0) - throw uhd::io_error((boost::format("Failed to write SPI (%d: %s)") % ret % libusb_error_name(ret)).str()); - else if (ret != tx_length) - throw uhd::io_error((boost::format("Short write on write SPI (expecting: %d, returned: %d)") % tx_length % ret).str()); - - - if(num_rx_bits) { - boost::uint16_t total_length = num_rx_bits / 8; - - ret = fx3_control_read(B200_VREQ_LOOP, 0x00, \ - 0x00, rx_data, total_length); - - if (ret < 0) - throw uhd::io_error((boost::format("Failed to readback (%d: %s)") % ret % libusb_error_name(ret)).str()); - else if (ret != total_length) - throw uhd::io_error((boost::format("Short read on readback (expecting: %d, returned: %d)") % total_length % ret).str()); - } - } - - void ad9361_transact(const unsigned char in_buff[AD9361_DISPATCH_PACKET_SIZE], unsigned char out_buff[AD9361_DISPATCH_PACKET_SIZE]) { - const int bytes_to_write = AD9361_DISPATCH_PACKET_SIZE; - const int bytes_to_read = AD9361_DISPATCH_PACKET_SIZE; - const size_t read_retries = 5; - - int ret = fx3_control_write(B200_VREQ_AD9361_CTRL_WRITE, 0x00, 0x00, (unsigned char *)in_buff, bytes_to_write); - if (ret < 0) - throw uhd::io_error((boost::format("Failed to write AD9361 (%d: %s)") % ret % libusb_error_name(ret)).str()); - else if (ret != bytes_to_write) - throw uhd::io_error((boost::format("Short write on write AD9361 (expecting: %d, returned: %d)") % bytes_to_write % ret).str()); - - for (size_t i = 0; i < read_retries; i++) - { - ret = fx3_control_read(B200_VREQ_AD9361_CTRL_READ, 0x00, 0x00, out_buff, bytes_to_read, 3000); - if (ret < 0) - { - if (ret == LIBUSB_ERROR_TIMEOUT) - { - UHD_LOG << (boost::format("Failed to read AD9361 (%d: %s). Retrying (%d of %d)...") - % ret - % libusb_error_name(ret) - % (i+1) - % read_retries - ) << std::endl; - } - else - { - throw uhd::io_error((boost::format("Failed to read AD9361 (%d: %s)") - % ret - % libusb_error_name(ret) - ).str()); - } - } - - if (ret == bytes_to_read) - return; - } - - throw uhd::io_error(str(boost::format("Failed to read complete AD9361 (expecting: %d, last read: %d)") % bytes_to_read % ret)); - } - void load_firmware(const std::string filestring, UHD_UNUSED(bool force) = false) { const char *filename = filestring.c_str(); diff --git a/host/lib/usrp/b200/b200_iface.hpp b/host/lib/usrp/b200/b200_iface.hpp index 20b4a7a89..83adfdd64 100644 --- a/host/lib/usrp/b200/b200_iface.hpp +++ b/host/lib/usrp/b200/b200_iface.hpp @@ -35,8 +35,7 @@ static const std::string B200_FW_FILE_NAME = "usrp_b200_fw.hex"; static const std::string B200_FPGA_FILE_NAME = "usrp_b200_fpga.bin"; static const std::string B210_FPGA_FILE_NAME = "usrp_b210_fpga.bin"; -class UHD_API b200_iface: boost::noncopyable, public virtual uhd::i2c_iface, - public ad9361_ctrl_iface_type { +class UHD_API b200_iface: boost::noncopyable, public virtual uhd::i2c_iface { public: typedef boost::shared_ptr<b200_iface> sptr; @@ -71,10 +70,6 @@ public: //! load an FPGA image virtual boost::uint32_t load_fpga(const std::string filestring) = 0; - //! send SPI through the FX3 - virtual void transact_spi( unsigned char *tx_data, size_t num_tx_bits, \ - unsigned char *rx_data, size_t num_rx_bits) = 0; - virtual void write_eeprom(boost::uint16_t addr, boost::uint16_t offset, const uhd::byte_vector_t &bytes) = 0; virtual uhd::byte_vector_t read_eeprom(boost::uint16_t addr, boost::uint16_t offset, size_t num_bytes) = 0; diff --git a/host/lib/usrp/b200/b200_impl.cpp b/host/lib/usrp/b200/b200_impl.cpp index bf5fdd251..5c9324cb9 100644 --- a/host/lib/usrp/b200/b200_impl.cpp +++ b/host/lib/usrp/b200/b200_impl.cpp @@ -31,6 +31,7 @@ #include <boost/thread/thread.hpp> #include <boost/lexical_cast.hpp> #include <boost/functional/hash.hpp> +#include <boost/make_shared.hpp> #include <cstdio> #include <ctime> #include <cmath> @@ -45,6 +46,33 @@ static const boost::posix_time::milliseconds REENUMERATION_TIMEOUT_MS(3000); static const size_t FE1 = 1; static const size_t FE2 = 0; +class b200_ad9361_client_t : public ad9361_params { +public: + ~b200_ad9361_client_t() {} + double get_band_edge(frequency_band_t band) { + switch (band) { + case AD9361_RX_BAND0: return 2.2e9; + case AD9361_RX_BAND1: return 4.0e9; + case AD9361_TX_BAND0: return 2.5e9; + default: return 0; + } + } + clocking_mode_t get_clocking_mode() { + return AD9361_XTAL_N_CLK_PATH; + } + digital_interface_mode_t get_digital_interface_mode() { + return AD9361_DDR_FDD_LVCMOS; + } + digital_interface_delays_t get_digital_interface_timing() { + digital_interface_delays_t delays; + delays.rx_clk_delay = 0; + delays.rx_data_delay = 0xF; + delays.tx_clk_delay = 0; + delays.tx_data_delay = 0xF; + return delays; + } +}; + /*********************************************************************** * Discovery **********************************************************************/ @@ -146,7 +174,7 @@ static device::sptr b200_make(const device_addr_t &device_addr) UHD_STATIC_BLOCK(register_b200_device) { - device::register_device(&b200_find, &b200_make); + device::register_device(&b200_find, &b200_make, device::USRP); } /*********************************************************************** @@ -155,6 +183,7 @@ UHD_STATIC_BLOCK(register_b200_device) b200_impl::b200_impl(const device_addr_t &device_addr) { _tree = property_tree::make(); + _type = device::USRP; const fs_path mb_path = "/mboards/0"; //try to match the given device address with something on the USB bus @@ -338,10 +367,17 @@ b200_impl::b200_impl(const device_addr_t &device_addr) _demux = recv_packet_demuxer_3000::make(_data_transport); //////////////////////////////////////////////////////////////////// + // create time and clock control objects + //////////////////////////////////////////////////////////////////// + _spi_iface = b200_local_spi_core::make(_local_ctrl); + _adf4001_iface = boost::make_shared<b200_ref_pll_ctrl>(_spi_iface); + + //////////////////////////////////////////////////////////////////// // Init codec - turns on clocks //////////////////////////////////////////////////////////////////// UHD_MSG(status) << "Initialize CODEC control..." << std::endl; - _codec_ctrl = ad9361_ctrl::make(_iface); + ad9361_params::sptr client_settings = boost::make_shared<b200_ad9361_client_t>(); + _codec_ctrl = ad9361_ctrl::make_spi(client_settings, _spi_iface, AD9361_SLAVENO); this->reset_codec_dcm(); //////////////////////////////////////////////////////////////////// @@ -404,13 +440,6 @@ b200_impl::b200_impl(const device_addr_t &device_addr) } _codec_ctrl->data_port_loopback(false); - //////////////////////////////////////////////////////////////////// - // create time and clock control objects - //////////////////////////////////////////////////////////////////// - _spi_iface = spi_core_3000::make(_local_ctrl, TOREG(SR_CORE_SPI), RB32_CORE_SPI); - _spi_iface->set_divider(B200_BUS_CLOCK_RATE/ADF4001_SPI_RATE); - _adf4001_iface = boost::shared_ptr<adf4001_ctrl>(new adf4001_ctrl(_spi_iface, ADF4001_SLAVENO)); - //register time now and pps onto available radio cores _tree->create<time_spec_t>(mb_path / "time" / "now") .publish(boost::bind(&time_core_3000::get_time_now, _radio_perifs[0].time64)); @@ -680,7 +709,7 @@ void b200_impl::enforce_tick_rate_limits(size_t chan_count, double tick_rate, co } else { - const double max_tick_rate = ((chan_count <= 1) ? AD9361_1_CHAN_CLOCK_RATE_MAX : AD9361_2_CHAN_CLOCK_RATE_MAX); + const double max_tick_rate = ad9361_device_t::AD9361_MAX_CLOCK_RATE / ((chan_count <= 1) ? 1 : 2); if (tick_rate - max_tick_rate >= 1.0) { throw uhd::value_error(boost::str( diff --git a/host/lib/usrp/b200/b200_impl.hpp b/host/lib/usrp/b200/b200_impl.hpp index c3508c550..155ff699c 100644 --- a/host/lib/usrp/b200/b200_impl.hpp +++ b/host/lib/usrp/b200/b200_impl.hpp @@ -20,6 +20,7 @@ #include "b200_iface.hpp" #include "b200_uart.hpp" +#include "b200_cores.hpp" #include "ad9361_ctrl.hpp" #include "adf4001_ctrl.hpp" #include "rx_vita_core_3000.hpp" @@ -44,9 +45,9 @@ #include <uhd/transport/bounded_buffer.hpp> #include <boost/weak_ptr.hpp> #include "recv_packet_demuxer_3000.hpp" -static const boost::uint8_t B200_FW_COMPAT_NUM_MAJOR = 0x04; +static const boost::uint8_t B200_FW_COMPAT_NUM_MAJOR = 0x06; static const boost::uint8_t B200_FW_COMPAT_NUM_MINOR = 0x00; -static const boost::uint16_t B200_FPGA_COMPAT_NUM = 0x03; +static const boost::uint16_t B200_FPGA_COMPAT_NUM = 0x04; static const double B200_BUS_CLOCK_RATE = 100e6; static const double B200_DEFAULT_TICK_RATE = 32e6; static const boost::uint32_t B200_GPSDO_ST_NONE = 0x83; @@ -99,8 +100,8 @@ private: //controllers b200_iface::sptr _iface; radio_ctrl_core_3000::sptr _local_ctrl; - ad9361_ctrl::sptr _codec_ctrl; - spi_core_3000::sptr _spi_iface; + uhd::usrp::ad9361_ctrl::sptr _codec_ctrl; + b200_local_spi_core::sptr _spi_iface; boost::shared_ptr<uhd::usrp::adf4001_ctrl> _adf4001_iface; uhd::gps_ctrl::sptr _gps; diff --git a/host/lib/usrp/b200/b200_regs.hpp b/host/lib/usrp/b200/b200_regs.hpp index c64066b27..dc8a6b0dc 100644 --- a/host/lib/usrp/b200/b200_regs.hpp +++ b/host/lib/usrp/b200/b200_regs.hpp @@ -52,7 +52,9 @@ localparam RB64_TIME_PPS = 16; localparam RB64_CODEC_READBACK = 24; //pll constants +static const int AD9361_SLAVENO = (1 << 0); static const int ADF4001_SLAVENO = (1 << 1); +static const double AD9361_SPI_RATE = 1e6; static const double ADF4001_SPI_RATE = 10e3; //slow for large time constant on spi lines /* ATR Control Bits */ diff --git a/host/lib/usrp/common/CMakeLists.txt b/host/lib/usrp/common/CMakeLists.txt index b99464873..129cc569b 100644 --- a/host/lib/usrp/common/CMakeLists.txt +++ b/host/lib/usrp/common/CMakeLists.txt @@ -27,11 +27,13 @@ IF(ENABLE_USB) ENDIF(ENABLE_USB) INCLUDE_DIRECTORIES(${CMAKE_CURRENT_SOURCE_DIR}) +INCLUDE_DIRECTORIES("${CMAKE_CURRENT_SOURCE_DIR}/ad9361_driver") LIBUHD_APPEND_SOURCES( ${CMAKE_CURRENT_SOURCE_DIR}/adf4001_ctrl.cpp ${CMAKE_CURRENT_SOURCE_DIR}/adf435x_common.cpp ${CMAKE_CURRENT_SOURCE_DIR}/ad9361_ctrl.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/ad9361_driver/ad9361_device.cpp ${CMAKE_CURRENT_SOURCE_DIR}/apply_corrections.cpp ${CMAKE_CURRENT_SOURCE_DIR}/validate_subdev_spec.cpp ${CMAKE_CURRENT_SOURCE_DIR}/recv_packet_demuxer.cpp diff --git a/host/lib/usrp/common/ad9361_ctrl.cpp b/host/lib/usrp/common/ad9361_ctrl.cpp index 10496f2a9..dea18ff06 100644 --- a/host/lib/usrp/common/ad9361_ctrl.cpp +++ b/host/lib/usrp/common/ad9361_ctrl.cpp @@ -1,70 +1,105 @@ // -// Copyright 2012-2013 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see <http://www.gnu.org/licenses/>. +// Copyright 2014 Ettus Research LLC // #include "ad9361_ctrl.hpp" -#include "ad9361_transaction.h" #include <uhd/exception.hpp> #include <uhd/types/ranges.hpp> #include <uhd/utils/msg.hpp> -#include <boost/thread/mutex.hpp> -#include <boost/format.hpp> +#include <uhd/types/serial.hpp> #include <cstring> - -//! compat strnlen for platforms that dont have it -static size_t my_strnlen(const char *str, size_t max) -{ - const char *end = (const char *)std::memchr((const void *)str, 0, max); - if (end == NULL) return max; - return (size_t)(end - str); -} +#include <boost/format.hpp> +#include <boost/utility.hpp> +#include <boost/function.hpp> +#include <boost/make_shared.hpp> +#include <boost/thread.hpp> using namespace uhd; +using namespace uhd::usrp; + +/*********************************************************************** + * AD9361 IO Implementation Classes + **********************************************************************/ -struct ad9361_ctrl_impl : public ad9361_ctrl +class ad9361_io_spi : public ad9361_io { - ad9361_ctrl_impl(ad9361_ctrl_iface_sptr iface): - _iface(iface), _seq(0) +public: + ad9361_io_spi(uhd::spi_iface::sptr spi_iface, boost::uint32_t slave_num) : + _spi_iface(spi_iface), _slave_num(slave_num) { } + + virtual ~ad9361_io_spi() { } + + virtual boost::uint8_t peek8(boost::uint32_t reg) { - ad9361_transaction_t request; + boost::lock_guard<boost::mutex> lock(_mutex); + + uhd::spi_config_t config; + config.mosi_edge = uhd::spi_config_t::EDGE_FALL; + config.miso_edge = uhd::spi_config_t::EDGE_FALL; //TODO (Ashish): FPGA SPI workaround. This should be EDGE_RISE - request.action = AD9361_ACTION_ECHO; - this->do_transaction(request); + boost::uint32_t rd_word = AD9361_SPI_READ_CMD | + ((boost::uint32_t(reg) << AD9361_SPI_ADDR_SHIFT) & AD9361_SPI_ADDR_MASK); - request.action = AD9361_ACTION_INIT; - this->do_transaction(request); + boost::uint32_t val = (_spi_iface->read_spi(_slave_num, config, rd_word, AD9361_SPI_NUM_BITS)); + val &= 0xFF; + + return static_cast<boost::uint8_t>(val); } - double set_gain(const std::string &which, const double value) + virtual void poke8(boost::uint32_t reg, boost::uint8_t val) + { + boost::lock_guard<boost::mutex> lock(_mutex); + + uhd::spi_config_t config; + config.mosi_edge = uhd::spi_config_t::EDGE_FALL; + config.miso_edge = uhd::spi_config_t::EDGE_FALL; //TODO (Ashish): FPGA SPI workaround. This should be EDGE_RISE + + boost::uint32_t wr_word = AD9361_SPI_WRITE_CMD | + ((boost::uint32_t(reg) << AD9361_SPI_ADDR_SHIFT) & AD9361_SPI_ADDR_MASK) | + ((boost::uint32_t(val) << AD9361_SPI_DATA_SHIFT) & AD9361_SPI_DATA_MASK); + _spi_iface->write_spi(_slave_num, config, wr_word, AD9361_SPI_NUM_BITS); + } + +private: + uhd::spi_iface::sptr _spi_iface; + boost::uint32_t _slave_num; + boost::mutex _mutex; + + static const boost::uint32_t AD9361_SPI_WRITE_CMD = 0x00800000; + static const boost::uint32_t AD9361_SPI_READ_CMD = 0x00000000; + static const boost::uint32_t AD9361_SPI_ADDR_MASK = 0x003FFF00; + static const boost::uint32_t AD9361_SPI_ADDR_SHIFT = 8; + static const boost::uint32_t AD9361_SPI_DATA_MASK = 0x000000FF; + static const boost::uint32_t AD9361_SPI_DATA_SHIFT = 0; + static const boost::uint32_t AD9361_SPI_NUM_BITS = 24; +}; + +/*********************************************************************** + * AD9361 Control API Class + **********************************************************************/ +class ad9361_ctrl_impl : public ad9361_ctrl +{ +public: + ad9361_ctrl_impl(ad9361_params::sptr client_settings, ad9361_io::sptr io_iface): + _device(client_settings, io_iface) { - ad9361_transaction_t request; + _device.initialize(); + } - if (which == "RX1") request.action = AD9361_ACTION_SET_RX1_GAIN; - if (which == "RX2") request.action = AD9361_ACTION_SET_RX2_GAIN; - if (which == "TX1") request.action = AD9361_ACTION_SET_TX1_GAIN; - if (which == "TX2") request.action = AD9361_ACTION_SET_TX2_GAIN; + double set_gain(const std::string &which, const double value) + { + boost::lock_guard<boost::mutex> lock(_mutex); - ad9361_double_pack(value, request.value.gain); - const ad9361_transaction_t reply = this->do_transaction(request); - return ad9361_double_unpack(reply.value.gain); + ad9361_device_t::direction_t direction = _get_direction_from_antenna(which); + ad9361_device_t::chain_t chain =_get_chain_from_antenna(which); + return _device.set_gain(direction, chain, value); } //! set a new clock rate, return the exact value double set_clock_rate(const double rate) { + boost::lock_guard<boost::mutex> lock(_mutex); + //warning for known trouble rates if (rate > 56e6) UHD_MSG(warning) << boost::format( "The requested clock rate %f MHz may cause slow configuration.\n" @@ -75,99 +110,76 @@ struct ad9361_ctrl_impl : public ad9361_ctrl const meta_range_t clock_rate_range = ad9361_ctrl::get_clock_rate_range(); const double clipped_rate = clock_rate_range.clip(rate); - ad9361_transaction_t request; - request.action = AD9361_ACTION_SET_CLOCK_RATE; - ad9361_double_pack(clipped_rate, request.value.rate); - const ad9361_transaction_t reply = this->do_transaction(request); - return ad9361_double_unpack(reply.value.rate); + return _device.set_clock_rate(clipped_rate); } //! set which RX and TX chains/antennas are active void set_active_chains(bool tx1, bool tx2, bool rx1, bool rx2) { - boost::uint32_t mask = 0; - if (tx1) mask |= (1 << 0); - if (tx2) mask |= (1 << 1); - if (rx1) mask |= (1 << 2); - if (rx2) mask |= (1 << 3); - - ad9361_transaction_t request; - request.action = AD9361_ACTION_SET_ACTIVE_CHAINS; - request.value.enable_mask = mask; - this->do_transaction(request); + boost::lock_guard<boost::mutex> lock(_mutex); + + _device.set_active_chains(tx1, tx2, rx1, rx2); } //! tune the given frontend, return the exact value double tune(const std::string &which, const double freq) { + boost::lock_guard<boost::mutex> lock(_mutex); + //clip to known bounds const meta_range_t freq_range = ad9361_ctrl::get_rf_freq_range(); const double clipped_freq = freq_range.clip(freq); - - ad9361_transaction_t request; - - if (which[0] == 'R') request.action = AD9361_ACTION_SET_RX_FREQ; - if (which[0] == 'T') request.action = AD9361_ACTION_SET_TX_FREQ; - const double value = ad9361_ctrl::get_rf_freq_range().clip(clipped_freq); - ad9361_double_pack(value, request.value.freq); - const ad9361_transaction_t reply = this->do_transaction(request); - return ad9361_double_unpack(reply.value.freq); + + ad9361_device_t::direction_t direction = _get_direction_from_antenna(which); + return _device.tune(direction, value); } //! turn on/off Catalina's data port loopback void data_port_loopback(const bool on) { - ad9361_transaction_t request; - request.action = AD9361_ACTION_SET_CODEC_LOOP; - request.value.codec_loop = on? 1 : 0; - this->do_transaction(request); + boost::lock_guard<boost::mutex> lock(_mutex); + + _device.data_port_loopback(on); } - ad9361_transaction_t do_transaction(const ad9361_transaction_t &request) +private: + static ad9361_device_t::direction_t _get_direction_from_antenna(const std::string& antenna) { - boost::mutex::scoped_lock lock(_mutex); - - //declare in/out buffers - unsigned char in_buff[64] = {}; - unsigned char out_buff[64] = {}; - - //copy the input transaction - std::memcpy(in_buff, &request, sizeof(request)); - - //fill in other goodies - ad9361_transaction_t *in = (ad9361_transaction_t *)in_buff; - in->version = AD9361_TRANSACTION_VERSION; - in->sequence = _seq++; - - //transact - _iface->ad9361_transact(in_buff, out_buff); - ad9361_transaction_t *out = (ad9361_transaction_t *)out_buff; - - //sanity checks - UHD_ASSERT_THROW(out->version == in->version); - UHD_ASSERT_THROW(out->sequence == in->sequence); - - //handle errors - const size_t len = my_strnlen(out->error_msg, AD9361_TRANSACTION_MAX_ERROR_MSG); - const std::string error_msg(out->error_msg, len); - if (not error_msg.empty()) throw uhd::runtime_error("[ad9361_ctrl::do_transaction] firmware reported: \"" + error_msg + "\""); - - //return result done! - return *out; + std::string sub = antenna.substr(0, 2); + if (sub == "RX") { + return ad9361_device_t::RX; + } else if (sub == "TX") { + return ad9361_device_t::TX; + } else { + throw uhd::runtime_error("ad9361_ctrl got an invalid channel string."); + } + return ad9361_device_t::RX; } - ad9361_ctrl_iface_sptr _iface; - size_t _seq; - boost::mutex _mutex; + static ad9361_device_t::chain_t _get_chain_from_antenna(const std::string& antenna) + { + std::string sub = antenna.substr(2, 1); + if (sub == "1") { + return ad9361_device_t::CHAIN_1; + } else if (sub == "2") { + return ad9361_device_t::CHAIN_2; + } else { + throw uhd::runtime_error("ad9361_ctrl::set_gain got an invalid channel string."); + } + return ad9361_device_t::CHAIN_1; + } + ad9361_device_t _device; + boost::mutex _mutex; }; - -/*********************************************************************** - * Make an instance of the implementation - **********************************************************************/ -ad9361_ctrl::sptr ad9361_ctrl::make(ad9361_ctrl_iface_sptr iface) +//---------------------------------------------------------------------- +// Make an instance of the AD9361 Control interface +//---------------------------------------------------------------------- +ad9361_ctrl::sptr ad9361_ctrl::make_spi( + ad9361_params::sptr client_settings, uhd::spi_iface::sptr spi_iface, boost::uint32_t slave_num) { - return sptr(new ad9361_ctrl_impl(iface)); + boost::shared_ptr<ad9361_io_spi> spi_io_iface = boost::make_shared<ad9361_io_spi>(spi_iface, slave_num); + return sptr(new ad9361_ctrl_impl(client_settings, spi_io_iface)); } diff --git a/host/lib/usrp/common/ad9361_ctrl.hpp b/host/lib/usrp/common/ad9361_ctrl.hpp index 098b5dae8..f1659f30e 100644 --- a/host/lib/usrp/common/ad9361_ctrl.hpp +++ b/host/lib/usrp/common/ad9361_ctrl.hpp @@ -1,79 +1,30 @@ // -// Copyright 2012-2013 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see <http://www.gnu.org/licenses/>. +// Copyright 2014 Ettus Research LLC // #ifndef INCLUDED_AD9361_CTRL_HPP #define INCLUDED_AD9361_CTRL_HPP #include <uhd/transport/zero_copy.hpp> -#include <uhd/types/serial.hpp> #include <uhd/types/ranges.hpp> +#include <uhd/types/serial.hpp> #include <boost/shared_ptr.hpp> -#include <boost/utility.hpp> -#include <boost/function.hpp> -#include <vector> +#include <ad9361_device.h> #include <string> -#include "ad9361_transaction.h" - - -static const double AD9361_CLOCK_RATE_MAX = 61.44e6; -static const double AD9361_1_CHAN_CLOCK_RATE_MAX = AD9361_CLOCK_RATE_MAX; -static const double AD9361_2_CHAN_CLOCK_RATE_MAX = (AD9361_1_CHAN_CLOCK_RATE_MAX / 2); - - -struct ad9361_ctrl_iface_type -{ - virtual void ad9361_transact(const unsigned char in_buff[AD9361_DISPATCH_PACKET_SIZE], unsigned char out_buff[AD9361_DISPATCH_PACKET_SIZE]) = 0; -}; -typedef boost::shared_ptr<ad9361_ctrl_iface_type> ad9361_ctrl_iface_sptr; - +namespace uhd { namespace usrp { -struct ad9361_ctrl_over_zc : ad9361_ctrl_iface_type +/*********************************************************************** + * AD9361 Control Interface + **********************************************************************/ +class ad9361_ctrl : public boost::noncopyable { - ad9361_ctrl_over_zc(uhd::transport::zero_copy_if::sptr xport) - { - _xport = xport; - } - - void ad9361_transact(const unsigned char in_buff[AD9361_DISPATCH_PACKET_SIZE], unsigned char out_buff[AD9361_DISPATCH_PACKET_SIZE]) - { - { - uhd::transport::managed_send_buffer::sptr buff = _xport->get_send_buff(10.0); - if (not buff or buff->size() < AD9361_DISPATCH_PACKET_SIZE) throw std::runtime_error("ad9361_ctrl_over_zc send timeout"); - std::memcpy(buff->cast<void *>(), in_buff, AD9361_DISPATCH_PACKET_SIZE); - buff->commit(AD9361_DISPATCH_PACKET_SIZE); - } - { - uhd::transport::managed_recv_buffer::sptr buff = _xport->get_recv_buff(10.0); - if (not buff or buff->size() < AD9361_DISPATCH_PACKET_SIZE) throw std::runtime_error("ad9361_ctrl_over_zc recv timeout"); - std::memcpy(out_buff, buff->cast<const void *>(), AD9361_DISPATCH_PACKET_SIZE); - } - } - - uhd::transport::zero_copy_if::sptr _xport; -}; - - -class ad9361_ctrl : boost::noncopyable{ public: typedef boost::shared_ptr<ad9361_ctrl> sptr; //! make a new codec control object - static sptr make(ad9361_ctrl_iface_sptr iface); + static sptr make_spi( + ad9361_params::sptr client_settings, uhd::spi_iface::sptr spi_iface, boost::uint32_t slave_num); //! Get a list of gain names for RX or TX static std::vector<std::string> get_gain_names(const std::string &/*which*/) @@ -107,7 +58,7 @@ public: static uhd::meta_range_t get_clock_rate_range(void) { //return uhd::meta_range_t(220e3, 61.44e6); - return uhd::meta_range_t(5e6, AD9361_CLOCK_RATE_MAX); //5 MHz DCM low end + return uhd::meta_range_t(5e6, ad9361_device_t::AD9361_MAX_CLOCK_RATE); //5 MHz DCM low end } //! set the filter bandwidth for the frontend @@ -132,4 +83,6 @@ public: virtual void data_port_loopback(const bool on) = 0; }; +}} + #endif /* INCLUDED_AD9361_CTRL_HPP */ diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_client.h b/host/lib/usrp/common/ad9361_driver/ad9361_client.h new file mode 100644 index 000000000..5e848d4c0 --- /dev/null +++ b/host/lib/usrp/common/ad9361_driver/ad9361_client.h @@ -0,0 +1,73 @@ +// +// Copyright 2014 Ettus Research LLC +// + +#ifndef INCLUDED_AD9361_CLIENT_H +#define INCLUDED_AD9361_CLIENT_H + +#include <boost/shared_ptr.hpp> + +namespace uhd { namespace usrp { + +/*! + * Frequency band settings + */ +typedef enum { + AD9361_RX_BAND0, + AD9361_RX_BAND1, + AD9361_TX_BAND0 +} frequency_band_t; + +/*! + * Clocking mode + */ +typedef enum { + AD9361_XTAL_P_CLK_PATH, + AD9361_XTAL_N_CLK_PATH +} clocking_mode_t; + +/*! + * Digital interface specific + */ +typedef enum { + AD9361_DDR_FDD_LVCMOS, + AD9361_DDR_FDD_LVDS +} digital_interface_mode_t; + +/*! + * Interface timing + */ +typedef struct { + boost::uint8_t rx_clk_delay; + boost::uint8_t rx_data_delay; + boost::uint8_t tx_clk_delay; + boost::uint8_t tx_data_delay; +} digital_interface_delays_t; + +class ad9361_params { +public: + typedef boost::shared_ptr<ad9361_params> sptr; + + virtual ~ad9361_params() {} + + virtual digital_interface_delays_t get_digital_interface_timing() = 0; + virtual digital_interface_mode_t get_digital_interface_mode() = 0; + virtual clocking_mode_t get_clocking_mode() = 0; + virtual double get_band_edge(frequency_band_t band) = 0; +}; + +class ad9361_io +{ +public: + typedef boost::shared_ptr<ad9361_io> sptr; + + virtual ~ad9361_io() {} + + virtual boost::uint8_t peek8(boost::uint32_t reg) = 0; + virtual void poke8(boost::uint32_t reg, boost::uint8_t val) = 0; +}; + + +}} + +#endif /* INCLUDED_AD9361_CLIENT_H */ diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp new file mode 100644 index 000000000..ade206d36 --- /dev/null +++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp @@ -0,0 +1,1914 @@ +// +// Copyright 2014 Ettus Research LLC +// + +#include "ad9361_filter_taps.h" +#include "ad9361_gain_tables.h" +#include "ad9361_synth_lut.h" +#include "ad9361_client.h" +#include "ad9361_device.h" +#define _USE_MATH_DEFINES +#include <cmath> +#include <uhd/exception.hpp> +#include <uhd/utils/log.hpp> +#include <boost/cstdint.hpp> +#include <boost/date_time/posix_time/posix_time.hpp> +#include <boost/thread/thread.hpp> +#include <boost/scoped_array.hpp> +#include <boost/format.hpp> +#include <boost/math/special_functions.hpp> + +//////////////////////////////////////////////////////////// +// the following macros evaluate to a compile time constant +// macros By Tom Torfs - donated to the public domain + +/* turn a numeric literal into a hex constant +(avoids problems with leading zeroes) +8-bit constants max value 0x11111111, always fits in unsigned long +*/ +#define HEX__(n) 0x##n##LU + +/* 8-bit conversion function */ +#define B8__(x) ((x&0x0000000FLU)?1:0) \ ++((x&0x000000F0LU)?2:0) \ ++((x&0x00000F00LU)?4:0) \ ++((x&0x0000F000LU)?8:0) \ ++((x&0x000F0000LU)?16:0) \ ++((x&0x00F00000LU)?32:0) \ ++((x&0x0F000000LU)?64:0) \ ++((x&0xF0000000LU)?128:0) + +/* for upto 8-bit binary constants */ +#define B8(d) ((unsigned char)B8__(HEX__(d))) +//////////////////////////////////////////////////////////// + + +namespace uhd { namespace usrp { + +/* This is a simple comparison for very large double-precision floating + * point numbers. It is used to prevent re-tunes for frequencies that are + * the same but not 'exactly' because of data precision issues. */ +// TODO: see if we can avoid the need for this function +int freq_is_nearly_equal(double a, double b) { + return std::max(a,b) - std::min(a,b) < 1; +} + +/*********************************************************************** + * Filter functions + **********************************************************************/ + +/* This function takes in the calculated maximum number of FIR taps, and + * returns a number of taps that makes AD9361 happy. */ +int get_num_taps(int max_num_taps) { + + int num_taps = 0; + int num_taps_list[] = {16, 32, 48, 64, 80, 96, 112, 128}; + int i; + for(i = 1; i < 8; i++) { + if(max_num_taps >= num_taps_list[i]) { + continue; + } else { + num_taps = num_taps_list[i - 1]; + break; + } + } if(num_taps == 0) { num_taps = 128; } + + return num_taps; +} + +const double ad9361_device_t::AD9361_MAX_GAIN = 89.75; +const double ad9361_device_t::AD9361_MAX_CLOCK_RATE = 61.44e6; + + +/* Program either the RX or TX FIR filter. + * + * The process is the same for both filters, but the function must be told + * how many taps are in the filter, and given a vector of the taps + * themselves. */ + +void ad9361_device_t::_program_fir_filter(direction_t direction, int num_taps, boost::uint16_t *coeffs) +{ + boost::uint16_t base; + + /* RX and TX filters use largely identical sets of programming registers. + Select the appropriate bank of registers here. */ + if (direction == RX) { + base = 0x0f0; + } else { + base = 0x060; + } + + /* Encode number of filter taps for programming register */ + boost::uint8_t reg_numtaps = (((num_taps / 16) - 1) & 0x07) << 5; + + /* Turn on the filter clock. */ + _io_iface->poke8(base + 5, reg_numtaps | 0x1a); + boost::this_thread::sleep(boost::posix_time::milliseconds(1)); + + /* Zero the unused taps just in case they have stale data */ + int addr; + for (addr = num_taps; addr < 128; addr++) { + _io_iface->poke8(base + 0, addr); + _io_iface->poke8(base + 1, 0x0); + _io_iface->poke8(base + 2, 0x0); + _io_iface->poke8(base + 5, reg_numtaps | 0x1e); + _io_iface->poke8(base + 4, 0x00); + _io_iface->poke8(base + 4, 0x00); + } + + /* Iterate through indirect programming of filter coeffs using ADI recomended procedure */ + for (addr = 0; addr < num_taps; addr++) { + _io_iface->poke8(base + 0, addr); + _io_iface->poke8(base + 1, (coeffs[addr]) & 0xff); + _io_iface->poke8(base + 2, (coeffs[addr] >> 8) & 0xff); + _io_iface->poke8(base + 5, reg_numtaps | 0x1e); + _io_iface->poke8(base + 4, 0x00); + _io_iface->poke8(base + 4, 0x00); + } + + /* UG-671 states (page 25) (paraphrased and clarified): + " After the table has been programmed, write to register BASE+5 with the write bit D2 cleared and D1 high. + Then, write to register BASE+5 again with D1 clear, thus ensuring that the write bit resets internally + before the clock stops. Wait 4 sample clock periods after setting D2 high while that data writes into the table" + */ + + _io_iface->poke8(base + 5, reg_numtaps | 0x1A); + if (direction == RX) { + _io_iface->poke8(base + 5, reg_numtaps | 0x18); + _io_iface->poke8(base + 6, 0x02); /* Also turn on -6dB Rx gain here, to stop filter overfow.*/ + } else { + _io_iface->poke8(base + 5, reg_numtaps | 0x19); /* Also turn on -6dB Tx gain here, to stop filter overfow.*/ + } +} + + +/* Program the RX FIR Filter. */ +void ad9361_device_t::_setup_rx_fir(size_t num_taps) +{ + boost::scoped_array<boost::uint16_t> coeffs(new boost::uint16_t[num_taps]); + for (size_t i = 0; i < num_taps; i++) { + switch (num_taps) { + case 128: + coeffs[i] = boost::uint16_t(hb127_coeffs[i]); + break; + case 96: + coeffs[i] = boost::uint16_t(hb95_coeffs[i]); + break; + case 64: + coeffs[i] = boost::uint16_t(hb63_coeffs[i]); + break; + case 48: + coeffs[i] = boost::uint16_t(hb47_coeffs[i]); + break; + default: + throw uhd::runtime_error("[ad9361_device_t] Unsupported number of Rx FIR taps."); + } + } + + _program_fir_filter(RX, num_taps, coeffs.get()); +} + +/* Program the TX FIR Filter. */ +void ad9361_device_t::_setup_tx_fir(size_t num_taps) +{ + boost::scoped_array<boost::uint16_t> coeffs(new boost::uint16_t[num_taps]); + for (size_t i = 0; i < num_taps; i++) { + switch (num_taps) { + case 128: + coeffs[i] = boost::uint16_t(hb127_coeffs[i]); + break; + case 96: + coeffs[i] = boost::uint16_t(hb95_coeffs[i]); + break; + case 64: + coeffs[i] = boost::uint16_t(hb63_coeffs[i]); + break; + case 48: + coeffs[i] = boost::uint16_t(hb47_coeffs[i]); + break; + default: + throw uhd::runtime_error("[ad9361_device_t] Unsupported number of Tx FIR taps."); + } + } + + _program_fir_filter(TX, num_taps, coeffs.get()); +} + +/*********************************************************************** + * Calibration functions + ***********************************************************************/ + +/* Calibrate and lock the BBPLL. + * + * This function should be called anytime the BBPLL is tuned. */ +void ad9361_device_t::_calibrate_lock_bbpll() +{ + _io_iface->poke8(0x03F, 0x05); // Start the BBPLL calibration + _io_iface->poke8(0x03F, 0x01); // Clear the 'start' bit + + /* Increase BBPLL KV and phase margin. */ + _io_iface->poke8(0x04c, 0x86); + _io_iface->poke8(0x04d, 0x01); + _io_iface->poke8(0x04d, 0x05); + + /* Wait for BBPLL lock. */ + size_t count = 0; + while (!(_io_iface->peek8(0x05e) & 0x80)) { + if (count > 1000) { + throw uhd::runtime_error("[ad9361_device_t] BBPLL not locked"); + break; + } + count++; + boost::this_thread::sleep(boost::posix_time::milliseconds(2)); + } +} + +/* Calibrate the synthesizer charge pumps. + * + * Technically, this calibration only needs to be done once, at device + * initialization. */ +void ad9361_device_t::_calibrate_synth_charge_pumps() +{ + /* If this function ever gets called, and the ENSM isn't already in the + * ALERT state, then something has gone horribly wrong. */ + if ((_io_iface->peek8(0x017) & 0x0F) != 5) { + throw uhd::runtime_error("[ad9361_device_t] AD9361 not in ALERT during cal"); + } + + /* Calibrate the RX synthesizer charge pump. */ + size_t count = 0; + _io_iface->poke8(0x23d, 0x04); + while (!(_io_iface->peek8(0x244) & 0x80)) { + if (count > 5) { + throw uhd::runtime_error("[ad9361_device_t] RX charge pump cal failure"); + break; + } + count++; + boost::this_thread::sleep(boost::posix_time::milliseconds(1)); + } + _io_iface->poke8(0x23d, 0x00); + + /* Calibrate the TX synthesizer charge pump. */ + count = 0; + _io_iface->poke8(0x27d, 0x04); + while (!(_io_iface->peek8(0x284) & 0x80)) { + if (count > 5) { + throw uhd::runtime_error("[ad9361_device_t] TX charge pump cal failure"); + break; + } + count++; + boost::this_thread::sleep(boost::posix_time::milliseconds(1)); + } + _io_iface->poke8(0x27d, 0x00); +} + +/* Calibrate the analog BB RX filter. + * + * Note that the filter calibration depends heavily on the baseband + * bandwidth, so this must be re-done after any change to the RX sample + * rate. */ +double ad9361_device_t::_calibrate_baseband_rx_analog_filter() +{ + /* For filter tuning, baseband BW is half the complex BW, and must be + * between 28e6 and 0.2e6. */ + double bbbw = _baseband_bw / 2.0; + if (bbbw > 28e6) { + bbbw = 28e6; + } else if (bbbw < 0.20e6) { + bbbw = 0.20e6; + } + + double rxtune_clk = ((1.4 * bbbw * 2 * M_PI) / M_LN2); + _rx_bbf_tunediv = std::min<boost::uint16_t>(511, boost::uint16_t(std::ceil(_bbpll_freq / rxtune_clk))); + _regs.bbftune_config = (_regs.bbftune_config & 0xFE) + | ((_rx_bbf_tunediv >> 8) & 0x0001); + + double bbbw_mhz = bbbw / 1e6; + double temp = ((bbbw_mhz - std::floor(bbbw_mhz)) * 1000) / 7.8125; + boost::uint8_t bbbw_khz = std::min<boost::uint8_t>(127, boost::uint8_t(std::floor(temp + 0.5))); + + /* Set corner frequencies and dividers. */ + _io_iface->poke8(0x1fb, (boost::uint8_t) (bbbw_mhz)); + _io_iface->poke8(0x1fc, bbbw_khz); + _io_iface->poke8(0x1f8, (_rx_bbf_tunediv & 0x00FF)); + _io_iface->poke8(0x1f9, _regs.bbftune_config); + + /* RX Mix Voltage settings - only change with apps engineer help. */ + _io_iface->poke8(0x1d5, 0x3f); + _io_iface->poke8(0x1c0, 0x03); + + /* Enable RX1 & RX2 filter tuners. */ + _io_iface->poke8(0x1e2, 0x02); + _io_iface->poke8(0x1e3, 0x02); + + /* Run the calibration! */ + size_t count = 0; + _io_iface->poke8(0x016, 0x80); + while (_io_iface->peek8(0x016) & 0x80) { + if (count > 100) { + throw uhd::runtime_error("[ad9361_device_t] RX baseband filter cal FAILURE"); + break; + } + count++; + boost::this_thread::sleep(boost::posix_time::milliseconds(1)); + } + + /* Disable RX1 & RX2 filter tuners. */ + _io_iface->poke8(0x1e2, 0x03); + _io_iface->poke8(0x1e3, 0x03); + + return bbbw; +} + +/* Calibrate the analog BB TX filter. + * + * Note that the filter calibration depends heavily on the baseband + * bandwidth, so this must be re-done after any change to the TX sample + * rate. */ +double ad9361_device_t::_calibrate_baseband_tx_analog_filter() +{ + /* For filter tuning, baseband BW is half the complex BW, and must be + * between 28e6 and 0.2e6. */ + double bbbw = _baseband_bw / 2.0; + if (bbbw > 20e6) { + bbbw = 20e6; + } else if (bbbw < 0.625e6) { + bbbw = 0.625e6; + } + + double txtune_clk = ((1.6 * bbbw * 2 * M_PI) / M_LN2); + boost::uint16_t txbbfdiv = std::min<boost::uint16_t>(511, boost::uint16_t(std::ceil(_bbpll_freq / txtune_clk))); + _regs.bbftune_mode = (_regs.bbftune_mode & 0xFE) + | ((txbbfdiv >> 8) & 0x0001); + + /* Program the divider values. */ + _io_iface->poke8(0x0d6, (txbbfdiv & 0x00FF)); + _io_iface->poke8(0x0d7, _regs.bbftune_mode); + + /* Enable the filter tuner. */ + _io_iface->poke8(0x0ca, 0x22); + + /* Calibrate! */ + size_t count = 0; + _io_iface->poke8(0x016, 0x40); + while (_io_iface->peek8(0x016) & 0x40) { + if (count > 100) { + throw uhd::runtime_error("[ad9361_device_t] TX baseband filter cal FAILURE"); + break; + } + + count++; + boost::this_thread::sleep(boost::posix_time::milliseconds(1)); + } + + /* Disable the filter tuner. */ + _io_iface->poke8(0x0ca, 0x26); + + return bbbw; +} + +/* Calibrate the secondary TX filter. + * + * This filter also depends on the TX sample rate, so if a rate change is + * made, the previous calibration will no longer be valid. */ +void ad9361_device_t::_calibrate_secondary_tx_filter() +{ + /* For filter tuning, baseband BW is half the complex BW, and must be + * between 20e6 and 0.53e6. */ + double bbbw = _baseband_bw / 2.0; + if (bbbw > 20e6) { + bbbw = 20e6; + } else if (bbbw < 0.53e6) { + bbbw = 0.53e6; + } + + double bbbw_mhz = bbbw / 1e6; + + /* Start with a resistor value of 100 Ohms. */ + int res = 100; + + /* Calculate target corner frequency. */ + double corner_freq = 5 * bbbw_mhz * 2 * M_PI; + + /* Iterate through RC values to determine correct combination. */ + int cap = 0; + int i; + for (i = 0; i <= 3; i++) { + cap = static_cast<int>(std::floor(0.5 + ((1 / ((corner_freq * res) * 1e6)) * 1e12))) + - 12; + + if (cap <= 63) { + break; + } + + res = res * 2; + } + if (cap > 63) { + cap = 63; + } + + boost::uint8_t reg0d0, reg0d1, reg0d2; + + /* Translate baseband bandwidths to register settings. */ + if ((bbbw_mhz * 2) <= 9) { + reg0d0 = 0x59; + } else if (((bbbw_mhz * 2) > 9) && ((bbbw_mhz * 2) <= 24)) { + reg0d0 = 0x56; + } else if ((bbbw_mhz * 2) > 24) { + reg0d0 = 0x57; + } else { + throw uhd::runtime_error("[ad9361_device_t] Cal2ndTxFil: INVALID_CODE_PATH bad bbbw_mhz"); + reg0d0 = 0x00; + } + + /* Translate resistor values to register settings. */ + if (res == 100) { + reg0d1 = 0x0c; + } else if (res == 200) { + reg0d1 = 0x04; + } else if (res == 400) { + reg0d1 = 0x03; + } else if (res == 800) { + reg0d1 = 0x01; + } else { + reg0d1 = 0x0c; + } + + reg0d2 = cap; + + /* Program the above-calculated values. Sweet. */ + _io_iface->poke8(0x0d2, reg0d2); + _io_iface->poke8(0x0d1, reg0d1); + _io_iface->poke8(0x0d0, reg0d0); +} + +/* Calibrate the RX TIAs. + * + * Note that the values in the TIA register, after calibration, vary with + * the RX gain settings. */ +void ad9361_device_t::_calibrate_rx_TIAs() +{ + boost::uint8_t reg1eb = _io_iface->peek8(0x1eb) & 0x3F; + boost::uint8_t reg1ec = _io_iface->peek8(0x1ec) & 0x7F; + boost::uint8_t reg1e6 = _io_iface->peek8(0x1e6) & 0x07; + boost::uint8_t reg1db = 0x00; + boost::uint8_t reg1dc = 0x00; + boost::uint8_t reg1dd = 0x00; + boost::uint8_t reg1de = 0x00; + boost::uint8_t reg1df = 0x00; + + /* For calibration, baseband BW is half the complex BW, and must be + * between 28e6 and 0.2e6. */ + double bbbw = _baseband_bw / 2.0; + if (bbbw > 20e6) { + bbbw = 20e6; + } else if (bbbw < 0.20e6) { + bbbw = 0.20e6; + } + double ceil_bbbw_mhz = std::ceil(bbbw / 1e6); + + /* Do some crazy resistor and capacitor math. */ + int Cbbf = (reg1eb * 160) + (reg1ec * 10) + 140; + int R2346 = 18300 * (reg1e6 & 0x07); + double CTIA_fF = (Cbbf * R2346 * 0.56) / 3500; + + /* Translate baseband BW to register settings. */ + if (ceil_bbbw_mhz <= 3) { + reg1db = 0xe0; + } else if ((ceil_bbbw_mhz > 3) && (ceil_bbbw_mhz <= 10)) { + reg1db = 0x60; + } else if (ceil_bbbw_mhz > 10) { + reg1db = 0x20; + } else { + throw uhd::runtime_error("[ad9361_device_t] CalRxTias: INVALID_CODE_PATH bad bbbw_mhz"); + } + + if (CTIA_fF > 2920) { + reg1dc = 0x40; + reg1de = 0x40; + boost::uint8_t temp = (boost::uint8_t) std::min<boost::uint8_t>(127, + boost::uint8_t(std::floor(0.5 + ((CTIA_fF - 400.0) / 320.0)))); + reg1dd = temp; + reg1df = temp; + } else { + boost::uint8_t temp = boost::uint8_t(std::floor(0.5 + ((CTIA_fF - 400.0) / 40.0)) + 0x40); + reg1dc = temp; + reg1de = temp; + reg1dd = 0; + reg1df = 0; + } + + /* w00t. Settings calculated. Program them and roll out. */ + _io_iface->poke8(0x1db, reg1db); + _io_iface->poke8(0x1dd, reg1dd); + _io_iface->poke8(0x1df, reg1df); + _io_iface->poke8(0x1dc, reg1dc); + _io_iface->poke8(0x1de, reg1de); +} + +/* Setup the AD9361 ADC. + * + * There are 40 registers that control the ADC's operation, most of the + * values of which must be derived mathematically, dependent on the current + * setting of the BBPLL. Note that the order of calculation is critical, as + * some of the 40 registers depend on the values in others. */ +void ad9361_device_t::_setup_adc() +{ + double bbbw_mhz = (((_bbpll_freq / 1e6) / _rx_bbf_tunediv) * M_LN2) \ + / (1.4 * 2 * M_PI); + + /* For calibration, baseband BW is half the complex BW, and must be + * between 28e6 and 0.2e6. */ + if(bbbw_mhz > 28) { + bbbw_mhz = 28; + } else if (bbbw_mhz < 0.20) { + bbbw_mhz = 0.20; + } + + boost::uint8_t rxbbf_c3_msb = _io_iface->peek8(0x1eb) & 0x3F; + boost::uint8_t rxbbf_c3_lsb = _io_iface->peek8(0x1ec) & 0x7F; + boost::uint8_t rxbbf_r2346 = _io_iface->peek8(0x1e6) & 0x07; + + double fsadc = _adcclock_freq / 1e6; + + /* Sort out the RC time constant for our baseband bandwidth... */ + double rc_timeconst = 0.0; + if(bbbw_mhz < 18) { + rc_timeconst = (1 / ((1.4 * 2 * M_PI) \ + * (18300 * rxbbf_r2346) + * ((160e-15 * rxbbf_c3_msb) + + (10e-15 * rxbbf_c3_lsb) + 140e-15) + * (bbbw_mhz * 1e6))); + } else { + rc_timeconst = (1 / ((1.4 * 2 * M_PI) \ + * (18300 * rxbbf_r2346) + * ((160e-15 * rxbbf_c3_msb) + + (10e-15 * rxbbf_c3_lsb) + 140e-15) + * (bbbw_mhz * 1e6) * (1 + (0.01 * (bbbw_mhz - 18))))); + } + + double scale_res = sqrt(1 / rc_timeconst); + double scale_cap = sqrt(1 / rc_timeconst); + + double scale_snr = (_adcclock_freq < 80e6) ? 1.0 : 1.584893192; + double maxsnr = 640 / 160; + + /* Calculate the values for all 40 settings registers. + * + * DO NOT TOUCH THIS UNLESS YOU KNOW EXACTLY WHAT YOU ARE DOING. kthx.*/ + boost::uint8_t data[40]; + data[0] = 0; data[1] = 0; data[2] = 0; data[3] = 0x24; + data[4] = 0x24; data[5] = 0; data[6] = 0; + data[7] = std::min<boost::uint8_t>(124, boost::uint8_t(std::floor(-0.5 + + (80.0 * scale_snr * scale_res + * std::min<double>(1.0, sqrt(maxsnr * fsadc / 640.0)))))); + double data007 = data[7]; + data[8] = std::min<boost::uint8_t>(255, boost::uint8_t(std::floor(0.5 + + ((20.0 * (640.0 / fsadc) * ((data007 / 80.0)) + / (scale_res * scale_cap)))))); + data[10] = std::min<boost::uint8_t>(127, boost::uint8_t(std::floor(-0.5 + (77.0 * scale_res + * std::min<double>(1.0, sqrt(maxsnr * fsadc / 640.0)))))); + double data010 = data[10]; + data[9] = std::min<boost::uint8_t>(127, boost::uint8_t(std::floor(0.8 * data010))); + data[11] = std::min<boost::uint8_t>(255, boost::uint8_t(std::floor(0.5 + + (20.0 * (640.0 / fsadc) * ((data010 / 77.0) + / (scale_res * scale_cap)))))); + data[12] = std::min<boost::uint8_t>(127, boost::uint8_t(std::floor(-0.5 + + (80.0 * scale_res * std::min<double>(1.0, + sqrt(maxsnr * fsadc / 640.0)))))); + double data012 = data[12]; + data[13] = std::min<boost::uint8_t>(255, boost::uint8_t(std::floor(-1.5 + + (20.0 * (640.0 / fsadc) * ((data012 / 80.0) + / (scale_res * scale_cap)))))); + data[14] = 21 * boost::uint8_t(std::floor(0.1 * 640.0 / fsadc)); + data[15] = std::min<boost::uint8_t>(127, boost::uint8_t(1.025 * data007)); + double data015 = data[15]; + data[16] = std::min<boost::uint8_t>(127, boost::uint8_t(std::floor((data015 + * (0.98 + (0.02 * std::max<double>(1.0, + (640.0 / fsadc) / maxsnr))))))); + data[17] = data[15]; + data[18] = std::min<boost::uint8_t>(127, boost::uint8_t(0.975 * (data010))); + double data018 = data[18]; + data[19] = std::min<boost::uint8_t>(127, boost::uint8_t(std::floor((data018 + * (0.98 + (0.02 * std::max<double>(1.0, + (640.0 / fsadc) / maxsnr))))))); + data[20] = data[18]; + data[21] = std::min<boost::uint8_t>(127, boost::uint8_t(0.975 * data012)); + double data021 = data[21]; + data[22] = std::min<boost::uint8_t>(127, boost::uint8_t(std::floor((data021 + * (0.98 + (0.02 * std::max<double>(1.0, + (640.0 / fsadc) / maxsnr))))))); + data[23] = data[21]; + data[24] = 0x2e; + data[25] = boost::uint8_t(std::floor(128.0 + std::min<double>(63.0, + 63.0 * (fsadc / 640.0)))); + data[26] = boost::uint8_t(std::floor(std::min<double>(63.0, 63.0 * (fsadc / 640.0) + * (0.92 + (0.08 * (640.0 / fsadc)))))); + data[27] = boost::uint8_t(std::floor(std::min<double>(63.0, + 32.0 * sqrt(fsadc / 640.0)))); + data[28] = boost::uint8_t(std::floor(128.0 + std::min<double>(63.0, + 63.0 * (fsadc / 640.0)))); + data[29] = boost::uint8_t(std::floor(std::min<double>(63.0, + 63.0 * (fsadc / 640.0) + * (0.92 + (0.08 * (640.0 / fsadc)))))); + data[30] = boost::uint8_t(std::floor(std::min<double>(63.0, + 32.0 * sqrt(fsadc / 640.0)))); + data[31] = boost::uint8_t(std::floor(128.0 + std::min<double>(63.0, + 63.0 * (fsadc / 640.0)))); + data[32] = boost::uint8_t(std::floor(std::min<double>(63.0, + 63.0 * (fsadc / 640.0) * (0.92 + + (0.08 * (640.0 / fsadc)))))); + data[33] = boost::uint8_t(std::floor(std::min<double>(63.0, + 63.0 * sqrt(fsadc / 640.0)))); + data[34] = std::min<boost::uint8_t>(127, boost::uint8_t(std::floor(64.0 + * sqrt(fsadc / 640.0)))); + data[35] = 0x40; + data[36] = 0x40; + data[37] = 0x2c; + data[38] = 0x00; + data[39] = 0x00; + + /* Program the registers! */ + for(size_t i = 0; i < 40; i++) { + _io_iface->poke8(0x200+i, data[i]); + } +} + +/* Calibrate the baseband DC offset. + * + * Note that this function is called from within the TX quadrature + * calibration function! */ +void ad9361_device_t::_calibrate_baseband_dc_offset() +{ + _io_iface->poke8(0x193, 0x3f); // Calibration settings + _io_iface->poke8(0x190, 0x0f); // Set tracking coefficient + //write_ad9361_reg(device, 0x190, /*0x0f*//*0xDF*/0x80*1 | 0x40*1 | (16+8/*+4*/)); // Set tracking coefficient: don't *4 counter, do decim /4, increased gain shift + _io_iface->poke8(0x194, 0x01); // More calibration settings + + /* Start that calibration, baby. */ + size_t count = 0; + _io_iface->poke8(0x016, 0x01); + while (_io_iface->peek8(0x016) & 0x01) { + if (count > 100) { + throw uhd::runtime_error("[ad9361_device_t] Baseband DC Offset Calibration Failure"); + break; + } + count++; + boost::this_thread::sleep(boost::posix_time::milliseconds(5)); + } +} + +/* Calibrate the RF DC offset. + * + * Note that this function is called from within the TX quadrature + * calibration function. */ +void ad9361_device_t::_calibrate_rf_dc_offset() +{ + /* Some settings are frequency-dependent. */ + if (_rx_freq < 4e9) { + _io_iface->poke8(0x186, 0x32); // RF DC Offset count + _io_iface->poke8(0x187, 0x24); + _io_iface->poke8(0x188, 0x05); + } else { + _io_iface->poke8(0x186, 0x28); // RF DC Offset count + _io_iface->poke8(0x187, 0x34); + _io_iface->poke8(0x188, 0x06); + } + + _io_iface->poke8(0x185, 0x20); // RF DC Offset wait count + _io_iface->poke8(0x18b, 0x83); + _io_iface->poke8(0x189, 0x30); + + /* Run the calibration! */ + size_t count = 0; + _io_iface->poke8(0x016, 0x02); + while (_io_iface->peek8(0x016) & 0x02) { + if (count > 100) { + throw uhd::runtime_error("[ad9361_device_t] RF DC Offset Calibration Failure"); + break; + } + count++; + boost::this_thread::sleep(boost::posix_time::milliseconds(50)); + } +} + +/* Start the RX quadrature calibration. + * + * Note that we are using AD9361's 'tracking' feature for RX quadrature + * calibration, so once it starts it continues to free-run during operation. + * It should be re-run for large frequency changes. */ +void ad9361_device_t::_calibrate_rx_quadrature() +{ + /* Configure RX Quadrature calibration settings. */ + _io_iface->poke8(0x168, 0x03); // Set tone level for cal + _io_iface->poke8(0x16e, 0x25); // RX Gain index to use for cal + _io_iface->poke8(0x16a, 0x75); // Set Kexp phase + _io_iface->poke8(0x16b, 0x15); // Set Kexp amplitude + _io_iface->poke8(0x169, 0xcf); // Continuous tracking mode + _io_iface->poke8(0x18b, 0xad); +} + +/* TX quadtrature calibration routine. + * + * The TX quadrature needs to be done twice, once for each TX chain, with + * only one register change in between. Thus, this function enacts the + * calibrations, and it is called from calibrate_tx_quadrature. */ +void ad9361_device_t::_tx_quadrature_cal_routine() { + /* This is a weird process, but here is how it works: + * 1) Read the calibrated NCO frequency bits out of 0A3. + * 2) Write the two bits to the RX NCO freq part of 0A0. + * 3) Re-read 0A3 to get bits [5:0] because maybe they changed? + * 4) Update only the TX NCO freq bits in 0A3. + * 5) Profit (I hope). */ + boost::uint8_t reg0a3 = _io_iface->peek8(0x0a3); + boost::uint8_t nco_freq = (reg0a3 & 0xC0); + _io_iface->poke8(0x0a0, 0x15 | (nco_freq >> 1)); + reg0a3 = _io_iface->peek8(0x0a3); + _io_iface->poke8(0x0a3, (reg0a3 & 0x3F) | nco_freq); + + /* It is possible to reach a configuration that won't operate correctly, + * where the two test tones used for quadrature calibration are outside + * of the RX BBF, and therefore don't make it to the ADC. We will check + * for that scenario here. */ + double max_cal_freq = (((_baseband_bw * _tfir_factor) + * ((nco_freq >> 6) + 1)) / 32) * 2; + double bbbw = _baseband_bw / 2.0; // bbbw represents the one-sided BW + if (bbbw > 28e6) { + bbbw = 28e6; + } else if (bbbw < 0.20e6) { + bbbw = 0.20e6; + } + if (max_cal_freq > bbbw) + throw uhd::runtime_error("[ad9361_device_t] max_cal_freq > bbbw"); + + _io_iface->poke8(0x0a1, 0x7B); // Set tracking coefficient + _io_iface->poke8(0x0a9, 0xff); // Cal count + _io_iface->poke8(0x0a2, 0x7f); // Cal Kexp + _io_iface->poke8(0x0a5, 0x01); // Cal magnitude threshold VVVV + _io_iface->poke8(0x0a6, 0x01); + + /* The gain table index used for calibration must be adjusted for the + * mid-table to get a TIA index = 1 and LPF index = 0. */ + if ((_rx_freq >= 1300e6) && (_rx_freq < 4000e6)) { + _io_iface->poke8(0x0aa, 0x22); // Cal gain table index + } else { + _io_iface->poke8(0x0aa, 0x25); // Cal gain table index + } + + _io_iface->poke8(0x0a4, 0xf0); // Cal setting conut + _io_iface->poke8(0x0ae, 0x00); // Cal LPF gain index (split mode) + + /* First, calibrate the baseband DC offset. */ + _calibrate_baseband_dc_offset(); + + /* Second, calibrate the RF DC offset. */ + _calibrate_rf_dc_offset(); + + /* Now, calibrate the TX quadrature! */ + size_t count = 0; + _io_iface->poke8(0x016, 0x10); + while (_io_iface->peek8(0x016) & 0x10) { + if (count > 100) { + throw uhd::runtime_error("[ad9361_device_t] TX Quadrature Calibration Failure"); + break; + } + count++; + boost::this_thread::sleep(boost::posix_time::milliseconds(10)); + } +} + +/* Run the TX quadrature calibration. + * + * Note that from within this function we are also triggering the baseband + * and RF DC calibrations. */ +void ad9361_device_t::_calibrate_tx_quadrature() +{ + /* Make sure we are, in fact, in the ALERT state. If not, something is + * terribly wrong in the driver execution flow. */ + if ((_io_iface->peek8(0x017) & 0x0F) != 5) { + throw uhd::runtime_error("[ad9361_device_t] TX Quad Cal started, but not in ALERT"); + } + + /* Turn off free-running and continuous calibrations. Note that this + * will get turned back on at the end of the RX calibration routine. */ + _io_iface->poke8(0x169, 0xc0); + + /* This calibration must be done in a certain order, and for both TX_A + * and TX_B, separately. Store the original setting so that we can + * restore it later. */ + boost::uint8_t orig_reg_inputsel = _regs.inputsel; + + /*********************************************************************** + * TX1/2-A Calibration + **********************************************************************/ + _regs.inputsel = _regs.inputsel & 0xBF; + _io_iface->poke8(0x004, _regs.inputsel); + + _tx_quadrature_cal_routine(); + + /*********************************************************************** + * TX1/2-B Calibration + **********************************************************************/ + _regs.inputsel = _regs.inputsel | 0x40; + _io_iface->poke8(0x004, _regs.inputsel); + + _tx_quadrature_cal_routine(); + + /*********************************************************************** + * fin + **********************************************************************/ + _regs.inputsel = orig_reg_inputsel; + _io_iface->poke8(0x004, orig_reg_inputsel); +} + + +/*********************************************************************** + * Other Misc Setup Functions + ***********************************************************************/ + +/* Program the mixer gain table. + * + * Note that this table is fixed for all frequency settings. */ +void ad9361_device_t::_program_mixer_gm_subtable() +{ + boost::uint8_t gain[] = { 0x78, 0x74, 0x70, 0x6C, 0x68, 0x64, 0x60, 0x5C, 0x58, + 0x54, 0x50, 0x4C, 0x48, 0x30, 0x18, 0x00 }; + boost::uint8_t gm[] = { 0x00, 0x0D, 0x15, 0x1B, 0x21, 0x25, 0x29, 0x2C, 0x2F, 0x31, + 0x33, 0x34, 0x35, 0x3A, 0x3D, 0x3E }; + + /* Start the clock. */ + _io_iface->poke8(0x13f, 0x02); + + /* Program the GM Sub-table. */ + int i; + for (i = 15; i >= 0; i--) { + _io_iface->poke8(0x138, i); + _io_iface->poke8(0x139, gain[(15 - i)]); + _io_iface->poke8(0x13A, 0x00); + _io_iface->poke8(0x13B, gm[(15 - i)]); + _io_iface->poke8(0x13F, 0x06); + _io_iface->poke8(0x13C, 0x00); + _io_iface->poke8(0x13C, 0x00); + } + + /* Clear write bit and stop clock. */ + _io_iface->poke8(0x13f, 0x02); + _io_iface->poke8(0x13C, 0x00); + _io_iface->poke8(0x13C, 0x00); + _io_iface->poke8(0x13f, 0x00); +} + +/* Program the gain table. + * + * There are three different gain tables for different frequency ranges! */ +void ad9361_device_t::_program_gain_table() { + /* Figure out which gain table we should be using for our current + * frequency band. */ + boost::uint8_t (*gain_table)[5] = NULL; + boost::uint8_t new_gain_table; + if (_rx_freq < 1300e6) { + gain_table = gain_table_sub_1300mhz; + new_gain_table = 1; + } else if (_rx_freq < 4e9) { + gain_table = gain_table_1300mhz_to_4000mhz; + new_gain_table = 2; + } else if (_rx_freq <= 6e9) { + gain_table = gain_table_4000mhz_to_6000mhz; + new_gain_table = 3; + } else { + throw uhd::runtime_error("[ad9361_device_t] Wrong _rx_freq value"); + new_gain_table = 1; + } + + /* Only re-program the gain table if there has been a band change. */ + if (_curr_gain_table == new_gain_table) { + return; + } else { + _curr_gain_table = new_gain_table; + } + + /* Okay, we have to program a new gain table. Sucks, brah. Start the + * gain table clock. */ + _io_iface->poke8(0x137, 0x1A); + + /* IT'S PROGRAMMING TIME. */ + boost::uint8_t index = 0; + for (; index < 77; index++) { + _io_iface->poke8(0x130, index); + _io_iface->poke8(0x131, gain_table[index][1]); + _io_iface->poke8(0x132, gain_table[index][2]); + _io_iface->poke8(0x133, gain_table[index][3]); + _io_iface->poke8(0x137, 0x1E); + _io_iface->poke8(0x134, 0x00); + _io_iface->poke8(0x134, 0x00); + } + + /* Everything above the 77th index is zero. */ + for (; index < 91; index++) { + _io_iface->poke8(0x130, index); + _io_iface->poke8(0x131, 0x00); + _io_iface->poke8(0x132, 0x00); + _io_iface->poke8(0x133, 0x00); + _io_iface->poke8(0x137, 0x1E); + _io_iface->poke8(0x134, 0x00); + _io_iface->poke8(0x134, 0x00); + } + + /* Clear the write bit and stop the gain clock. */ + _io_iface->poke8(0x137, 0x1A); + _io_iface->poke8(0x134, 0x00); + _io_iface->poke8(0x134, 0x00); + _io_iface->poke8(0x137, 0x00); +} + +/* Setup gain control registers. + * + * This really only needs to be done once, at initialization. */ +void ad9361_device_t::_setup_gain_control() +{ + _io_iface->poke8(0x0FA, 0xE0); // Gain Control Mode Select + _io_iface->poke8(0x0FB, 0x08); // Table, Digital Gain, Man Gain Ctrl + _io_iface->poke8(0x0FC, 0x23); // Incr Step Size, ADC Overrange Size + _io_iface->poke8(0x0FD, 0x4C); // Max Full/LMT Gain Table Index + _io_iface->poke8(0x0FE, 0x44); // Decr Step Size, Peak Overload Time + _io_iface->poke8(0x100, 0x6F); // Max Digital Gain + _io_iface->poke8(0x104, 0x2F); // ADC Small Overload Threshold + _io_iface->poke8(0x105, 0x3A); // ADC Large Overload Threshold + _io_iface->poke8(0x107, 0x31); // Large LMT Overload Threshold + _io_iface->poke8(0x108, 0x39); // Small LMT Overload Threshold + _io_iface->poke8(0x109, 0x23); // Rx1 Full/LMT Gain Index + _io_iface->poke8(0x10A, 0x58); // Rx1 LPF Gain Index + _io_iface->poke8(0x10B, 0x00); // Rx1 Digital Gain Index + _io_iface->poke8(0x10C, 0x23); // Rx2 Full/LMT Gain Index + _io_iface->poke8(0x10D, 0x18); // Rx2 LPF Gain Index + _io_iface->poke8(0x10E, 0x00); // Rx2 Digital Gain Index + _io_iface->poke8(0x114, 0x30); // Low Power Threshold + _io_iface->poke8(0x11A, 0x27); // Initial LMT Gain Limit + _io_iface->poke8(0x081, 0x00); // Tx Symbol Gain Control +} + +/* Setup the RX or TX synthesizers. + * + * This setup depends on a fixed look-up table, which is stored in an + * included header file. The table is indexed based on the passed VCO rate. + */ +void ad9361_device_t::_setup_synth(direction_t direction, double vcorate) +{ + /* The vcorates in the vco_index array represent lower boundaries for + * rates. Once we find a match, we use that index to look-up the rest of + * the register values in the LUT. */ + int vcoindex = 0; + for (size_t i = 0; i < 53; i++) { + vcoindex = i; + if (vcorate > vco_index[i]) { + break; + } + } + if (vcoindex > 53) + throw uhd::runtime_error("[ad9361_device_t] vcoindex > 53"); + + /* Parse the values out of the LUT based on our calculated index... */ + boost::uint8_t vco_output_level = synth_cal_lut[vcoindex][0]; + boost::uint8_t vco_varactor = synth_cal_lut[vcoindex][1]; + boost::uint8_t vco_bias_ref = synth_cal_lut[vcoindex][2]; + boost::uint8_t vco_bias_tcf = synth_cal_lut[vcoindex][3]; + boost::uint8_t vco_cal_offset = synth_cal_lut[vcoindex][4]; + boost::uint8_t vco_varactor_ref = synth_cal_lut[vcoindex][5]; + boost::uint8_t charge_pump_curr = synth_cal_lut[vcoindex][6]; + boost::uint8_t loop_filter_c2 = synth_cal_lut[vcoindex][7]; + boost::uint8_t loop_filter_c1 = synth_cal_lut[vcoindex][8]; + boost::uint8_t loop_filter_r1 = synth_cal_lut[vcoindex][9]; + boost::uint8_t loop_filter_c3 = synth_cal_lut[vcoindex][10]; + boost::uint8_t loop_filter_r3 = synth_cal_lut[vcoindex][11]; + + /* ... annnd program! */ + if (direction == RX) { + _io_iface->poke8(0x23a, 0x40 | vco_output_level); + _io_iface->poke8(0x239, 0xC0 | vco_varactor); + _io_iface->poke8(0x242, vco_bias_ref | (vco_bias_tcf << 3)); + _io_iface->poke8(0x238, (vco_cal_offset << 3)); + _io_iface->poke8(0x245, 0x00); + _io_iface->poke8(0x251, vco_varactor_ref); + _io_iface->poke8(0x250, 0x70); + _io_iface->poke8(0x23b, 0x80 | charge_pump_curr); + _io_iface->poke8(0x23e, loop_filter_c1 | (loop_filter_c2 << 4)); + _io_iface->poke8(0x23f, loop_filter_c3 | (loop_filter_r1 << 4)); + _io_iface->poke8(0x240, loop_filter_r3); + } else if (direction == TX) { + _io_iface->poke8(0x27a, 0x40 | vco_output_level); + _io_iface->poke8(0x279, 0xC0 | vco_varactor); + _io_iface->poke8(0x282, vco_bias_ref | (vco_bias_tcf << 3)); + _io_iface->poke8(0x278, (vco_cal_offset << 3)); + _io_iface->poke8(0x285, 0x00); + _io_iface->poke8(0x291, vco_varactor_ref); + _io_iface->poke8(0x290, 0x70); + _io_iface->poke8(0x27b, 0x80 | charge_pump_curr); + _io_iface->poke8(0x27e, loop_filter_c1 | (loop_filter_c2 << 4)); + _io_iface->poke8(0x27f, loop_filter_c3 | (loop_filter_r1 << 4)); + _io_iface->poke8(0x280, loop_filter_r3); + } else { + throw uhd::runtime_error("[ad9361_device_t] [_setup_synth] INVALID_CODE_PATH"); + } +} + + +/* Tune the baseband VCO. + * + * This clock signal is what gets fed to the ADCs and DACs. This function is + * not exported outside of this file, and is invoked based on the rate + * fed to the public set_clock_rate function. */ +double ad9361_device_t::_tune_bbvco(const double rate) +{ + UHD_LOG << boost::format("[ad9361_device_t::_tune_bbvco] rate=%.10f\n") % rate; + + /* Let's not re-tune to the same frequency over and over... */ + if (freq_is_nearly_equal(rate, _req_coreclk)) { + return _adcclock_freq; + } + + _req_coreclk = rate; + + const double fref = 40e6; + const int modulus = 2088960; + const double vcomax = 1430e6; + const double vcomin = 672e6; + double vcorate; + int vcodiv; + + /* Iterate over VCO dividers until appropriate divider is found. */ + int i = 1; + for (; i <= 6; i++) { + vcodiv = 1 << i; + vcorate = rate * vcodiv; + + if (vcorate >= vcomin && vcorate <= vcomax) + break; + } + if (i == 7) + throw uhd::runtime_error("[ad9361_device_t] _tune_bbvco: wrong vcorate"); + + UHD_LOG << boost::format("[ad9361_device_t::_tune_bbvco] vcodiv=%d vcorate=%.10f\n") % vcodiv % vcorate; + /* Fo = Fref * (Nint + Nfrac / mod) */ + int nint = static_cast<int>(vcorate / fref); + UHD_LOG << boost::format("[ad9361_device_t::_tune_bbvco] (nint)=%.10f\n") % (vcorate / fref); + int nfrac = static_cast<int>(boost::math::round(((vcorate / fref) - (double) nint) * (double) modulus)); + UHD_LOG << boost::format("[ad9361_device_t::_tune_bbvco] (nfrac)=%.10f\n") % (((vcorate / fref) - (double) nint) * (double) modulus); + UHD_LOG << boost::format("[ad9361_device_t::_tune_bbvco] nint=%d nfrac=%d\n") % nint % nfrac; + double actual_vcorate = fref + * ((double) nint + ((double) nfrac / (double) modulus)); + + /* Scale CP current according to VCO rate */ + const double icp_baseline = 150e-6; + const double freq_baseline = 1280e6; + double icp = icp_baseline * (actual_vcorate / freq_baseline); + int icp_reg = static_cast<int>(icp / 25e-6) - 1; + + _io_iface->poke8(0x045, 0x00); // REFCLK / 1 to BBPLL + _io_iface->poke8(0x046, icp_reg & 0x3F); // CP current + _io_iface->poke8(0x048, 0xe8); // BBPLL loop filters + _io_iface->poke8(0x049, 0x5b); // BBPLL loop filters + _io_iface->poke8(0x04a, 0x35); // BBPLL loop filters + + _io_iface->poke8(0x04b, 0xe0); + _io_iface->poke8(0x04e, 0x10); // Max accuracy + + _io_iface->poke8(0x043, nfrac & 0xFF); // Nfrac[7:0] + _io_iface->poke8(0x042, (nfrac >> 8) & 0xFF); // Nfrac[15:8] + _io_iface->poke8(0x041, (nfrac >> 16) & 0xFF); // Nfrac[23:16] + _io_iface->poke8(0x044, nint); // Nint + + _calibrate_lock_bbpll(); + + _regs.bbpll = (_regs.bbpll & 0xF8) | i; + + _bbpll_freq = actual_vcorate; + _adcclock_freq = (actual_vcorate / vcodiv); + + return _adcclock_freq; +} + +/* This function re-programs all of the gains in the system. + * + * Because the gain values match to different gain indices based on the + * current operating band, this function can be called to update all gain + * settings to the appropriate index after a re-tune. */ +void ad9361_device_t::_reprogram_gains() +{ + set_gain(RX, CHAIN_1,_rx1_gain); + set_gain(RX, CHAIN_2,_rx2_gain); + set_gain(TX, CHAIN_1,_tx1_gain); + set_gain(TX, CHAIN_2,_tx2_gain); +} + +/* This is the internal tune function, not available for a host call. + * + * Calculate the VCO settings for the requested frquency, and then either + * tune the RX or TX VCO. */ +double ad9361_device_t::_tune_helper(direction_t direction, const double value) +{ + /* The RFPLL runs from 6 GHz - 12 GHz */ + const double fref = 80e6; + const int modulus = 8388593; + const double vcomax = 12e9; + const double vcomin = 6e9; + double vcorate; + int vcodiv; + + /* Iterate over VCO dividers until appropriate divider is found. */ + int i; + for (i = 0; i <= 6; i++) { + vcodiv = 2 << i; + vcorate = value * vcodiv; + if (vcorate >= vcomin && vcorate <= vcomax) + break; + } + if (i == 7) + throw uhd::runtime_error("[ad9361_device_t] RFVCO can't find valid VCO rate!"); + + int nint = static_cast<int>(vcorate / fref); + int nfrac = static_cast<int>(((vcorate / fref) - nint) * modulus); + + double actual_vcorate = fref * (nint + (double) (nfrac) / modulus); + double actual_lo = actual_vcorate / vcodiv; + + if (direction == RX) { + + _req_rx_freq = value; + + /* Set band-specific settings. */ + if (value < _client_params->get_band_edge(AD9361_RX_BAND0)) { + _regs.inputsel = (_regs.inputsel & 0xC0) | 0x30; + } else if ((value + >= _client_params->get_band_edge(AD9361_RX_BAND0)) + && (value + < _client_params->get_band_edge(AD9361_RX_BAND1))) { + _regs.inputsel = (_regs.inputsel & 0xC0) | 0x0C; + } else if ((value + >= _client_params->get_band_edge(AD9361_RX_BAND1)) + && (value <= 6e9)) { + _regs.inputsel = (_regs.inputsel & 0xC0) | 0x03; + } else { + throw uhd::runtime_error("[ad9361_device_t] [_tune_helper] INVALID_CODE_PATH"); + } + + _io_iface->poke8(0x004, _regs.inputsel); + + /* Store vcodiv setting. */ + _regs.vcodivs = (_regs.vcodivs & 0xF0) | (i & 0x0F); + + /* Setup the synthesizer. */ + _setup_synth(RX, actual_vcorate); + + /* Tune!!!! */ + _io_iface->poke8(0x233, nfrac & 0xFF); + _io_iface->poke8(0x234, (nfrac >> 8) & 0xFF); + _io_iface->poke8(0x235, (nfrac >> 16) & 0xFF); + _io_iface->poke8(0x232, (nint >> 8) & 0xFF); + _io_iface->poke8(0x231, nint & 0xFF); + _io_iface->poke8(0x005, _regs.vcodivs); + + /* Lock the PLL! */ + boost::this_thread::sleep(boost::posix_time::milliseconds(2)); + if ((_io_iface->peek8(0x247) & 0x02) == 0) { + throw uhd::runtime_error("[ad9361_device_t] RX PLL NOT LOCKED"); + } + + _rx_freq = actual_lo; + + return actual_lo; + + } else { + + _req_tx_freq = value; + + /* Set band-specific settings. */ + if (value < _client_params->get_band_edge(AD9361_TX_BAND0)) { + _regs.inputsel = _regs.inputsel | 0x40; + } else if ((value + >= _client_params->get_band_edge(AD9361_TX_BAND0)) + && (value <= 6e9)) { + _regs.inputsel = _regs.inputsel & 0xBF; + } else { + throw uhd::runtime_error("[ad9361_device_t] [_tune_helper] INVALID_CODE_PATH"); + } + + _io_iface->poke8(0x004, _regs.inputsel); + + /* Store vcodiv setting. */ + _regs.vcodivs = (_regs.vcodivs & 0x0F) | ((i & 0x0F) << 4); + + /* Setup the synthesizer. */ + _setup_synth(TX, actual_vcorate); + + /* Tune it, homey. */ + _io_iface->poke8(0x273, nfrac & 0xFF); + _io_iface->poke8(0x274, (nfrac >> 8) & 0xFF); + _io_iface->poke8(0x275, (nfrac >> 16) & 0xFF); + _io_iface->poke8(0x272, (nint >> 8) & 0xFF); + _io_iface->poke8(0x271, nint & 0xFF); + _io_iface->poke8(0x005, _regs.vcodivs); + + /* Lock the PLL! */ + boost::this_thread::sleep(boost::posix_time::milliseconds(2)); + if ((_io_iface->peek8(0x287) & 0x02) == 0) { + throw uhd::runtime_error("[ad9361_device_t] TX PLL NOT LOCKED"); + } + + _tx_freq = actual_lo; + + return actual_lo; + } +} + +/* Configure the various clock / sample rates in the RX and TX chains. + * + * Functionally, this function configures AD9361's RX and TX rates. For + * a requested TX & RX rate, it sets the interpolation & decimation filters, + * and tunes the VCO that feeds the ADCs and DACs. + */ +double ad9361_device_t::_setup_rates(const double rate) +{ + /* If we make it into this function, then we are tuning to a new rate. + * Store the new rate. */ + _req_clock_rate = rate; + + /* Set the decimation and interpolation values in the RX and TX chains. + * This also switches filters in / out. Note that all transmitters and + * receivers have to be turned on for the calibration portion of + * bring-up, and then they will be switched out to reflect the actual + * user-requested antenna selections. */ + int divfactor = 0; + _tfir_factor = 0; + if (rate < 0.33e6) { + // RX1 + RX2 enabled, 3, 2, 2, 4 + _regs.rxfilt = B8(11101111); + + // TX1 + TX2 enabled, 3, 2, 2, 4 + _regs.txfilt = B8(11101111); + + divfactor = 48; + _tfir_factor = 2; + } else if (rate < 0.66e6) { + // RX1 + RX2 enabled, 2, 2, 2, 4 + _regs.rxfilt = B8(11011111); + + // TX1 + TX2 enabled, 2, 2, 2, 4 + _regs.txfilt = B8(11011111); + + divfactor = 32; + _tfir_factor = 2; + } else if (rate <= 20e6) { + // RX1 + RX2 enabled, 2, 2, 2, 2 + _regs.rxfilt = B8(11011110); + + // TX1 + TX2 enabled, 2, 2, 2, 2 + _regs.txfilt = B8(11011110); + + divfactor = 16; + _tfir_factor = 2; + } else if ((rate > 20e6) && (rate < 23e6)) { + // RX1 + RX2 enabled, 3, 2, 2, 2 + _regs.rxfilt = B8(11101110); + + // TX1 + TX2 enabled, 3, 1, 2, 2 + _regs.txfilt = B8(11100110); + + divfactor = 24; + _tfir_factor = 2; + } else if ((rate >= 23e6) && (rate < 41e6)) { + // RX1 + RX2 enabled, 2, 2, 2, 2 + _regs.rxfilt = B8(11011110); + + // TX1 + TX2 enabled, 1, 2, 2, 2 + _regs.txfilt = B8(11001110); + + divfactor = 16; + _tfir_factor = 2; + } else if ((rate >= 41e6) && (rate <= 56e6)) { + // RX1 + RX2 enabled, 3, 1, 2, 2 + _regs.rxfilt = B8(11100110); + + // TX1 + TX2 enabled, 3, 1, 1, 2 + _regs.txfilt = B8(11100010); + + divfactor = 12; + _tfir_factor = 2; + } else if ((rate > 56e6) && (rate <= 61.44e6)) { + // RX1 + RX2 enabled, 3, 1, 1, 2 + _regs.rxfilt = B8(11100010); + + // TX1 + TX2 enabled, 3, 1, 1, 1 + _regs.txfilt = B8(11100001); + + divfactor = 6; + _tfir_factor = 1; + } else { + // should never get in here + throw uhd::runtime_error("[ad9361_device_t] [_setup_rates] INVALID_CODE_PATH"); + } + + UHD_LOG << boost::format("[ad9361_device_t::_setup_rates] divfactor=%d\n") % divfactor; + + /* Tune the BBPLL to get the ADC and DAC clocks. */ + const double adcclk = _tune_bbvco(rate * divfactor); + double dacclk = adcclk; + + /* The DAC clock must be <= 336e6, and is either the ADC clock or 1/2 the + * ADC clock.*/ + if (adcclk > 336e6) { + /* Make the DAC clock = ADC/2, and bypass the TXFIR. */ + _regs.bbpll = _regs.bbpll | 0x08; + dacclk = adcclk / 2.0; + } else { + _regs.bbpll = _regs.bbpll & 0xF7; + } + + /* Set the dividers / interpolators in AD9361. */ + _io_iface->poke8(0x002, _regs.txfilt); + _io_iface->poke8(0x003, _regs.rxfilt); + _io_iface->poke8(0x004, _regs.inputsel); + _io_iface->poke8(0x00A, _regs.bbpll); + + UHD_LOG << boost::format("[ad9361_device_t::_setup_rates] adcclk=%f\n") % adcclk; + _baseband_bw = (adcclk / divfactor); + + /* + The Tx & Rx FIR calculate 16 taps per clock cycle. This limits the number of available taps to the ratio of DAC_CLK/ADC_CLK + to the input data rate multiplied by 16. For example, if the input data rate is 25 MHz and DAC_CLK is 100 MHz, + then the ratio of DAC_CLK to the input data rate is 100/25 or 4. In this scenario, the total number of taps available is 64. + + Also, whilst the Rx FIR filter always has memory available for 128 taps, the Tx FIR Filter can only support a maximum length of 64 taps + in 1x interpolation mode, and 128 taps in 2x & 4x modes. + */ + const size_t max_tx_taps = std::min<size_t>( + std::min<size_t>((16 * (int)((dacclk / rate) + 0.5)), 128), + (_tfir_factor == 1) ? 64 : 128); + const size_t max_rx_taps = std::min<size_t>((16 * (size_t)((adcclk / rate) + 0.5)), + 128); + + const size_t num_tx_taps = get_num_taps(max_tx_taps); + const size_t num_rx_taps = get_num_taps(max_rx_taps); + + _setup_tx_fir(num_tx_taps); + _setup_rx_fir(num_rx_taps); + + return _baseband_bw; +} + +/*********************************************************************** + * Publicly exported functions to host calls + **********************************************************************/ +void ad9361_device_t::initialize() +{ + boost::lock_guard<boost::recursive_mutex> lock(_mutex); + + /* Initialize shadow registers. */ + _regs.vcodivs = 0x00; + _regs.inputsel = 0x30; + _regs.rxfilt = 0x00; + _regs.txfilt = 0x00; + _regs.bbpll = 0x02; + _regs.bbftune_config = 0x1e; + _regs.bbftune_mode = 0x1e; + + /* Initialize private VRQ fields. */ + _rx_freq = 0.0; + _tx_freq = 0.0; + _req_rx_freq = 0.0; + _req_tx_freq = 0.0; + _baseband_bw = 0.0; + _req_clock_rate = 0.0; + _req_coreclk = 0.0; + _bbpll_freq = 0.0; + _adcclock_freq = 0.0; + _rx_bbf_tunediv = 0; + _curr_gain_table = 0; + _rx1_gain = 0; + _rx2_gain = 0; + _tx1_gain = 0; + _tx2_gain = 0; + + /* Reset the device. */ + _io_iface->poke8(0x000, 0x01); + _io_iface->poke8(0x000, 0x00); + boost::this_thread::sleep(boost::posix_time::milliseconds(20)); + + /* There is not a WAT big enough for this. */ + _io_iface->poke8(0x3df, 0x01); + + _io_iface->poke8(0x2a6, 0x0e); // Enable master bias + _io_iface->poke8(0x2a8, 0x0e); // Set bandgap trim + + /* Set RFPLL ref clock scale to REFCLK * 2 */ + _io_iface->poke8(0x2ab, 0x07); + _io_iface->poke8(0x2ac, 0xff); + + /* Enable clocks. */ + switch (_client_params->get_clocking_mode()) { + case AD9361_XTAL_N_CLK_PATH: { + _io_iface->poke8(0x009, 0x17); + } break; + + case AD9361_XTAL_P_CLK_PATH: { + _io_iface->poke8(0x009, 0x07); + _io_iface->poke8(0x292, 0x08); + _io_iface->poke8(0x293, 0x80); + _io_iface->poke8(0x294, 0x00); + _io_iface->poke8(0x295, 0x14); + } break; + + default: + throw uhd::runtime_error("[ad9361_device_t] NOT IMPLEMENTED"); + } + boost::this_thread::sleep(boost::posix_time::milliseconds(20)); + + /* Tune the BBPLL, write TX and RX FIRS. */ + _setup_rates(50e6); + + /* Setup data ports (FDD dual port DDR): + * FDD dual port DDR CMOS no swap. + * Force TX on one port, RX on the other. */ + switch (_client_params->get_digital_interface_mode()) { + case AD9361_DDR_FDD_LVCMOS: { + _io_iface->poke8(0x010, 0xc8); + _io_iface->poke8(0x011, 0x00); + _io_iface->poke8(0x012, 0x02); + } break; + + case AD9361_DDR_FDD_LVDS: { + _io_iface->poke8(0x010, 0xcc); + _io_iface->poke8(0x011, 0x00); + _io_iface->poke8(0x012, 0x10); + + //LVDS Specific + _io_iface->poke8(0x03C, 0x23); + _io_iface->poke8(0x03D, 0xFF); + _io_iface->poke8(0x03E, 0x0F); + } break; + + default: + throw uhd::runtime_error("[ad9361_device_t] NOT IMPLEMENTED"); + } + + /* Data delay for TX and RX data clocks */ + digital_interface_delays_t timing = + _client_params->get_digital_interface_timing(); + boost::uint8_t rx_delays = ((timing.rx_clk_delay & 0xF) << 4) + | (timing.rx_data_delay & 0xF); + boost::uint8_t tx_delays = ((timing.tx_clk_delay & 0xF) << 4) + | (timing.tx_data_delay & 0xF); + _io_iface->poke8(0x006, rx_delays); + _io_iface->poke8(0x007, tx_delays); + + /* Setup AuxDAC */ + _io_iface->poke8(0x018, 0x00); // AuxDAC1 Word[9:2] + _io_iface->poke8(0x019, 0x00); // AuxDAC2 Word[9:2] + _io_iface->poke8(0x01A, 0x00); // AuxDAC1 Config and Word[1:0] + _io_iface->poke8(0x01B, 0x00); // AuxDAC2 Config and Word[1:0] + _io_iface->poke8(0x022, 0x4A); // Invert Bypassed LNA + _io_iface->poke8(0x023, 0xFF); // AuxDAC Manaul/Auto Control + _io_iface->poke8(0x026, 0x00); // AuxDAC Manual Select Bit/GPO Manual Select + _io_iface->poke8(0x030, 0x00); // AuxDAC1 Rx Delay + _io_iface->poke8(0x031, 0x00); // AuxDAC1 Tx Delay + _io_iface->poke8(0x032, 0x00); // AuxDAC2 Rx Delay + _io_iface->poke8(0x033, 0x00); // AuxDAC2 Tx Delay + + /* Setup AuxADC */ + _io_iface->poke8(0x00B, 0x00); // Temp Sensor Setup (Offset) + _io_iface->poke8(0x00C, 0x00); // Temp Sensor Setup (Temp Window) + _io_iface->poke8(0x00D, 0x03); // Temp Sensor Setup (Periodic Measure) + _io_iface->poke8(0x00F, 0x04); // Temp Sensor Setup (Decimation) + _io_iface->poke8(0x01C, 0x10); // AuxADC Setup (Clock Div) + _io_iface->poke8(0x01D, 0x01); // AuxADC Setup (Decimation/Enable) + + /* Setup control outputs. */ + _io_iface->poke8(0x035, 0x01); + _io_iface->poke8(0x036, 0xFF); + + /* Setup GPO */ + _io_iface->poke8(0x03a, 0x27); //set delay register + _io_iface->poke8(0x020, 0x00); // GPO Auto Enable Setup in RX and TX + _io_iface->poke8(0x027, 0x03); // GPO Manual and GPO auto value in ALERT + _io_iface->poke8(0x028, 0x00); // GPO_0 RX Delay + _io_iface->poke8(0x029, 0x00); // GPO_1 RX Delay + _io_iface->poke8(0x02A, 0x00); // GPO_2 RX Delay + _io_iface->poke8(0x02B, 0x00); // GPO_3 RX Delay + _io_iface->poke8(0x02C, 0x00); // GPO_0 TX Delay + _io_iface->poke8(0x02D, 0x00); // GPO_1 TX Delay + _io_iface->poke8(0x02E, 0x00); // GPO_2 TX Delay + _io_iface->poke8(0x02F, 0x00); // GPO_3 TX Delay + + _io_iface->poke8(0x261, 0x00); // RX LO power + _io_iface->poke8(0x2a1, 0x00); // TX LO power + _io_iface->poke8(0x248, 0x0b); // en RX VCO LDO + _io_iface->poke8(0x288, 0x0b); // en TX VCO LDO + _io_iface->poke8(0x246, 0x02); // pd RX cal Tcf + _io_iface->poke8(0x286, 0x02); // pd TX cal Tcf + _io_iface->poke8(0x249, 0x8e); // rx vco cal length + _io_iface->poke8(0x289, 0x8e); // rx vco cal length + _io_iface->poke8(0x23b, 0x80); // set RX MSB?, FIXME 0x89 magic cp + _io_iface->poke8(0x27b, 0x80); // "" TX //FIXME 0x88 see above + _io_iface->poke8(0x243, 0x0d); // set rx prescaler bias + _io_iface->poke8(0x283, 0x0d); // "" TX + + _io_iface->poke8(0x23d, 0x00); // Clear half VCO cal clock setting + _io_iface->poke8(0x27d, 0x00); // Clear half VCO cal clock setting + + /* The order of the following process is EXTREMELY important. If the + * below functions are modified at all, device initialization and + * calibration might be broken in the process! */ + + _io_iface->poke8(0x015, 0x04); // dual synth mode, synth en ctrl en + _io_iface->poke8(0x014, 0x05); // use SPI for TXNRX ctrl, to ALERT, TX on + _io_iface->poke8(0x013, 0x01); // enable ENSM + boost::this_thread::sleep(boost::posix_time::milliseconds(1)); + + _calibrate_synth_charge_pumps(); + + _tune_helper(RX, 800e6); + _tune_helper(TX, 850e6); + + _program_mixer_gm_subtable(); + _program_gain_table(); + _setup_gain_control(); + + _calibrate_baseband_rx_analog_filter(); + _calibrate_baseband_tx_analog_filter(); + _calibrate_rx_TIAs(); + _calibrate_secondary_tx_filter(); + + _setup_adc(); + + _calibrate_tx_quadrature(); + _calibrate_rx_quadrature(); + + // cals done, set PPORT config + switch (_client_params->get_digital_interface_mode()) { + case AD9361_DDR_FDD_LVCMOS: { + _io_iface->poke8(0x012, 0x02); + } break; + + case AD9361_DDR_FDD_LVDS: { + _io_iface->poke8(0x012, 0x10); + } break; + + default: + throw uhd::runtime_error("[ad9361_device_t] NOT IMPLEMENTED"); + } + + _io_iface->poke8(0x013, 0x01); // Set ENSM FDD bit + _io_iface->poke8(0x015, 0x04); // dual synth mode, synth en ctrl en + + /* Default TX attentuation to 10dB on both TX1 and TX2 */ + _io_iface->poke8(0x073, 0x00); + _io_iface->poke8(0x074, 0x00); + _io_iface->poke8(0x075, 0x00); + _io_iface->poke8(0x076, 0x00); + + /* Setup RSSI Measurements */ + _io_iface->poke8(0x150, 0x0E); // RSSI Measurement Duration 0, 1 + _io_iface->poke8(0x151, 0x00); // RSSI Measurement Duration 2, 3 + _io_iface->poke8(0x152, 0xFF); // RSSI Weighted Multiplier 0 + _io_iface->poke8(0x153, 0x00); // RSSI Weighted Multiplier 1 + _io_iface->poke8(0x154, 0x00); // RSSI Weighted Multiplier 2 + _io_iface->poke8(0x155, 0x00); // RSSI Weighted Multiplier 3 + _io_iface->poke8(0x156, 0x00); // RSSI Delay + _io_iface->poke8(0x157, 0x00); // RSSI Wait + _io_iface->poke8(0x158, 0x0D); // RSSI Mode Select + _io_iface->poke8(0x15C, 0x67); // Power Measurement Duration + + /* Turn on the default RX & TX chains. */ + set_active_chains(true, false, false, false); + + /* Set TXers & RXers on (only works in FDD mode) */ + _io_iface->poke8(0x014, 0x21); +} + + +/* This function sets the RX / TX rate between AD9361 and the FPGA, and + * thus determines the interpolation / decimation required in the FPGA to + * achieve the user's requested rate. + * + * This is the only clock setting function that is exposed to the outside. */ +double ad9361_device_t::set_clock_rate(const double req_rate) +{ + boost::lock_guard<boost::recursive_mutex> lock(_mutex); + + if (req_rate > 61.44e6) { + throw uhd::runtime_error("[ad9361_device_t] Requested master clock rate outside range"); + } + + UHD_LOG << boost::format("[ad9361_device_t::set_clock_rate] req_rate=%.10f\n") % req_rate; + + /* UHD has a habit of requesting the same rate like four times when it + * starts up. This prevents that, and any bugs in user code that request + * the same rate over and over. */ + if (freq_is_nearly_equal(req_rate, _req_clock_rate)) { + return _baseband_bw; + } + + /* We must be in the SLEEP / WAIT state to do this. If we aren't already + * there, transition the ENSM to State 0. */ + boost::uint8_t current_state = _io_iface->peek8(0x017) & 0x0F; + switch (current_state) { + case 0x05: + /* We are in the ALERT state. */ + _io_iface->poke8(0x014, 0x21); + boost::this_thread::sleep(boost::posix_time::milliseconds(5)); + _io_iface->poke8(0x014, 0x00); + break; + + case 0x0A: + /* We are in the FDD state. */ + _io_iface->poke8(0x014, 0x00); + break; + + default: + throw uhd::runtime_error("[ad9361_device_t] [set_clock_rate:1] AD9361 in unknown state"); + break; + }; + + /* Store the current chain / antenna selections so that we can restore + * them at the end of this routine; all chains will be enabled from + * within setup_rates for calibration purposes. */ + boost::uint8_t orig_tx_chains = _regs.txfilt & 0xC0; + boost::uint8_t orig_rx_chains = _regs.rxfilt & 0xC0; + + /* Call into the clock configuration / settings function. This is where + * all the hard work gets done. */ + double rate = _setup_rates(req_rate); + + UHD_LOG << boost::format("[ad9361_device_t::set_clock_rate] rate=%.10f\n") % rate; + + /* Transition to the ALERT state and calibrate everything. */ + _io_iface->poke8(0x015, 0x04); //dual synth mode, synth en ctrl en + _io_iface->poke8(0x014, 0x05); //use SPI for TXNRX ctrl, to ALERT, TX on + _io_iface->poke8(0x013, 0x01); //enable ENSM + boost::this_thread::sleep(boost::posix_time::milliseconds(1)); + + _calibrate_synth_charge_pumps(); + + _tune_helper(RX, _rx_freq); + _tune_helper(TX, _tx_freq); + + _program_mixer_gm_subtable(); + _program_gain_table(); + _setup_gain_control(); + _reprogram_gains(); + + _calibrate_baseband_rx_analog_filter(); + _calibrate_baseband_tx_analog_filter(); + _calibrate_rx_TIAs(); + _calibrate_secondary_tx_filter(); + + _setup_adc(); + + _calibrate_tx_quadrature(); + _calibrate_rx_quadrature(); + + // cals done, set PPORT config + switch (_client_params->get_digital_interface_mode()) { + case AD9361_DDR_FDD_LVCMOS: { + _io_iface->poke8(0x012, 0x02); + }break; + + case AD9361_DDR_FDD_LVDS: { + _io_iface->poke8(0x012, 0x10); + }break; + + default: + throw uhd::runtime_error("[ad9361_device_t] NOT IMPLEMENTED"); + } + _io_iface->poke8(0x013, 0x01); // Set ENSM FDD bit + _io_iface->poke8(0x015, 0x04); // dual synth mode, synth en ctrl en + + /* End the function in the same state as the entry state. */ + switch (current_state) { + case 0x05: + /* We are already in ALERT. */ + break; + + case 0x0A: + /* Transition back to FDD, and restore the original antenna + * / chain selections. */ + _regs.txfilt = (_regs.txfilt & 0x3F) | orig_tx_chains; + _regs.rxfilt = (_regs.rxfilt & 0x3F) | orig_rx_chains; + + _io_iface->poke8(0x002, _regs.txfilt); + _io_iface->poke8(0x003, _regs.rxfilt); + _io_iface->poke8(0x014, 0x21); + break; + + default: + throw uhd::runtime_error("[ad9361_device_t] [set_clock_rate:2] AD9361 in unknown state"); + break; + }; + + return rate; +} + + +/* Set which of the four TX / RX chains provided by AD9361 are active. + * + * AD9361 provides two sets of chains, Side A and Side B. Each side + * provides one TX antenna, and one RX antenna. The B200 maintains the USRP + * standard of providing one antenna connection that is both TX & RX, and + * one that is RX-only - for each chain. Thus, the possible antenna and + * chain selections are: + * + * B200 Antenna AD9361 Side AD9361 Chain + * ------------------------------------------------------------------- + * TX / RX1 Side A TX1 (when switched to TX) + * TX / RX1 Side A RX1 (when switched to RX) + * RX1 Side A RX1 + * + * TX / RX2 Side B TX2 (when switched to TX) + * TX / RX2 Side B RX2 (when switched to RX) + * RX2 Side B RX2 + */ +void ad9361_device_t::set_active_chains(bool tx1, bool tx2, bool rx1, bool rx2) +{ + boost::lock_guard<boost::recursive_mutex> lock(_mutex); + + /* Clear out the current active chain settings. */ + _regs.txfilt = _regs.txfilt & 0x3F; + _regs.rxfilt = _regs.rxfilt & 0x3F; + + /* Turn on the different chains based on the passed parameters. */ + if (tx1) { + _regs.txfilt = _regs.txfilt | 0x40; + } + if (tx2) { + _regs.txfilt = _regs.txfilt | 0x80; + } + if (rx1) { + _regs.rxfilt = _regs.rxfilt | 0x40; + } + if (rx2) { + _regs.rxfilt = _regs.rxfilt | 0x80; + } + + /* Check for FDD state */ + boost::uint8_t set_back_to_fdd = 0; + boost::uint8_t ensm_state = _io_iface->peek8(0x017) & 0x0F; + if (ensm_state == 0xA) // FDD + { + /* Put into ALERT state (via the FDD flush state). */ + _io_iface->poke8(0x014, 0x01); + set_back_to_fdd = 1; + } + + /* Wait for FDD flush state to complete (if necessary) */ + while (ensm_state == 0xA || ensm_state == 0xB) + ensm_state = _io_iface->peek8(0x017) & 0x0F; + + /* Turn on / off the chains. */ + _io_iface->poke8(0x002, _regs.txfilt); + _io_iface->poke8(0x003, _regs.rxfilt); + + /* Put back into FDD state if necessary */ + if (set_back_to_fdd) + _io_iface->poke8(0x014, 0x21); +} + +/* Tune the RX or TX frequency. + * + * This is the publicly-accessible tune function. It makes sure the tune + * isn't a redundant request, and if not, passes it on to the class's + * internal tune function. + * + * After tuning, it runs any appropriate calibrations. */ +double ad9361_device_t::tune(direction_t direction, const double value) +{ + boost::lock_guard<boost::recursive_mutex> lock(_mutex); + + if (direction == RX) { + if (freq_is_nearly_equal(value, _req_rx_freq)) { + return _rx_freq; + } + + } else if (direction == TX) { + if (freq_is_nearly_equal(value, _req_tx_freq)) { + return _tx_freq; + } + + } else { + throw uhd::runtime_error("[ad9361_device_t] [tune] INVALID_CODE_PATH"); + } + + /* If we aren't already in the ALERT state, we will need to return to + * the FDD state after tuning. */ + int not_in_alert = 0; + if ((_io_iface->peek8(0x017) & 0x0F) != 5) { + /* Force the device into the ALERT state. */ + not_in_alert = 1; + _io_iface->poke8(0x014, 0x01); + } + + /* Tune the RF VCO! */ + double tune_freq = _tune_helper(direction, value); + + /* Run any necessary calibrations / setups */ + if (direction == RX) { + _program_gain_table(); + } + + /* Update the gain settings. */ + _reprogram_gains(); + + /* Run the calibration algorithms. */ + _calibrate_tx_quadrature(); + _calibrate_rx_quadrature(); + + /* If we were in the FDD state, return it now. */ + if (not_in_alert) { + _io_iface->poke8(0x014, 0x21); + } + + return tune_freq; +} + +/* Set the gain of RX1, RX2, TX1, or TX2. + * + * Note that the 'value' passed to this function is the actual gain value, + * _not_ the gain index. This is the opposite of the eval software's GUI! + * Also note that the RX chains are done in terms of gain, and the TX chains + * are done in terms of attenuation. */ +double ad9361_device_t::set_gain(direction_t direction, chain_t chain, const double value) +{ + boost::lock_guard<boost::recursive_mutex> lock(_mutex); + + if (direction == RX) { + /* Indexing the gain tables requires an offset from the requested + * amount of total gain in dB: + * < 1300MHz: dB + 5 + * >= 1300MHz and < 4000MHz: dB + 3 + * >= 4000MHz and <= 6000MHz: dB + 14 + */ + int gain_offset = 0; + if (_rx_freq < 1300e6) { + gain_offset = 5; + } else if (_rx_freq < 4000e6) { + gain_offset = 3; + } else { + gain_offset = 14; + } + + int gain_index = static_cast<int>(value + gain_offset); + + /* Clip the gain values to the proper min/max gain values. */ + if (gain_index > 76) + gain_index = 76; + if (gain_index < 0) + gain_index = 0; + + if (chain == CHAIN_1) { + _rx1_gain = boost::uint32_t(value); + _io_iface->poke8(0x109, gain_index); + } else { + _rx2_gain = boost::uint32_t(value); + _io_iface->poke8(0x10c, gain_index); + } + + return gain_index - gain_offset; + } else { + /* Setting the below bits causes a change in the TX attenuation word + * to immediately take effect. */ + _io_iface->poke8(0x077, 0x40); + _io_iface->poke8(0x07c, 0x40); + + /* Each gain step is -0.25dB. Calculate the attenuation necessary + * for the requested gain, convert it into gain steps, then write + * the attenuation word. Max gain (so zero attenuation) is 89.75. */ + double atten = AD9361_MAX_GAIN - value; + boost::uint32_t attenreg = boost::uint32_t(atten * 4); + if (chain == CHAIN_1) { + _tx1_gain = boost::uint32_t(value); + _io_iface->poke8(0x073, attenreg & 0xFF); + _io_iface->poke8(0x074, (attenreg >> 8) & 0x01); + } else { + _tx2_gain = boost::uint32_t(value); + _io_iface->poke8(0x075, attenreg & 0xFF); + _io_iface->poke8(0x076, (attenreg >> 8) & 0x01); + } + return AD9361_MAX_GAIN - ((double) (attenreg) / 4); + } +} + +void ad9361_device_t::output_test_tone() +{ + boost::lock_guard<boost::recursive_mutex> lock(_mutex); + /* Output a 480 kHz tone at 800 MHz */ + _io_iface->poke8(0x3F4, 0x0B); + _io_iface->poke8(0x3FC, 0xFF); + _io_iface->poke8(0x3FD, 0xFF); + _io_iface->poke8(0x3FE, 0x3F); +} + +void ad9361_device_t::data_port_loopback(const bool loopback_enabled) +{ + boost::lock_guard<boost::recursive_mutex> lock(_mutex); + _io_iface->poke8(0x3F5, (loopback_enabled ? 0x01 : 0x00)); +} + +}} diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.h b/host/lib/usrp/common/ad9361_driver/ad9361_device.h new file mode 100644 index 000000000..74f16cff9 --- /dev/null +++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.h @@ -0,0 +1,125 @@ +// +// Copyright 2014 Ettus Research LLC +// + +#ifndef INCLUDED_AD9361_DEVICE_H +#define INCLUDED_AD9361_DEVICE_H + +#include <ad9361_client.h> +#include <boost/noncopyable.hpp> +#include <boost/thread/recursive_mutex.hpp> + +namespace uhd { namespace usrp { + +class ad9361_device_t : public boost::noncopyable +{ +public: + enum direction_t { RX, TX }; + enum chain_t { CHAIN_1, CHAIN_2 }; + + ad9361_device_t(ad9361_params::sptr client, ad9361_io::sptr io_iface) : + _client_params(client), _io_iface(io_iface) {} + + /* Initialize the AD9361 codec. */ + void initialize(); + + /* This function sets the RX / TX rate between AD9361 and the FPGA, and + * thus determines the interpolation / decimation required in the FPGA to + * achieve the user's requested rate. + */ + double set_clock_rate(const double req_rate); + + /* Set which of the four TX / RX chains provided by AD9361 are active. + * + * AD9361 provides two sets of chains, Side A and Side B. Each side + * provides one TX antenna, and one RX antenna. The B200 maintains the USRP + * standard of providing one antenna connection that is both TX & RX, and + * one that is RX-only - for each chain. Thus, the possible antenna and + * chain selections are: + * + */ + void set_active_chains(bool tx1, bool tx2, bool rx1, bool rx2); + + /* Tune the RX or TX frequency. + * + * This is the publicly-accessible tune function. It makes sure the tune + * isn't a redundant request, and if not, passes it on to the class's + * internal tune function. + * + * After tuning, it runs any appropriate calibrations. */ + double tune(direction_t direction, const double value); + + /* Set the gain of RX1, RX2, TX1, or TX2. + * + * Note that the 'value' passed to this function is the actual gain value, + * _not_ the gain index. This is the opposite of the eval software's GUI! + * Also note that the RX chains are done in terms of gain, and the TX chains + * are done in terms of attenuation. */ + double set_gain(direction_t direction, chain_t chain, const double value); + + /* Make AD9361 output its test tone. */ + void output_test_tone(); + + /* Turn on/off AD9361's TX port --> RX port loopback. */ + void data_port_loopback(const bool loopback_enabled); + + //Constants + static const double AD9361_MAX_GAIN; + static const double AD9361_MAX_CLOCK_RATE; + +private: //Methods + void _program_fir_filter(direction_t direction, int num_taps, boost::uint16_t *coeffs); + void _setup_tx_fir(size_t num_taps); + void _setup_rx_fir(size_t num_taps); + void _calibrate_lock_bbpll(); + void _calibrate_synth_charge_pumps(); + double _calibrate_baseband_rx_analog_filter(); + double _calibrate_baseband_tx_analog_filter(); + void _calibrate_secondary_tx_filter(); + void _calibrate_rx_TIAs(); + void _setup_adc(); + void _calibrate_baseband_dc_offset(); + void _calibrate_rf_dc_offset(); + void _calibrate_rx_quadrature(); + void _tx_quadrature_cal_routine(); + void _calibrate_tx_quadrature(); + void _program_mixer_gm_subtable(); + void _program_gain_table(); + void _setup_gain_control(); + void _setup_synth(direction_t direction, double vcorate); + double _tune_bbvco(const double rate); + void _reprogram_gains(); + double _tune_helper(direction_t direction, const double value); + double _setup_rates(const double rate); + +private: //Members + typedef struct { + boost::uint8_t vcodivs; + boost::uint8_t inputsel; + boost::uint8_t rxfilt; + boost::uint8_t txfilt; + boost::uint8_t bbpll; + boost::uint8_t bbftune_config; + boost::uint8_t bbftune_mode; + } chip_regs_t; + + //Interfaces + ad9361_params::sptr _client_params; + ad9361_io::sptr _io_iface; + //Intermediate state + double _rx_freq, _tx_freq, _req_rx_freq, _req_tx_freq; + double _baseband_bw, _bbpll_freq, _adcclock_freq; + double _req_clock_rate, _req_coreclk; + boost::uint16_t _rx_bbf_tunediv; + boost::uint8_t _curr_gain_table; + boost::uint32_t _rx1_gain, _rx2_gain, _tx1_gain, _tx2_gain; + boost::int32_t _tfir_factor; + //Register soft-copies + chip_regs_t _regs; + //Synchronization + boost::recursive_mutex _mutex; +}; + +}} //namespace + +#endif /* INCLUDED_AD9361_DEVICE_H */ diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_filter_taps.h b/host/lib/usrp/common/ad9361_driver/ad9361_filter_taps.h new file mode 100644 index 000000000..4059ad7ee --- /dev/null +++ b/host/lib/usrp/common/ad9361_driver/ad9361_filter_taps.h @@ -0,0 +1,73 @@ +// +// Copyright 2014 Ettus Research LLC +// + +#ifndef INCLUDED_AD9361_FILTER_TAPS_HPP +#define INCLUDED_AD9361_FILTER_TAPS_HPP + +#include <boost/cstdint.hpp> + +/* A default 128-tap filter that can be used for generic circumstances. */ +/* static uint16_t default_128tap_coeffs[] = { + 0x0001,0xfff1,0xffcf,0xffc0,0xffe8,0x0020,0x001a,0xffe3, + 0xffe1,0x001f,0x0028,0xffdf,0xffcc,0x0024,0x0043,0xffdb, + 0xffac,0x0026,0x0068,0xffdb,0xff80,0x0022,0x009a,0xffe2, + 0xff47,0x0017,0x00db,0xfff3,0xfeff,0xffff,0x012b,0x0013, + 0xfea5,0xffd7,0x0190,0x0046,0xfe35,0xff97,0x020e,0x0095, + 0xfda7,0xff36,0x02ae,0x010d,0xfcf0,0xfea1,0x0383,0x01c6, + 0xfbf3,0xfdb6,0x04b7,0x02f8,0xfa6d,0xfc1a,0x06be,0x0541, + 0xf787,0xf898,0x0b60,0x0b6d,0xee88,0xea40,0x2786,0x7209 +}; +*/ + +/* The below pair of filters is from ADI and "optimized for a 10MHz LTE application". */ +/* +static uint16_t lte10mhz_rx_coeffs[] = { + 0xffe2,0x0042,0x0024,0x0095,0x0056,0x004d,0xffcf,0xffb7, + 0xffb1,0x0019,0x0059,0x006a,0x0004,0xff9d,0xff72,0xffd4, + 0x0063,0x00b7,0x0062,0xffac,0xff21,0xff59,0x0032,0x0101, + 0x00f8,0x0008,0xfeea,0xfeac,0xffa3,0x0117,0x01b5,0x00d0, + 0xff05,0xfdea,0xfe9e,0x00ba,0x026f,0x0215,0xffb5,0xfd4a, + 0xfd18,0xffa0,0x02de,0x03dc,0x0155,0xfd2a,0xfb0d,0xfd54, + 0x0287,0x062f,0x048a,0xfe37,0xf862,0xf8c1,0x004d,0x0963, + 0x0b88,0x02a4,0xf3e7,0xebdd,0xf5f8,0x1366,0x3830,0x518b +}; + +static uint16_t lte10mhz_tx_coeffs[] = { + 0xfffb,0x0000,0x0004,0x0017,0x0024,0x0028,0x0013,0xfff3, + 0xffdc,0xffe5,0x000b,0x0030,0x002e,0xfffe,0xffc4,0xffb8, + 0xfff0,0x0045,0x0068,0x002b,0xffb6,0xff72,0xffad,0x0047, + 0x00b8,0x0088,0xffc8,0xff1c,0xff33,0x001a,0x0110,0x0124, + 0x0019,0xfec8,0xfe74,0xff9a,0x0156,0x0208,0x00d3,0xfe9b, + 0xfd68,0xfe96,0x015d,0x033f,0x0236,0xfecd,0xfc00,0xfcb5, + 0x00d7,0x04e5,0x04cc,0xffd5,0xf9fe,0xf8fb,0xfef2,0x078c, + 0x0aae,0x036d,0xf5c0,0xed89,0xf685,0x12af,0x36a4,0x4faa +}; +*/ + + +/* 127 tap Halfband designed with: round(2^16 * halfgen4(0.9/4,32)) (center tap tweaked to 32767) */ +static boost::int16_t hb127_coeffs[] = { + -0,0,1,-0,-2,0,3,-0,-5,0,8,-0,-11,0,17,-0,-24,0,33,-0,-45,0,61,-0,-80,0,104,-0,-134,0,169,-0, + -213,0,264,-0,-327,0,401,-0,-489,0,595,-0,-724,0,880,-0,-1075,0,1323,-0,-1652,0,2114,-0,-2819,0,4056,-0,-6883,0,20837,32767, + 20837,0,-6883,-0,4056,0,-2819,-0,2114,0,-1652,-0,1323,0,-1075,-0,880,0,-724,-0,595,0,-489,-0,401,0,-327,-0,264,0,-213,-0, + 169,0,-134,-0,104,0,-80,-0,61,0,-45,-0,33,0,-24,-0,17,0,-11,-0,8,0,-5,-0,3,0,-2,-0,1,0,-0, 0 }; + +/* 95 tap Halfband designed with: round(2^16 * halfgen4(0.9/4,24)) (center tap tweaked to 32767) */ +static boost::int16_t hb95_coeffs[] = { + -4,0,8,-0,-14,0,23,-0,-36,0,52,-0,-75,0,104,-0,-140,0,186,-0,-243,0,314,-0,-400,0,505,-0,-634,0,793,-0, + -993,0,1247,-0,-1585,0,2056,-0,-2773,0,4022,-0,-6862,0,20830,32767,20830,0,-6862,-0,4022,0,-2773,-0,2056,0,-1585,-0,1247,0,-993,-0, + 793,0,-634,-0,505,0,-400,-0,314,0,-243,-0,186,0,-140,-0,104,0,-75,-0,52,0,-36,-0,23,0,-14,-0,8,0,-4,0}; + +/* 63 tap Halfband designed with: round(2^16 * halfgen4(0.9/4,16)) (center tap tweaked to 32767) */ +static boost::int16_t hb63_coeffs[] = { + -58,0,83,-0,-127,0,185,-0,-262,0,361,-0,-488,0,648,-0,-853,0,1117,-0,-1466,0,1954,-0,-2689,0,3960,-0,-6825,0,20818,32767, + 20818,0,-6825,-0,3960,0,-2689,-0,1954,0,-1466,-0,1117,0,-853,-0,648,0,-488,-0,361,0,-262,-0,185,0,-127,-0,83,0,-58,0}; + +/* 47 tap Halfband designed with: round(2^16 * halfgen4(0.85/4,12)) (center tap tweaked to 32767) */ +static boost::int16_t hb47_coeffs[] = { + -50,0,98,-0,-181,0,307,-0,-489,0,747,-0,-1109,0,1628,-0,-2413,0,3750,-0,-6693,0,20773,32767,20773,0,-6693,-0,3750,0,-2413,-0, + 1628,0,-1109,-0,747,0,-489,-0,307,0,-181,-0,98,0,-50,0}; + + +#endif // INCLUDED_AD9361_FILTER_TAPS_HPP diff --git a/firmware/fx3/ad9361/lib/ad9361_gain_tables.h b/host/lib/usrp/common/ad9361_driver/ad9361_gain_tables.h index 58dcbeb65..786029d6e 100644 --- a/firmware/fx3/ad9361/lib/ad9361_gain_tables.h +++ b/host/lib/usrp/common/ad9361_driver/ad9361_gain_tables.h @@ -1,11 +1,13 @@ // -// Copyright 2013-2014 Ettus Research LLC +// Copyright 2014 Ettus Research LLC // #ifndef INCLUDED_AD9361_GAIN_TABLES_HPP #define INCLUDED_AD9361_GAIN_TABLES_HPP -uint8_t gain_table_sub_1300mhz[77][5] = { {0,0x00,0x00,0x20,1}, +#include <boost/cstdint.hpp> + +boost::uint8_t gain_table_sub_1300mhz[77][5] = { {0,0x00,0x00,0x20,1}, {1,0x00,0x00,0x00,0}, {2,0x00,0x00,0x00,0}, {3,0x00,0x01,0x00,0}, {4,0x00,0x02,0x00,0}, {5,0x00,0x03,0x00,0}, {6,0x00,0x04,0x00,0}, {7,0x00,0x05,0x00,0}, {8,0x01,0x03,0x20,1}, {9,0x01,0x04,0x00,0}, @@ -34,7 +36,7 @@ uint8_t gain_table_sub_1300mhz[77][5] = { {0,0x00,0x00,0x20,1}, {76,0x6F,0x38,0x20,1}}; -uint8_t gain_table_1300mhz_to_4000mhz[77][5] = { {0,0x00,0x00,0x20,1}, +boost::uint8_t gain_table_1300mhz_to_4000mhz[77][5] = { {0,0x00,0x00,0x20,1}, {1,0x00,0x00,0x00,0}, {2,0x00,0x00,0x00,0}, {3,0x00,0x01,0x00,0}, {4,0x00,0x02,0x00,0}, {5,0x00,0x03,0x00,0}, {6,0x00,0x04,0x00,0}, {7,0x00,0x05,0x00,0}, {8,0x01,0x03,0x20,1}, {9,0x01,0x04,0x00,0}, @@ -63,7 +65,7 @@ uint8_t gain_table_1300mhz_to_4000mhz[77][5] = { {0,0x00,0x00,0x20,1}, {76,0x6F,0x38,0x20,1}}; -uint8_t gain_table_4000mhz_to_6000mhz[77][5] = { {0,0x00,0x00,0x20,1}, +boost::uint8_t gain_table_4000mhz_to_6000mhz[77][5] = { {0,0x00,0x00,0x20,1}, {1,0x00,0x00,0x00,0}, {2,0x00,0x00,0x00,0}, {3,0x00,0x00,0x00,0}, {4,0x00,0x00,0x00,0}, {5,0x00,0x01,0x00,0}, {6,0x00,0x02,0x00,0}, {7,0x00,0x03,0x00,0}, {8,0x01,0x01,0x20,1}, {9,0x01,0x02,0x00,0}, diff --git a/firmware/fx3/ad9361/lib/ad9361_synth_lut.h b/host/lib/usrp/common/ad9361_driver/ad9361_synth_lut.h index 79214526d..cb320e1f4 100644 --- a/firmware/fx3/ad9361/lib/ad9361_synth_lut.h +++ b/host/lib/usrp/common/ad9361_driver/ad9361_synth_lut.h @@ -1,5 +1,5 @@ // -// Copyright 2013-2014 Ettus Research LLC +// Copyright 2014 Ettus Research LLC // #ifndef INCLUDED_AD9361_SYNTH_LUT_HPP diff --git a/host/lib/usrp/common/ad9361_transaction.h b/host/lib/usrp/common/ad9361_transaction.h deleted file mode 100644 index 693f32e41..000000000 --- a/host/lib/usrp/common/ad9361_transaction.h +++ /dev/null @@ -1,109 +0,0 @@ -// -// Copyright 2013 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see <http://www.gnu.org/licenses/>. -// - -#ifndef INCLUDED_AD9361_TRANSACTION_H -#define INCLUDED_AD9361_TRANSACTION_H - -#include <stdint.h> - -#ifdef __cplusplus -extern "C" { -#endif - -//various constants -#define AD9361_TRANSACTION_VERSION 0x4 -#define AD9361_DISPATCH_PACKET_SIZE 64 - -//action types -#define AD9361_ACTION_ECHO 0 -#define AD9361_ACTION_INIT 1 -#define AD9361_ACTION_SET_RX1_GAIN 2 -#define AD9361_ACTION_SET_TX1_GAIN 3 -#define AD9361_ACTION_SET_RX2_GAIN 4 -#define AD9361_ACTION_SET_TX2_GAIN 5 -#define AD9361_ACTION_SET_RX_FREQ 6 -#define AD9361_ACTION_SET_TX_FREQ 7 -#define AD9361_ACTION_SET_CODEC_LOOP 8 -#define AD9361_ACTION_SET_CLOCK_RATE 9 -#define AD9361_ACTION_SET_ACTIVE_CHAINS 10 - -typedef union -{ - double d; - uint32_t x[2]; -} ad9361_double_union_t; - -static inline void ad9361_double_pack(const double input, uint32_t output[2]) -{ - ad9361_double_union_t p = {}; - p.d = input; - output[0] = p.x[0]; - output[1] = p.x[1]; -} - -static inline double ad9361_double_unpack(const uint32_t input[2]) -{ - ad9361_double_union_t p = {}; - p.x[0] = input[0]; - p.x[1] = input[1]; - return p.d; -} - -typedef struct -{ - //version is expected to be AD9361_TRANSACTION_VERSION - //check otherwise for compatibility - uint32_t version; - - //sequence number - increment every call for sanity - uint32_t sequence; - - //action tells us what to do, see AD9361_ACTION_* - uint32_t action; - - union - { - //enable mask for chains - uint32_t enable_mask; - - //true to enable codec internal loopback - uint32_t codec_loop; - - //freq holds request LO freq and result from tune - uint32_t freq[2]; - - //gain holds request gain and result from action - uint32_t gain[2]; - - //rate holds request clock rate and result from action - uint32_t rate[2]; - - } value; - - //error message comes back as a reply - - //set to null string for no error \0 - char error_msg[]; - -} ad9361_transaction_t; - -#define AD9361_TRANSACTION_MAX_ERROR_MSG (AD9361_DISPATCH_PACKET_SIZE - (sizeof(ad9361_transaction_t)-4)-1) // -4 for 'error_msg' alignment padding, -1 for terminating \0 - -#ifdef __cplusplus -} -#endif - -#endif /* INCLUDED_AD9361_TRANSACTION_H */ diff --git a/host/lib/usrp/common/adf4001_ctrl.cpp b/host/lib/usrp/common/adf4001_ctrl.cpp index 46171c7ce..a7510c272 100644 --- a/host/lib/usrp/common/adf4001_ctrl.cpp +++ b/host/lib/usrp/common/adf4001_ctrl.cpp @@ -93,7 +93,7 @@ boost::uint32_t adf4001_regs_t::get_reg(boost::uint8_t addr) { } -adf4001_ctrl::adf4001_ctrl(spi_core_3000::sptr _spi, int slaveno): +adf4001_ctrl::adf4001_ctrl(uhd::spi_iface::sptr _spi, int slaveno): spi_iface(_spi), slaveno(slaveno) { diff --git a/host/lib/usrp/common/adf4001_ctrl.hpp b/host/lib/usrp/common/adf4001_ctrl.hpp index a16cff3fa..9ea3caf1a 100644 --- a/host/lib/usrp/common/adf4001_ctrl.hpp +++ b/host/lib/usrp/common/adf4001_ctrl.hpp @@ -123,12 +123,11 @@ public: class adf4001_ctrl { public: - - adf4001_ctrl(spi_core_3000::sptr _spi, int slaveno); + adf4001_ctrl(uhd::spi_iface::sptr _spi, int slaveno); void set_lock_to_ext_ref(bool external); private: - spi_core_3000::sptr spi_iface; + uhd::spi_iface::sptr spi_iface; int slaveno; spi_config_t spi_config; adf4001_regs_t adf4001_regs; diff --git a/host/lib/usrp/e100/e100_impl.cpp b/host/lib/usrp/e100/e100_impl.cpp index b49ba64a2..e59df7708 100644 --- a/host/lib/usrp/e100/e100_impl.cpp +++ b/host/lib/usrp/e100/e100_impl.cpp @@ -1,5 +1,5 @@ // -// Copyright 2010-2012 Ettus Research LLC +// Copyright 2010-2012,2014 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -96,7 +96,7 @@ static device::sptr e100_make(const device_addr_t &device_addr){ } UHD_STATIC_BLOCK(register_e100_device){ - device::register_device(&e100_find, &e100_make); + device::register_device(&e100_find, &e100_make, device::USRP); } static const uhd::dict<std::string, std::string> model_to_fpga_file_name = boost::assign::map_list_of @@ -109,6 +109,7 @@ static const uhd::dict<std::string, std::string> model_to_fpga_file_name = boost **********************************************************************/ e100_impl::e100_impl(const uhd::device_addr_t &device_addr){ _tree = property_tree::make(); + _type = device::USRP; //read the eeprom so we can determine the hardware _dev_i2c_iface = e100_ctrl::make_dev_i2c_iface(E100_I2C_DEV_NODE); diff --git a/host/lib/usrp/multi_usrp.cpp b/host/lib/usrp/multi_usrp.cpp index c13d3efba..388cf03fa 100644 --- a/host/lib/usrp/multi_usrp.cpp +++ b/host/lib/usrp/multi_usrp.cpp @@ -246,7 +246,7 @@ static double derive_freq_from_xx_subdev_and_dsp( class multi_usrp_impl : public multi_usrp{ public: multi_usrp_impl(const device_addr_t &addr){ - _dev = device::make(addr); + _dev = device::make(addr, device::USRP); _tree = _dev->get_tree(); } diff --git a/host/lib/usrp/usrp1/usrp1_impl.cpp b/host/lib/usrp/usrp1/usrp1_impl.cpp index 0ba2e1e4a..709092e42 100644 --- a/host/lib/usrp/usrp1/usrp1_impl.cpp +++ b/host/lib/usrp/usrp1/usrp1_impl.cpp @@ -1,5 +1,5 @@ // -// Copyright 2010-2012 Ettus Research LLC +// Copyright 2010-2012,2014 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -139,7 +139,7 @@ static device::sptr usrp1_make(const device_addr_t &device_addr){ } UHD_STATIC_BLOCK(register_usrp1_device){ - device::register_device(&usrp1_find, &usrp1_make); + device::register_device(&usrp1_find, &usrp1_make, device::USRP); } /*********************************************************************** @@ -147,6 +147,7 @@ UHD_STATIC_BLOCK(register_usrp1_device){ **********************************************************************/ usrp1_impl::usrp1_impl(const device_addr_t &device_addr){ UHD_MSG(status) << "Opening a USRP1 device..." << std::endl; + _type = device::USRP; //extract the FPGA path for the USRP1 std::string usrp1_fpga_image = find_image_path( diff --git a/host/lib/usrp/usrp2/usrp2_impl.cpp b/host/lib/usrp/usrp2/usrp2_impl.cpp index d96a8ab7d..93885fbd3 100644 --- a/host/lib/usrp/usrp2/usrp2_impl.cpp +++ b/host/lib/usrp/usrp2/usrp2_impl.cpp @@ -1,5 +1,5 @@ // -// Copyright 2010-2012 Ettus Research LLC +// Copyright 2010-2012,2014 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -200,7 +200,7 @@ static device::sptr usrp2_make(const device_addr_t &device_addr){ } UHD_STATIC_BLOCK(register_usrp2_device){ - device::register_device(&usrp2_find, &usrp2_make); + device::register_device(&usrp2_find, &usrp2_make, device::USRP); } /*********************************************************************** @@ -368,6 +368,7 @@ usrp2_impl::usrp2_impl(const device_addr_t &_device_addr){ // create controller objects and initialize the properties tree //////////////////////////////////////////////////////////////////// _tree = property_tree::make(); + _type = device::USRP; _tree->create<std::string>("/name").set("USRP2 / N-Series Device"); for (size_t mbi = 0; mbi < device_args.size(); mbi++){ diff --git a/host/lib/usrp/x300/x300_impl.cpp b/host/lib/usrp/x300/x300_impl.cpp index 1b651065d..d5eacc3ea 100644 --- a/host/lib/usrp/x300/x300_impl.cpp +++ b/host/lib/usrp/x300/x300_impl.cpp @@ -326,7 +326,7 @@ static device::sptr x300_make(const device_addr_t &device_addr) UHD_STATIC_BLOCK(register_x300_device) { - device::register_device(&x300_find, &x300_make); + device::register_device(&x300_find, &x300_make, device::USRP); } static void x300_load_fw(wb_iface::sptr fw_reg_ctrl, const std::string &file_name) @@ -355,6 +355,7 @@ static void x300_load_fw(wb_iface::sptr fw_reg_ctrl, const std::string &file_nam x300_impl::x300_impl(const uhd::device_addr_t &dev_addr) { UHD_MSG(status) << "X300 initialization sequence..." << std::endl; + _type = device::USRP; _async_md.reset(new async_md_type(1000/*messages deep*/)); _tree = uhd::property_tree::make(); _tree->create<std::string>("/name").set("X-Series Device"); diff --git a/host/lib/usrp_clock/CMakeLists.txt b/host/lib/usrp_clock/CMakeLists.txt new file mode 100644 index 000000000..8a58aa9ac --- /dev/null +++ b/host/lib/usrp_clock/CMakeLists.txt @@ -0,0 +1,26 @@ +# +# Copyright 2011-2014 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +######################################################################## +# This file included, use CMake directory variables +######################################################################## + +LIBUHD_APPEND_SOURCES( + ${CMAKE_CURRENT_SOURCE_DIR}/multi_usrp_clock.cpp +) + +INCLUDE_SUBDIRECTORY(octoclock) diff --git a/host/lib/usrp_clock/multi_usrp_clock.cpp b/host/lib/usrp_clock/multi_usrp_clock.cpp new file mode 100644 index 000000000..77489e13b --- /dev/null +++ b/host/lib/usrp_clock/multi_usrp_clock.cpp @@ -0,0 +1,93 @@ +// +// Copyright 2010-2013 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#include <uhd/property_tree.hpp> +#include <uhd/usrp_clock/multi_usrp_clock.hpp> +#include <uhd/usrp_clock/octoclock_eeprom.hpp> + +#include <uhd/utils/msg.hpp> +#include <uhd/exception.hpp> +#include <uhd/utils/log.hpp> +#include <boost/assign/list_of.hpp> +#include <boost/foreach.hpp> +#include <boost/format.hpp> + +using namespace uhd; +using namespace uhd::usrp_clock; + +/*********************************************************************** + * Multi USRP Clock implementation + **********************************************************************/ +class multi_usrp_clock_impl : public multi_usrp_clock{ +public: + multi_usrp_clock_impl(const device_addr_t &addr){ + _dev = device::make(addr, device::CLOCK); + _tree = _dev->get_tree(); + } + + device::sptr get_device(void){ + return _dev; + } + + std::string get_pp_string(void){ + std::string buff = str(boost::format("%s USRP Clock Device\n") + % ((get_num_boards() > 1) ? "Multi" : "Single") + ); + for(size_t i = 0; i < get_num_boards(); i++){ + buff += str(boost::format(" Board %s\n") % i); + buff += str(boost::format(" Reference: %s\n") + % (get_sensor("using_ref", i).value) + ); + } + + return buff; + } + + size_t get_num_boards(void){ + return _tree->list("/mboards").size(); + } + + boost::uint32_t get_time(size_t board){ + std::string board_str = str(boost::format("/mboards/%d") % board); + + return _tree->access<boost::uint32_t>(board_str / "time").get(); + } + + sensor_value_t get_sensor(const std::string &name, size_t board){ + std::string board_str = str(boost::format("/mboards/%d") % board); + + return _tree->access<sensor_value_t>(board_str / "sensors" / name).get(); + } + + std::vector<std::string> get_sensor_names(size_t board){ + std::string board_str = str(boost::format("/mboards/%d") % board); + + return _tree->list(board_str / "sensors"); + } + +private: + device::sptr _dev; + property_tree::sptr _tree; +}; + +/*********************************************************************** + * Multi USRP Clock factory function + **********************************************************************/ +multi_usrp_clock::sptr multi_usrp_clock::make(const device_addr_t &dev_addr){ + UHD_LOG << "multi_usrp_clock::make with args " << dev_addr.to_pp_string() << std::endl; + return sptr(new multi_usrp_clock_impl(dev_addr)); +} diff --git a/host/lib/usrp_clock/octoclock/CMakeLists.txt b/host/lib/usrp_clock/octoclock/CMakeLists.txt new file mode 100644 index 000000000..e363bb9da --- /dev/null +++ b/host/lib/usrp_clock/octoclock/CMakeLists.txt @@ -0,0 +1,33 @@ +# +# Copyright 2011-2014 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +######################################################################## +# This file included, use CMake directory variables +######################################################################## + +######################################################################## +# Conditionally configure the OctoClock support +######################################################################## +LIBUHD_REGISTER_COMPONENT("OctoClock" ENABLE_OCTOCLOCK ON "ENABLE_LIBUHD" OFF) + +IF(ENABLE_OCTOCLOCK) + LIBUHD_APPEND_SOURCES( + ${CMAKE_CURRENT_SOURCE_DIR}/octoclock_eeprom.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/octoclock_impl.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/octoclock_uart.cpp + ) +ENDIF(ENABLE_OCTOCLOCK) diff --git a/host/lib/usrp_clock/octoclock/common.h b/host/lib/usrp_clock/octoclock/common.h new file mode 100644 index 000000000..96acbb30f --- /dev/null +++ b/host/lib/usrp_clock/octoclock/common.h @@ -0,0 +1,149 @@ +/* + * Copyright 2014 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _OCTOCLOCK_COMMON_H_ +#define _OCTOCLOCK_COMMON_H_ + +#include <stdint.h> + +/* + * C++ macros used for code cleanliness and extern "C" declaration. + */ +#ifdef __cplusplus + +#define UHD_OCTOCLOCK_SEND_AND_RECV(xport, pkt_code, pkt_out, len, data) pkt_out.proto_ver = OCTOCLOCK_FW_COMPAT_NUM; \ + pkt_out.code = pkt_code; \ + xport->send(boost::asio::buffer(&pkt_out, sizeof(octoclock_packet_t))); \ + len = xport->recv(boost::asio::buffer(data), 2); + +#define UHD_OCTOCLOCK_PACKET_MATCHES(pkt_code, pkt_out, pkt_in, len) (len > offsetof(octoclock_packet_t, data) and \ + pkt_in->sequence == pkt_out.sequence and \ + pkt_in->code == pkt_code) + +extern "C" { +#endif + +/* + * This code is used by both the C firmware and C++ host driver, so + * only valid C code should go in this section. + */ + +//These values are placed in the octoclock_packet_t.proto_ver field +#define OCTOCLOCK_BOOTLOADER_PROTO_VER 1234 +#define OCTOCLOCK_FW_COMPAT_NUM 2 + +//UDP ports assigned for different tasks +#define OCTOCLOCK_UDP_CTRL_PORT 50000 +#define OCTOCLOCK_UDP_GPSDO_PORT 50001 +#define OCTOCLOCK_UDP_FW_PORT 50002 +#define OCTOCLOCK_UDP_EEPROM_PORT 50003 + +typedef enum { + NO_CODE, + + OCTOCLOCK_QUERY_CMD, + OCTOCLOCK_QUERY_ACK, + + SEND_EEPROM_CMD, + SEND_EEPROM_ACK, + BURN_EEPROM_CMD, + BURN_EEPROM_SUCCESS_ACK, + BURN_EEPROM_FAILURE_ACK, + CLEAR_EEPROM_CMD, + CLEAR_EEPROM_ACK, + + SEND_STATE_CMD, + SEND_STATE_ACK, + + RESET_CMD, + RESET_ACK, + + HOST_SEND_TO_GPSDO_CMD, + HOST_SEND_TO_GPSDO_ACK, + SEND_POOLSIZE_CMD, + SEND_POOLSIZE_ACK, + SEND_CACHE_STATE_CMD, + SEND_CACHE_STATE_ACK, + SEND_GPSDO_CACHE_CMD, + SEND_GPSDO_CACHE_ACK, + + PREPARE_FW_BURN_CMD, + FW_BURN_READY_ACK, + FILE_TRANSFER_CMD, + FILE_TRANSFER_ACK, + READ_FW_CMD, + READ_FW_ACK, + FINALIZE_BURNING_CMD, + FINALIZE_BURNING_ACK, +} packet_code_t; + +typedef enum { + NO_REF, + INTERNAL, + EXTERNAL +} ref_t; + +typedef enum { + UP, + DOWN +} switch_pos_t; + +#pragma pack(push,1) + +// Structure of values in EEPROM, starting in location 0 +typedef struct { + uint8_t mac_addr[6]; + uint32_t ip_addr; + uint32_t dr_addr; + uint32_t netmask; + uint8_t serial[10]; + uint8_t name[10]; + uint8_t revision; +} octoclock_fw_eeprom_t; + +typedef struct { + uint8_t external_detected; + uint8_t gps_detected; + uint8_t which_ref; + uint8_t switch_pos; +} octoclock_state_t; + +typedef struct { + uint8_t num_wraps; + uint8_t pos; +} gpsdo_cache_state_t; + +typedef struct { + uint32_t proto_ver; + uint32_t sequence; + uint8_t code; + union { + uint16_t len; + gpsdo_cache_state_t state; + uint16_t poolsize; + uint16_t addr; + }; + uint8_t data[256]; +} octoclock_packet_t; + +#pragma pack(pop) + +#ifdef __cplusplus +} +#endif + +#endif /* _OCTOCLOCK_COMMON_H_ */ diff --git a/host/lib/usrp_clock/octoclock/octoclock_eeprom.cpp b/host/lib/usrp_clock/octoclock/octoclock_eeprom.cpp new file mode 100644 index 000000000..6d54cac70 --- /dev/null +++ b/host/lib/usrp_clock/octoclock/octoclock_eeprom.cpp @@ -0,0 +1,184 @@ +// +// Copyright 2014 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#include <uhd/exception.hpp> +#include <uhd/usrp_clock/octoclock_eeprom.hpp> +#include <uhd/transport/udp_simple.hpp> +#include <uhd/usrp/mboard_eeprom.hpp> +#include <uhd/types/mac_addr.hpp> +#include <uhd/utils/byteswap.hpp> +#include <boost/assign/list_of.hpp> +#include <boost/asio.hpp> +#include <boost/lexical_cast.hpp> +#include <boost/foreach.hpp> + +#include <iostream> + +#include "common.h" + +typedef boost::asio::ip::address_v4 ip_v4; + +using namespace uhd; +using namespace uhd::usrp_clock; +using namespace uhd::transport; + +/*********************************************************************** + * Utility functions + **********************************************************************/ + +//! A wrapper around std::copy that takes ranges instead of iterators. +template<typename RangeSrc, typename RangeDst> inline +void byte_copy(const RangeSrc &src, RangeDst &dst){ + std::copy(boost::begin(src), boost::end(src), boost::begin(dst)); +} + +//! create a string from a byte vector, return empty if invalid ascii +static const std::string bytes_to_string(const byte_vector_t &bytes){ + std::string out; + BOOST_FOREACH(boost::uint8_t byte, bytes){ + if (byte < 32 or byte > 127) return out; + out += byte; + } + return out; +} + +/*********************************************************************** + * Implementation + **********************************************************************/ +void octoclock_eeprom_t::_load(){ + boost::uint32_t octoclock_data[udp_simple::mtu]; + const octoclock_packet_t *pkt_in = reinterpret_cast<const octoclock_packet_t*>(octoclock_data); + const octoclock_fw_eeprom_t *eeprom_in = reinterpret_cast<const octoclock_fw_eeprom_t*>(pkt_in->data); + + octoclock_packet_t pkt_out; + pkt_out.sequence = uhd::htonx<boost::uint32_t>(std::rand()); + size_t len = 0; + + UHD_OCTOCLOCK_SEND_AND_RECV(xport, SEND_EEPROM_CMD, pkt_out, len, octoclock_data); + if(UHD_OCTOCLOCK_PACKET_MATCHES(SEND_EEPROM_ACK, pkt_out, pkt_in, len)){ + //MAC address + byte_vector_t mac_bytes(eeprom_in->mac_addr, eeprom_in->mac_addr+6); + (*this)["mac-addr"] = mac_addr_t::from_bytes(mac_bytes).to_string(); + + //IP address + boost::uint32_t ip_addr = uhd::htonx<boost::uint32_t>(eeprom_in->ip_addr); + ip_v4::bytes_type ip_addr_bytes; + memcpy(&ip_addr_bytes, &ip_addr, 4); + (*this)["ip-addr"] = ip_v4(ip_addr_bytes).to_string(); + + //Default router + boost::uint32_t dr_addr = uhd::htonx<boost::uint32_t>(eeprom_in->dr_addr); + ip_v4::bytes_type dr_addr_bytes; + memcpy(&dr_addr_bytes, &dr_addr, 4); + (*this)["gateway"] = ip_v4(dr_addr_bytes).to_string(); + + //Netmask + boost::uint32_t netmask = uhd::htonx<boost::uint32_t>(eeprom_in->netmask); + ip_v4::bytes_type netmask_bytes; + memcpy(&netmask_bytes, &netmask, 4); + (*this)["netmask"] = ip_v4(netmask_bytes).to_string(); + + //Serial + std::string raw_serial((char*)eeprom_in->serial, 10); + byte_vector_t serial_bytes(raw_serial.begin(), raw_serial.end()); + (*this)["serial"] = bytes_to_string(serial_bytes); + + //Name + std::string raw_name((char*)eeprom_in->name, 10); + byte_vector_t name_bytes(raw_name.begin(), raw_name.end()); + (*this)["name"] = bytes_to_string(name_bytes); + + //Revision + (*this)["revision"] = boost::lexical_cast<std::string>(int(eeprom_in->revision)); + } + else throw uhd::runtime_error("Error loading OctoClock EEPROM."); +} + +void octoclock_eeprom_t::_store() const { + boost::uint32_t octoclock_data[udp_simple::mtu]; + const octoclock_packet_t *pkt_in = reinterpret_cast<const octoclock_packet_t *>(octoclock_data); + + octoclock_packet_t pkt_out; + pkt_out.sequence = uhd::htonx<boost::uint32_t>(std::rand()); + pkt_out.len = sizeof(octoclock_fw_eeprom_t); + size_t len = 0; + + octoclock_fw_eeprom_t *eeprom_out = reinterpret_cast<octoclock_fw_eeprom_t *>(&pkt_out.data); + memset(eeprom_out, 0xFF, sizeof(octoclock_fw_eeprom_t)); + + //MAC address + if((*this).has_key("mac-addr")){ + byte_copy(mac_addr_t::from_string((*this)["mac-addr"]).to_bytes(), eeprom_out->mac_addr); + } + + //IP address + if((*this).has_key("ip-addr")){ + ip_v4::bytes_type ip_addr_bytes = ip_v4::from_string((*this)["ip-addr"]).to_bytes(); + memcpy(&eeprom_out->ip_addr, &ip_addr_bytes, 4); + eeprom_out->ip_addr = uhd::htonx<boost::uint32_t>(eeprom_out->ip_addr); + } + + //Default router + if((*this).has_key("gateway")){ + ip_v4::bytes_type dr_addr_bytes = ip_v4::from_string((*this)["gateway"]).to_bytes(); + memcpy(&eeprom_out->dr_addr, &dr_addr_bytes, 4); + eeprom_out->dr_addr = uhd::htonx<boost::uint32_t>(eeprom_out->dr_addr); + } + + //Netmask + if((*this).has_key("netmask")){ + ip_v4::bytes_type netmask_bytes = ip_v4::from_string((*this)["netmask"]).to_bytes(); + memcpy(&eeprom_out->netmask, &netmask_bytes, 4); + eeprom_out->netmask = uhd::htonx<boost::uint32_t>(eeprom_out->netmask); + } + + //Serial + if((*this).has_key("serial")){ + byte_copy(byte_vector_t((*this)["serial"].begin(), (*this)["serial"].end()), eeprom_out->serial); + } + + //Name + if((*this).has_key("name")){ + byte_copy(byte_vector_t((*this)["name"].begin(), (*this)["name"].end()), eeprom_out->name); + } + + //Revision + if((*this).has_key("revision")){ + eeprom_out->revision = (*this)["revision"][0]-'0'; + } + + UHD_OCTOCLOCK_SEND_AND_RECV(xport, BURN_EEPROM_CMD, pkt_out, len, octoclock_data); + if(not UHD_OCTOCLOCK_PACKET_MATCHES(BURN_EEPROM_SUCCESS_ACK, pkt_out, pkt_in, len)) + throw uhd::runtime_error("Error writing to OctoClock EEPROM."); +} + +/*********************************************************************** + * Implementation of OctoClock EEPROM + **********************************************************************/ +octoclock_eeprom_t::octoclock_eeprom_t(void){ + /* NOP */ +} + +octoclock_eeprom_t::octoclock_eeprom_t(udp_simple::sptr transport){ + xport = transport; + _load(); +} + +void octoclock_eeprom_t::commit() const{ + if(!xport) throw uhd::runtime_error("There is no set device communication."); + _store(); +} diff --git a/host/lib/usrp_clock/octoclock/octoclock_impl.cpp b/host/lib/usrp_clock/octoclock/octoclock_impl.cpp new file mode 100644 index 000000000..8c207dd9f --- /dev/null +++ b/host/lib/usrp_clock/octoclock/octoclock_impl.cpp @@ -0,0 +1,437 @@ +// +// Copyright 2014 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#include <iostream> + +#include <boost/asio.hpp> +#include <boost/assign.hpp> +#include <boost/cstdint.hpp> +#include <boost/filesystem.hpp> +#include <boost/foreach.hpp> +#include <boost/format.hpp> +#include <boost/thread.hpp> + +#include <uhd/device.hpp> +#include <uhd/exception.hpp> +#include <uhd/transport/udp_simple.hpp> +#include <uhd/transport/if_addrs.hpp> +#include <uhd/types/dict.hpp> +#include <uhd/usrp/gps_ctrl.hpp> +#include <uhd/usrp_clock/octoclock_eeprom.hpp> +#include <uhd/utils/byteswap.hpp> +#include <uhd/utils/images.hpp> +#include <uhd/utils/msg.hpp> +#include <uhd/utils/paths.hpp> +#include <uhd/utils/static.hpp> + +#include "octoclock_impl.hpp" +#include "octoclock_uart.hpp" +#include "common.h" + +using namespace uhd; +using namespace uhd::usrp_clock; +using namespace uhd::transport; +namespace asio = boost::asio; +namespace fs = boost::filesystem; + +/*********************************************************************** + * Discovery + **********************************************************************/ +device_addrs_t octoclock_find(const device_addr_t &hint){ + //Handle the multi-device discovery + device_addrs_t hints = separate_device_addr(hint); + if (hints.size() > 1){ + device_addrs_t found_devices; + std::string error_msg; + BOOST_FOREACH(const device_addr_t &hint_i, hints){ + device_addrs_t found_devices_i = octoclock_find(hint_i); + if (found_devices_i.size() != 1) error_msg += str(boost::format( + "Could not resolve device hint \"%s\" to a single device." + ) % hint_i.to_string()); + else found_devices.push_back(found_devices_i[0]); + } + if (found_devices.empty()) return device_addrs_t(); + if (not error_msg.empty()) throw uhd::value_error(error_msg); + return device_addrs_t(1, combine_device_addrs(found_devices)); + } + + //Initialize the hint for a single device case + UHD_ASSERT_THROW(hints.size() <= 1); + hints.resize(1); //In case it was empty + device_addr_t _hint = hints[0]; + device_addrs_t octoclock_addrs; + + //return an empty list of addresses when type is set to non-OctoClock + if (hint.has_key("type") and hint["type"].find("octoclock") == std::string::npos) return octoclock_addrs; + + //Return an empty list of addresses when a resource is specified, + //since a resource is intended for a different, non-USB, device. + if (hint.has_key("resource")) return octoclock_addrs; + + //If no address was specified, send a broadcast on each interface + if (not _hint.has_key("addr")){ + BOOST_FOREACH(const if_addrs_t &if_addrs, get_if_addrs()){ + //avoid the loopback device + if (if_addrs.inet == asio::ip::address_v4::loopback().to_string()) continue; + + //create a new hint with this broadcast address + device_addr_t new_hint = hint; + new_hint["addr"] = if_addrs.bcast; + + //call discover with the new hint and append results + device_addrs_t new_octoclock_addrs = octoclock_find(new_hint); + octoclock_addrs.insert(octoclock_addrs.begin(), + new_octoclock_addrs.begin(), new_octoclock_addrs.end() + ); + } + return octoclock_addrs; + } + + //Create a UDP transport to communicate + udp_simple::sptr udp_transport = udp_simple::make_broadcast( + _hint["addr"], + BOOST_STRINGIZE(OCTOCLOCK_UDP_CTRL_PORT) + ); + + //Send a query packet + octoclock_packet_t pkt_out; + pkt_out.proto_ver = OCTOCLOCK_FW_COMPAT_NUM; + pkt_out.sequence = uhd::htonx<boost::uint32_t>(std::rand()); + pkt_out.len = 0; + pkt_out.code = OCTOCLOCK_QUERY_CMD; + try{ + udp_transport->send(boost::asio::buffer(&pkt_out, sizeof(pkt_out))); + } + catch(const std::exception &ex){ + UHD_MSG(error) << "OctoClock network discovery error - " << ex.what() << std::endl; + } + catch(...){ + UHD_MSG(error) << "OctoClock network discovery unknown error" << std::endl; + } + + boost::uint8_t octoclock_data[udp_simple::mtu]; + const octoclock_packet_t *pkt_in = reinterpret_cast<octoclock_packet_t*>(octoclock_data); + + while(true){ + size_t len = udp_transport->recv(asio::buffer(octoclock_data)); + if(UHD_OCTOCLOCK_PACKET_MATCHES(OCTOCLOCK_QUERY_ACK, pkt_out, pkt_in, len)){ + device_addr_t new_addr; + new_addr["addr"] = udp_transport->get_recv_addr(); + + //Attempt direct communication with OctoClock + udp_simple::sptr ctrl_xport = udp_simple::make_connected( + new_addr["addr"], + BOOST_STRINGIZE(OCTOCLOCK_UDP_CTRL_PORT) + ); + UHD_OCTOCLOCK_SEND_AND_RECV(ctrl_xport, OCTOCLOCK_QUERY_CMD, pkt_out, len, octoclock_data); + if(UHD_OCTOCLOCK_PACKET_MATCHES(OCTOCLOCK_QUERY_ACK, pkt_out, pkt_in, len)){ + //If the OctoClock is in its bootloader, don't ask for details + if(pkt_in->proto_ver == OCTOCLOCK_BOOTLOADER_PROTO_VER){ + new_addr["type"] = "octoclock-bootloader"; + octoclock_addrs.push_back(new_addr); + } + else{ + new_addr["type"] = "octoclock"; + + octoclock_eeprom_t oc_eeprom(ctrl_xport); + new_addr["name"] = oc_eeprom["name"]; + new_addr["serial"] = oc_eeprom["serial"]; + + //Filter based on optional keys (if any) + if( + (not _hint.has_key("name") or (_hint["name"] == new_addr["name"])) and + (not _hint.has_key("serial") or (_hint["serial"] == new_addr["serial"])) + ){ + octoclock_addrs.push_back(new_addr); + } + } + } + else continue; + } + + if(len == 0) break; + } + + return octoclock_addrs; +} + +device::sptr octoclock_make(const device_addr_t &device_addr){ + return device::sptr(new octoclock_impl(device_addr)); +} + +UHD_STATIC_BLOCK(register_octoclock_device){ + device::register_device(&octoclock_find, &octoclock_make, device::CLOCK); +} + +/*********************************************************************** + * Structors + **********************************************************************/ +octoclock_impl::octoclock_impl(const device_addr_t &_device_addr){ + UHD_MSG(status) << "Opening an OctoClock device..." << std::endl; + _type = device::CLOCK; + device_addrs_t device_args = separate_device_addr(_device_addr); + _sequence = std::rand(); + + //////////////////////////////////////////////////////////////////// + // Initialize the property tree + //////////////////////////////////////////////////////////////////// + _tree = property_tree::make(); + _tree->create<std::string>("/name").set("OctoClock Device"); + + for(size_t oci = 0; oci < device_args.size(); oci++){ + const device_addr_t device_args_i = device_args[oci]; + const std::string addr = device_args_i["addr"]; + //Can't make a device out of an OctoClock in bootloader state + if(device_args_i["type"] == "octoclock-bootloader"){ + throw uhd::runtime_error(str(boost::format( + "\n\nThis device is in its bootloader state and cannot be used by UHD.\n" + "This may mean the firmware on the device has been corrupted and will\n" + "need to be burned again.\n\n" + "%s\n" + ) % _get_images_help_message(addr))); + } + + const std::string oc = boost::lexical_cast<std::string>(oci); + + //////////////////////////////////////////////////////////////////// + // Set up UDP transports + //////////////////////////////////////////////////////////////////// + _oc_dict[oc].ctrl_xport = udp_simple::make_connected(addr, BOOST_STRINGIZE(OCTOCLOCK_UDP_CTRL_PORT)); + _oc_dict[oc].gpsdo_xport = udp_simple::make_connected(addr, BOOST_STRINGIZE(OCTOCLOCK_UDP_GPSDO_PORT)); + + const fs_path oc_path = "/mboards/" + oc; + _tree->create<std::string>(oc_path / "name").set("OctoClock"); + + //////////////////////////////////////////////////////////////////// + // Check the firmware compatibility number + //////////////////////////////////////////////////////////////////// + boost::uint32_t fw_version = _get_fw_version(oc); + if(fw_version != OCTOCLOCK_FW_COMPAT_NUM){ + throw uhd::runtime_error(str(boost::format( + "\n\nPlease update your OctoClock's firmware.\n" + "Expected firmware compatibility number %d, but got %d:\n" + "The firmware build is not compatible with the host code build.\n\n" + "%s\n" + ) % int(OCTOCLOCK_FW_COMPAT_NUM) % int(fw_version) % _get_images_help_message(addr))); + } + _tree->create<std::string>(oc_path / "fw_version").set(boost::lexical_cast<std::string>(int(fw_version))); + + //////////////////////////////////////////////////////////////////// + // Set up EEPROM + //////////////////////////////////////////////////////////////////// + _oc_dict[oc].eeprom = octoclock_eeprom_t(_oc_dict[oc].ctrl_xport); + _tree->create<octoclock_eeprom_t>(oc_path / "eeprom") + .set(_oc_dict[oc].eeprom) + .subscribe(boost::bind(&octoclock_impl::_set_eeprom, this, oc, _1)); + + //////////////////////////////////////////////////////////////////// + // Initialize non-GPSDO sensors + //////////////////////////////////////////////////////////////////// + _tree->create<boost::uint32_t>(oc_path / "time") + .publish(boost::bind(&octoclock_impl::_get_time, this, oc)); + _tree->create<sensor_value_t>(oc_path / "sensors/ext_ref_detected") + .publish(boost::bind(&octoclock_impl::_ext_ref_detected, this, oc)); + _tree->create<sensor_value_t>(oc_path / "sensors/gps_detected") + .publish(boost::bind(&octoclock_impl::_gps_detected, this, oc)); + _tree->create<sensor_value_t>(oc_path / "sensors/using_ref") + .publish(boost::bind(&octoclock_impl::_which_ref, this, oc)); + _tree->create<sensor_value_t>(oc_path / "sensors/switch_pos") + .publish(boost::bind(&octoclock_impl::_switch_pos, this, oc)); + + //////////////////////////////////////////////////////////////////// + // Check reference and GPSDO + //////////////////////////////////////////////////////////////////// + std::string asterisk = (device_args.size() > 1) ? " * " : ""; + + if(device_args.size() > 1){ + UHD_MSG(status) << std::endl << "Checking status of " << addr << ":" << std::endl; + } + UHD_MSG(status) << boost::format("%sDetecting internal GPSDO...") % asterisk << std::flush; + + _get_state(oc); + if(_oc_dict[oc].state.gps_detected){ + try{ + _oc_dict[oc].gps = gps_ctrl::make(octoclock_make_uart_iface(_oc_dict[oc].gpsdo_xport)); + + if(_oc_dict[oc].gps and _oc_dict[oc].gps->gps_detected()){ + BOOST_FOREACH(const std::string &name, _oc_dict[oc].gps->get_sensors()){ + _tree->create<sensor_value_t>(oc_path / "sensors" / name) + .publish(boost::bind(&gps_ctrl::get_sensor, _oc_dict[oc].gps, name)); + } + } + else{ + //If GPSDO communication failed, set gps_detected to false + _oc_dict[oc].state.gps_detected = 0; + UHD_MSG(warning) << "Device reports that it has a GPSDO, but we cannot communicate with it." << std::endl; + std::cout << std::endl; + } + } + catch(std::exception &e){ + UHD_MSG(error) << "An error occurred making GPSDO control: " << e.what() << std::endl; + } + } + else UHD_MSG(status) << "No GPSDO found" << std::endl; + UHD_MSG(status) << boost::format("%sDetecting external reference...%s") % asterisk + % _ext_ref_detected(oc).value + << std::endl; + UHD_MSG(status) << boost::format("%sDetecting switch position...%s") % asterisk + % _switch_pos(oc).value + << std::endl; + std::string ref = _which_ref(oc).value; + if(ref == "none") UHD_MSG(status) << boost::format("%sDevice is not using any reference") % asterisk << std::endl; + else UHD_MSG(status) << boost::format("%sDevice is using %s reference") % asterisk + % _which_ref(oc).value + << std::endl; + } +} + +rx_streamer::sptr octoclock_impl::get_rx_stream(UHD_UNUSED(const stream_args_t &args)){ + throw uhd::not_implemented_error("This function is incompatible with this device."); +} + +tx_streamer::sptr octoclock_impl::get_tx_stream(UHD_UNUSED(const stream_args_t &args)){ + throw uhd::not_implemented_error("This function is incompatible with this device."); +} + +bool octoclock_impl::recv_async_msg(UHD_UNUSED(uhd::async_metadata_t&), UHD_UNUSED(double)){ + throw uhd::not_implemented_error("This function is incompatible with this device."); +} + +void octoclock_impl::_set_eeprom(const std::string &oc, const octoclock_eeprom_t &oc_eeprom){ + /* + * The OctoClock needs a full octoclock_eeprom_t so as to not erase + * what it currently has in the EEPROM, so store the relevant values + * from the user's input and send that instead. + */ + BOOST_FOREACH(const std::string &key, oc_eeprom.keys()){ + if(_oc_dict[oc].eeprom.has_key(key)) _oc_dict[oc].eeprom[key] = oc_eeprom[key]; + } + _oc_dict[oc].eeprom.commit(); +} + +boost::uint32_t octoclock_impl::_get_fw_version(const std::string &oc){ + octoclock_packet_t pkt_out; + pkt_out.sequence = _sequence++; + pkt_out.len = 0; + size_t len; + + boost::uint8_t octoclock_data[udp_simple::mtu]; + const octoclock_packet_t *pkt_in = reinterpret_cast<octoclock_packet_t*>(octoclock_data); + + UHD_OCTOCLOCK_SEND_AND_RECV(_oc_dict[oc].ctrl_xport, OCTOCLOCK_QUERY_CMD, pkt_out, len, octoclock_data); + if(UHD_OCTOCLOCK_PACKET_MATCHES(OCTOCLOCK_QUERY_ACK, pkt_out, pkt_in, len)){ + return pkt_in->proto_ver; + } + else throw uhd::runtime_error("Failed to retrive firmware version from OctoClock."); +} + +void octoclock_impl::_get_state(const std::string &oc){ + octoclock_packet_t pkt_out; + pkt_out.sequence = _sequence++; + pkt_out.len = 0; + size_t len = 0; + + boost::uint8_t octoclock_data[udp_simple::mtu]; + const octoclock_packet_t *pkt_in = reinterpret_cast<octoclock_packet_t*>(octoclock_data); + + UHD_OCTOCLOCK_SEND_AND_RECV(_oc_dict[oc].ctrl_xport, SEND_STATE_CMD, pkt_out, len, octoclock_data); + if(UHD_OCTOCLOCK_PACKET_MATCHES(SEND_STATE_ACK, pkt_out, pkt_in, len)){ + const octoclock_state_t *state = reinterpret_cast<const octoclock_state_t*>(pkt_in->data); + _oc_dict[oc].state = *state; + } + else throw uhd::runtime_error("Failed to retrieve state information from OctoClock."); +} + +uhd::dict<ref_t, std::string> _ref_strings = boost::assign::map_list_of + (NO_REF, "none") + (INTERNAL, "internal") + (EXTERNAL, "external") +; + +uhd::dict<switch_pos_t, std::string> _switch_pos_strings = boost::assign::map_list_of + (UP, "Prefer internal") + (DOWN, "Prefer external") +; + +sensor_value_t octoclock_impl::_ext_ref_detected(const std::string &oc){ + _get_state(oc); + + return sensor_value_t("External reference detected", (_oc_dict[oc].state.external_detected > 0), + "true", "false"); +} + +sensor_value_t octoclock_impl::_gps_detected(const std::string &oc){ + //Don't check, this shouldn't change once device is turned on + + return sensor_value_t("GPSDO detected", (_oc_dict[oc].state.gps_detected > 0), + "true", "false"); +} + +sensor_value_t octoclock_impl::_which_ref(const std::string &oc){ + _get_state(oc); + + if(not _ref_strings.has_key(ref_t(_oc_dict[oc].state.which_ref))){ + throw uhd::runtime_error("Invalid reference detected."); + } + + return sensor_value_t("Using reference", _ref_strings[ref_t(_oc_dict[oc].state.which_ref)], ""); +} + +sensor_value_t octoclock_impl::_switch_pos(const std::string &oc){ + _get_state(oc); + + if(not _switch_pos_strings.has_key(switch_pos_t(_oc_dict[oc].state.switch_pos))){ + throw uhd::runtime_error("Invalid switch position detected."); + } + + return sensor_value_t("Switch position", _switch_pos_strings[switch_pos_t(_oc_dict[oc].state.switch_pos)], ""); +} + +boost::uint32_t octoclock_impl::_get_time(const std::string &oc){ + if(_oc_dict[oc].state.gps_detected){ + std::string time_str = _oc_dict[oc].gps->get_sensor("gps_time").value; + return boost::lexical_cast<boost::uint32_t>(time_str); + } + else throw uhd::runtime_error("This device cannot return a time."); +} + +std::string octoclock_impl::_get_images_help_message(const std::string &addr){ + const std::string image_name = "octoclock_r4_fw.bin"; + + //Check to see if image is in default location + std::string image_location; + try{ + image_location = uhd::find_image_path(image_name); + } + catch(const std::exception &e){ + return str(boost::format("Could not find %s in your images path.\n%s") + % image_name + % uhd::print_images_error()); + } + + //Get escape character + #ifdef UHD_PLATFORM_WIN32 + const std::string ml = "^\n "; + #else + const std::string ml = "\\\n "; + #endif + + //Get burner command + const std::string burner_path = (fs::path(uhd::get_pkg_path()) / "bin" / "octoclock_firmware_burner").string(); + const std::string burner_cmd = str(boost::format("%s %s--addr=\"%s\"") % burner_path % ml % addr); + return str(boost::format("%s\n%s") % uhd::print_images_error() % burner_cmd); +} diff --git a/host/lib/usrp_clock/octoclock/octoclock_impl.hpp b/host/lib/usrp_clock/octoclock/octoclock_impl.hpp new file mode 100644 index 000000000..ab45cd5f0 --- /dev/null +++ b/host/lib/usrp_clock/octoclock/octoclock_impl.hpp @@ -0,0 +1,80 @@ +// +// Copyright 2014 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#ifndef INCLUDED_OCTOCLOCK_IMPL_HPP +#define INCLUDED_OCTOCLOCK_IMPL_HPP + +#include <boost/shared_ptr.hpp> +#include <boost/thread.hpp> + +#include <uhd/device.hpp> +#include <uhd/stream.hpp> +#include <uhd/usrp/gps_ctrl.hpp> +#include <uhd/usrp_clock/octoclock_eeprom.hpp> +#include <uhd/types/device_addr.hpp> +#include <uhd/types/dict.hpp> +#include <uhd/types/sensors.hpp> + +#include "common.h" + +/*! + * OctoClock implementation guts + */ +class octoclock_impl : public uhd::device{ +public: + octoclock_impl(const uhd::device_addr_t &); + ~octoclock_impl(void) {}; + + uhd::rx_streamer::sptr get_rx_stream(const uhd::stream_args_t &args); + + uhd::tx_streamer::sptr get_tx_stream(const uhd::stream_args_t &args); + + bool recv_async_msg(uhd::async_metadata_t&, double); + +private: + struct oc_container_type{ + uhd::usrp_clock::octoclock_eeprom_t eeprom; + octoclock_state_t state; + uhd::transport::udp_simple::sptr ctrl_xport; + uhd::transport::udp_simple::sptr gpsdo_xport; + uhd::gps_ctrl::sptr gps; + }; + uhd::dict<std::string, oc_container_type> _oc_dict; + boost::uint32_t _sequence; + + void _set_eeprom(const std::string &oc, const uhd::usrp_clock::octoclock_eeprom_t &oc_eeprom); + + boost::uint32_t _get_fw_version(const std::string &oc); + + void _get_state(const std::string &oc); + + uhd::sensor_value_t _ext_ref_detected(const std::string &oc); + + uhd::sensor_value_t _gps_detected(const std::string &oc); + + uhd::sensor_value_t _which_ref(const std::string &oc); + + uhd::sensor_value_t _switch_pos(const std::string &oc); + + boost::uint32_t _get_time(const std::string &oc); + + std::string _get_images_help_message(const std::string &addr); + + boost::mutex _device_mutex; +}; + +#endif /* INCLUDED_OCTOCLOCK_IMPL_HPP */ diff --git a/host/lib/usrp_clock/octoclock/octoclock_uart.cpp b/host/lib/usrp_clock/octoclock/octoclock_uart.cpp new file mode 100644 index 000000000..eb3f40d9c --- /dev/null +++ b/host/lib/usrp_clock/octoclock/octoclock_uart.cpp @@ -0,0 +1,162 @@ +// +// Copyright 2014 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#include <iostream> +#include <string> +#include <string.h> + +#include <boost/algorithm/string.hpp> +#include <boost/asio.hpp> +#include <boost/cstdint.hpp> +#include <boost/format.hpp> +#include <boost/thread/thread.hpp> + +#include <uhd/exception.hpp> +#include <uhd/utils/byteswap.hpp> + +#include "common.h" +#include "octoclock_uart.hpp" + +namespace asio = boost::asio; +using namespace uhd::transport; + +#define NUM_WRAPS_EQUAL (_state.num_wraps == _device_state.num_wraps) +#define POS_EQUAL (_state.pos == _device_state.pos) +#define STATES_EQUAL (NUM_WRAPS_EQUAL && POS_EQUAL) +#define LOCAL_STATE_AHEAD (_state.num_wraps > _device_state.num_wraps || \ + (NUM_WRAPS_EQUAL && _state.pos > _device_state.pos)) + +namespace uhd{ + octoclock_uart_iface::octoclock_uart_iface(udp_simple::sptr udp): uart_iface(){ + _udp = udp; + _state.num_wraps = 0; + _state.pos = 0; + _device_state.num_wraps = 0; + _device_state.pos = 0; + size_t len = 0; + + //Get pool size from device + octoclock_packet_t pkt_out; + pkt_out.sequence = uhd::htonx<boost::uint16_t>(std::rand()); + pkt_out.len = 0; + + boost::uint8_t octoclock_data[udp_simple::mtu]; + const octoclock_packet_t *pkt_in = reinterpret_cast<octoclock_packet_t*>(octoclock_data); + + UHD_OCTOCLOCK_SEND_AND_RECV(_udp, SEND_POOLSIZE_CMD, pkt_out, len, octoclock_data); + if(UHD_OCTOCLOCK_PACKET_MATCHES(SEND_POOLSIZE_ACK, pkt_out, pkt_in, len)){ + _poolsize = pkt_in->poolsize; + _cache.resize(_poolsize); + } + else throw uhd::runtime_error("Failed to communicate with GPSDO."); + } + + void octoclock_uart_iface::write_uart(const std::string &buf){ + std::string to_send = boost::algorithm::replace_all_copy(buf, "\n", "\r\n"); + size_t len = 0; + + octoclock_packet_t pkt_out; + pkt_out.sequence = uhd::htonx<boost::uint32_t>(std::rand()); + pkt_out.len = to_send.size(); + memcpy(pkt_out.data, to_send.c_str(), to_send.size()); + + boost::uint8_t octoclock_data[udp_simple::mtu]; + const octoclock_packet_t *pkt_in = reinterpret_cast<octoclock_packet_t*>(octoclock_data); + + UHD_OCTOCLOCK_SEND_AND_RECV(_udp, HOST_SEND_TO_GPSDO_CMD, pkt_out, len, octoclock_data); + if(not UHD_OCTOCLOCK_PACKET_MATCHES(HOST_SEND_TO_GPSDO_ACK, pkt_out, pkt_in, len)){ + throw uhd::runtime_error("Failed to send commands to GPSDO."); + } + } + + std::string octoclock_uart_iface::read_uart(double timeout){ + std::string result; + + boost::system_time exit_time = boost::get_system_time() + boost::posix_time::milliseconds(long(timeout*1e3)); + + while(boost::get_system_time() < exit_time){ + _update_cache(); + + for(char ch = _getchar(); ch != -1; ch = _getchar()){ + if(ch == '\r') continue; //Skip carriage returns + _rxbuff += ch; + + //If newline found, return string + if(ch == '\n'){ + result = _rxbuff; + _rxbuff.clear(); + return result; + } + } + boost::this_thread::sleep(boost::posix_time::milliseconds(1)); + } + + return result; + } + + void octoclock_uart_iface::_update_cache(){ + octoclock_packet_t pkt_out; + pkt_out.len = 0; + size_t len = 0; + + boost::uint8_t octoclock_data[udp_simple::mtu]; + const octoclock_packet_t *pkt_in = reinterpret_cast<octoclock_packet_t*>(octoclock_data); + + if(STATES_EQUAL or LOCAL_STATE_AHEAD){ + pkt_out.sequence++; + UHD_OCTOCLOCK_SEND_AND_RECV(_udp, SEND_GPSDO_CACHE_CMD, pkt_out, len, octoclock_data); + if(UHD_OCTOCLOCK_PACKET_MATCHES(SEND_GPSDO_CACHE_ACK, pkt_out, pkt_in, len)){ + memcpy(&_cache[0], pkt_in->data, _poolsize); + _device_state = pkt_in->state; + } + + boost::uint8_t delta_wraps = (_device_state.num_wraps - _state.num_wraps); + if(delta_wraps > 1 or + ((delta_wraps == 1) and (_device_state.pos >= _state.pos))){ + + _state.pos = (_device_state.pos+1) % _poolsize; + _state.num_wraps = (_device_state.num_wraps-1); + + while((_cache[_state.pos] != '\n') and (_state.pos != _device_state.pos)){ + _state.pos = (_state.pos+1) % _poolsize; + //We may have wrapped around locally + if(_state.pos == 0) _state.num_wraps++; + } + _state.pos = (_state.pos+1) % _poolsize; + //We may have wrapped around locally + if(_state.pos == 0) _state.num_wraps++; + } + } + } + + char octoclock_uart_iface::_getchar(){ + if(LOCAL_STATE_AHEAD){ + return -1; + } + + char ch = _cache[_state.pos]; + _state.pos = ((_state.pos+1) % _poolsize); + //We may have wrapped around locally + if(_state.pos == 0) _state.num_wraps++; + + return ch; + } + + uart_iface::sptr octoclock_make_uart_iface(udp_simple::sptr udp){ + return uart_iface::sptr(new octoclock_uart_iface(udp)); + } +} diff --git a/host/lib/usrp_clock/octoclock/octoclock_uart.hpp b/host/lib/usrp_clock/octoclock/octoclock_uart.hpp new file mode 100644 index 000000000..05d1bb121 --- /dev/null +++ b/host/lib/usrp_clock/octoclock/octoclock_uart.hpp @@ -0,0 +1,57 @@ +// +// Copyright 2014 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the uart_ifaceied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#ifndef INCLUDED_OCTOCLOCK_UART_HPP +#define INCLUDED_OCTOCLOCK_UART_HPP + +#include <vector> + +#include <uhd/transport/udp_simple.hpp> +#include <uhd/types/serial.hpp> + +/*! + * The OctoClock doesn't take UART input per se but reads a specific + * packet type and sends the string from there through its own serial + * functions. + */ +namespace uhd{ +class octoclock_uart_iface : public uhd::uart_iface{ +public: + octoclock_uart_iface(uhd::transport::udp_simple::sptr udp); + ~octoclock_uart_iface(void) {}; + + void write_uart(const std::string &buf); + std::string read_uart(double timeout); + +private: + uhd::transport::udp_simple::sptr _udp; + + boost::uint16_t _poolsize; + gpsdo_cache_state_t _state; + gpsdo_cache_state_t _device_state; + std::vector<boost::uint8_t> _cache; + std::string _rxbuff; + + void _update_cache(); + char _getchar(); +}; + +uart_iface::sptr octoclock_make_uart_iface(uhd::transport::udp_simple::sptr udp); + +} + +#endif /* INCLUDED_OCTOCLOCK_UART_HPP */ diff --git a/host/utils/CMakeLists.txt b/host/utils/CMakeLists.txt index 7604a7d37..11bb2488a 100644 --- a/host/utils/CMakeLists.txt +++ b/host/utils/CMakeLists.txt @@ -1,5 +1,5 @@ # -# Copyright 2010-2013 Ettus Research LLC +# Copyright 2010-2014 Ettus Research LLC # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -62,8 +62,25 @@ IF(ENABLE_USB) ) INCLUDE_DIRECTORIES(${LIBUSB_INCLUDE_DIRS}) # Additional include directories for b2xx_fx3_utils - INCLUDE_DIRECTORIES(${CMAKE_CURRENT_SOURCE_DIR}/../lib/usrp/b200 ${CMAKE_CURRENT_SOURCE_DIR}/../lib/usrp/common) + INCLUDE_DIRECTORIES( + ${CMAKE_CURRENT_SOURCE_DIR}/../lib/usrp/b200 + ${CMAKE_CURRENT_SOURCE_DIR}/../lib/usrp/common + ${CMAKE_CURRENT_SOURCE_DIR}/../lib/usrp/common/ad9361_driver) ENDIF(ENABLE_USB) +IF(ENABLE_OCTOCLOCK) + LIST(APPEND util_share_sources + octoclock_burn_eeprom.cpp + ) + + SET(octoclock_burner_sources + octoclock_firmware_burner.cpp + ihexcvt.cpp + ) + + ADD_EXECUTABLE(octoclock_firmware_burner ${octoclock_burner_sources}) + TARGET_LINK_LIBRARIES(octoclock_firmware_burner uhd ${Boost_LIBRARIES}) + UHD_INSTALL(TARGETS octoclock_firmware_burner RUNTIME DESTINATION ${RUNTIME_DIR} COMPONENT utilities) +ENDIF(ENABLE_OCTOCLOCK) IF(LINUX AND ENABLE_USB) UHD_INSTALL(FILES diff --git a/host/utils/cdecode.c b/host/utils/cdecode.c index 0a9b5c46b..1d09cbe22 100644 --- a/host/utils/cdecode.c +++ b/host/utils/cdecode.c @@ -1,80 +1,80 @@ -/*
-cdecoder.c - c source to a base64 decoding algorithm implementation
-
-This is part of the libb64 project, and has been placed in the public domain.
-For details, see http://sourceforge.net/projects/libb64
-*/
-
-#include "cdecode.h"
-
-int base64_decode_value(char value_in){
- static const char decoding[] = {62,-1,-1,-1,63,52,53,54,55,56,57,58,59,60,61,-1,-1,-1,-2,-1,-1,-1,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,-1,-1,-1,-1,-1,-1,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51};
- static const char decoding_size = sizeof(decoding);
- value_in -= 43;
- if ((signed char)value_in < 0 || value_in > decoding_size) return -1;
- return decoding[(int)value_in];
-}
-
-void base64_init_decodestate(base64_decodestate* state_in){
- state_in->step = step_a;
- state_in->plainchar = 0;
-}
-
-size_t base64_decode_block(const char* code_in, const size_t length_in, char* plaintext_out, base64_decodestate* state_in){
- const char* codechar = code_in;
- char* plainchar = plaintext_out;
- char fragment;
-
- *plainchar = state_in->plainchar;
-
- switch (state_in->step){
- while (1){
- case step_a:
- do{
- if (codechar == code_in+length_in){
- state_in->step = step_a;
- state_in->plainchar = *plainchar;
- return plainchar - plaintext_out;
- }
- fragment = (char)base64_decode_value(*codechar++);
- } while ((signed char)fragment < 0);
- *plainchar = (fragment & 0x03f) << 2;
-
- case step_b:
- do{
- if (codechar == code_in+length_in){
- state_in->step = step_b;
- state_in->plainchar = *plainchar;
- return plainchar - plaintext_out;
- }
- fragment = (char)base64_decode_value(*codechar++);
- } while ((signed char)fragment < 0);
- *plainchar++ |= (fragment & 0x030) >> 4;
- *plainchar = (fragment & 0x00f) << 4;
- case step_c:
- do{
- if (codechar == code_in+length_in)
- {
- state_in->step = step_c;
- state_in->plainchar = *plainchar;
- return plainchar - plaintext_out;
- }
- fragment = (char)base64_decode_value(*codechar++);
- } while ((signed char)fragment < 0);
- *plainchar++ |= (fragment & 0x03c) >> 2;
- *plainchar = (fragment & 0x003) << 6;
- case step_d:
- do{
- if (codechar == code_in+length_in){
- state_in->step = step_d;
- state_in->plainchar = *plainchar;
- return plainchar - plaintext_out;
- }
- fragment = (char)base64_decode_value(*codechar++);
- } while ((signed char)fragment < 0);
- *plainchar++ |= (fragment & 0x03f);
- }
- }
- /* control should not reach here */
- return plainchar - plaintext_out;
-}
+/* +cdecoder.c - c source to a base64 decoding algorithm implementation + +This is part of the libb64 project, and has been placed in the public domain. +For details, see http://sourceforge.net/projects/libb64 +*/ + +#include "cdecode.h" + +int base64_decode_value(char value_in){ + static const char decoding[] = {62,-1,-1,-1,63,52,53,54,55,56,57,58,59,60,61,-1,-1,-1,-2,-1,-1,-1,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,-1,-1,-1,-1,-1,-1,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51}; + static const char decoding_size = sizeof(decoding); + value_in -= 43; + if ((signed char)value_in < 0 || value_in > decoding_size) return -1; + return decoding[(int)value_in]; +} + +void base64_init_decodestate(base64_decodestate* state_in){ + state_in->step = step_a; + state_in->plainchar = 0; +} + +size_t base64_decode_block(const char* code_in, const size_t length_in, char* plaintext_out, base64_decodestate* state_in){ + const char* codechar = code_in; + char* plainchar = plaintext_out; + char fragment; + + *plainchar = state_in->plainchar; + + switch (state_in->step){ + while (1){ + case step_a: + do{ + if (codechar == code_in+length_in){ + state_in->step = step_a; + state_in->plainchar = *plainchar; + return plainchar - plaintext_out; + } + fragment = (char)base64_decode_value(*codechar++); + } while ((signed char)fragment < 0); + *plainchar = (fragment & 0x03f) << 2; + + case step_b: + do{ + if (codechar == code_in+length_in){ + state_in->step = step_b; + state_in->plainchar = *plainchar; + return plainchar - plaintext_out; + } + fragment = (char)base64_decode_value(*codechar++); + } while ((signed char)fragment < 0); + *plainchar++ |= (fragment & 0x030) >> 4; + *plainchar = (fragment & 0x00f) << 4; + case step_c: + do{ + if (codechar == code_in+length_in) + { + state_in->step = step_c; + state_in->plainchar = *plainchar; + return plainchar - plaintext_out; + } + fragment = (char)base64_decode_value(*codechar++); + } while ((signed char)fragment < 0); + *plainchar++ |= (fragment & 0x03c) >> 2; + *plainchar = (fragment & 0x003) << 6; + case step_d: + do{ + if (codechar == code_in+length_in){ + state_in->step = step_d; + state_in->plainchar = *plainchar; + return plainchar - plaintext_out; + } + fragment = (char)base64_decode_value(*codechar++); + } while ((signed char)fragment < 0); + *plainchar++ |= (fragment & 0x03f); + } + } + /* control should not reach here */ + return plainchar - plaintext_out; +} diff --git a/host/utils/fx2_init_eeprom.cpp b/host/utils/fx2_init_eeprom.cpp index 701092a5d..5711b73e0 100644 --- a/host/utils/fx2_init_eeprom.cpp +++ b/host/utils/fx2_init_eeprom.cpp @@ -1,5 +1,5 @@ // -// Copyright 2010 Ettus Research LLC +// Copyright 2010,2014 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -72,7 +72,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ //find and create a control transport to do the writing. - uhd::device_addrs_t found_addrs = uhd::device::find(device_addr); + uhd::device_addrs_t found_addrs = uhd::device::find(device_addr, uhd::device::USRP); if (found_addrs.size() == 0){ std::cerr << "No USRP devices found" << std::endl; @@ -82,7 +82,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ for (size_t i = 0; i < found_addrs.size(); i++){ std::cout << "Writing EEPROM data..." << std::endl; //uhd::device_addrs_t devs = uhd::device::find(found_addrs[i]); - uhd::device::sptr dev = uhd::device::make(found_addrs[i]); + uhd::device::sptr dev = uhd::device::make(found_addrs[i], uhd::device::USRP); uhd::property_tree::sptr tree = dev->get_tree(); tree->access<std::string>("/mboards/0/load_eeprom").set(vm["image"].as<std::string>()); } diff --git a/host/utils/ihexcvt.cpp b/host/utils/ihexcvt.cpp new file mode 100644 index 000000000..0605ee61c --- /dev/null +++ b/host/utils/ihexcvt.cpp @@ -0,0 +1,250 @@ +/* IHexCvt - Intel HEX File <=> Binary Converter (C++) + Copyright (C) 2014 Ali Nakisaee + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.*/ + +//Include needed stuff from C++ +#include <iostream> +#include <fstream> +#include <string> + +//... and also from C +#include <stdio.h> + +#include <boost/filesystem.hpp> + +#include <uhd/exception.hpp> +#include "ihexcvt.hpp" + +//Avoid repeating 'std::': +using namespace std; + +//The following function reads a hexadecimal number from a text file. +template <class T> +static bool ReadValueFromHex(ifstream& InputFile, T& outCh, unsigned char* ApplyChecksum) +{ + char V, L; + T X = 0; + outCh = 0; + + //Get the characters one by one. + //Remember: These values are big-endian. + //Remember: Every two hex characters (0-9/A-F) indicate ONE byte. + for (size_t i = 0; i < 2 * sizeof(T); i++) + { + InputFile.get( V ); + if (InputFile.fail()) + return false; + + X <<= 4; + if (V >= '0' && V <= '9') + L = (V - '0'); + else if (V >= 'a' && V <= 'f') + L = (V - 'a' + 10); + else if (V >= 'A' && V <= 'F') + L = (V - 'A' + 10); + else + return false; + X |= L; + + //Apply this character to the checksum + if (ApplyChecksum && i % 2 == 1) *ApplyChecksum += X & 0xFF; + } + + //Return... + outCh = X; + return true; +} + +//The following function writes a hexadecimal number from a text file. +template <class T> +static bool WriteHexValue(ofstream& OutFile, T Value, unsigned char* CalcChecksum) +{ + unsigned char V0 = 0; + char C; + + //Remember: These values are big-endian. + for (size_t i = 0; i < sizeof(T); i++) + { + //Get byte #i from the value. + V0 = (Value >> ((sizeof(T) - i - 1) * 8)) & 0xFF; + + //Extract the high nibble (4-bits) + if ((V0 & 0xF0) <= 0x90) + C = (V0 >> 4) + '0'; + else + C = (V0 >> 4) + ('A' - 10); + OutFile.put( C ); + + //Extract the low nibble (4-bits) + if ((V0 & 0xF) <= 0x9) + C = (V0 & 0xF) + '0'; + else + C = (V0 & 0xF) + ('A' - 10); + OutFile.put( C ); + + //Calculate the checksum + if (CalcChecksum) *CalcChecksum += V0; + } + return true; +} + +//Skip any incoming whitespaces +static void SkipWhitespace(ifstream& InputFile) +{ + for (;;) + { + char C; + InputFile.get(C); + if (InputFile.eof() || InputFile.fail()) break; + if (!(C == '\n' || C == '\r' || C == ' ' || C == '\t' || C == '\v')) + { + InputFile.putback(C); + break; + } + } +} + +//The function responsible for conversion from HEX files to BINary. +void Hex2Bin(const char* SrcName, const char* DstName, bool IgnoreChecksum) +{ + ifstream Src(SrcName); + if (Src.bad()) + { + throw uhd::runtime_error("Could not convert Intel .hex file to binary."); + } + + ofstream Dst(DstName, ios_base::binary); + if (Dst.bad()) + { + throw uhd::runtime_error("Could not convert Intel .hex file to binary."); + } + + char Ch; + int LineIdx = 1; + + unsigned char ByteCount; + unsigned short AddressLow; + unsigned short Extra; + unsigned long ExtraL; + unsigned long AddressOffset = 0; + unsigned char RecordType; + unsigned char Data[255]; + unsigned char CurChecksum; + unsigned char FileChecksum; + bool EOFMarker = false; + bool EOFWarn = false; + + for ( ;; ) + { + Src.get(Ch); + if (Src.eof()) + break; + if (EOFMarker && !EOFWarn) + { + throw uhd::runtime_error("Could not convert Intel .hex file to binary."); + } + if (Ch != ':') goto genericErr; + + CurChecksum = 0; + if (!ReadValueFromHex( Src, ByteCount, &CurChecksum )) goto genericErr; + if (!ReadValueFromHex( Src, AddressLow, &CurChecksum )) goto genericErr; + if (!ReadValueFromHex( Src, RecordType, &CurChecksum )) goto genericErr; + + switch (RecordType) + { + case 0x00: //Data record + for (int i = 0; i < ByteCount; i++) + if (!ReadValueFromHex( Src, Data[i], &CurChecksum )) goto genericErr; + break; + case 0x01: //End Marker + if ( ByteCount != 0 ) + { + goto onErrExit; + } + EOFMarker = true; + break; + case 0x02: //Extended Segment Address + if ( ByteCount != 2 || AddressLow != 0 ) + { + goto onErrExit; + } + if (!ReadValueFromHex( Src, Extra, &CurChecksum )) goto genericErr; + AddressOffset = (unsigned long)Extra << 4; + break; + case 0x03: //Start Segment Address + if ( ByteCount != 4 || AddressLow != 0 ) + { + goto onErrExit; + } + if (!ReadValueFromHex( Src, ExtraL, &CurChecksum )) goto genericErr; + break; + case 0x04: //Extended Linear Address + if ( ByteCount != 2 || AddressLow != 0 ) + { + goto onErrExit; + } + if (!ReadValueFromHex( Src, Extra, &CurChecksum )) goto genericErr; + AddressOffset = (unsigned long)Extra << 16; + break; + case 0x05: //Start Linear Address + if ( ByteCount != 4 || AddressLow != 0 ) + { + goto onErrExit; + } + if (!ReadValueFromHex( Src, ExtraL, &CurChecksum )) goto genericErr; + break; + } + + //Verify checksum + CurChecksum = (~(CurChecksum & 0xFF) + 1) & 0xFF; + if (!ReadValueFromHex( Src, FileChecksum, NULL )) goto genericErr; + if (CurChecksum != FileChecksum) + { + if (!IgnoreChecksum) goto onErrExit; + } + + //Put Data + if (RecordType == 0x00) + { + Dst.seekp( AddressLow + AddressOffset ); + for (int i = 0; i < ByteCount; i++) + { + Dst.put( Data[i] ); + } + } + + //Skip any white space + SkipWhitespace( Src ); + + LineIdx++; + } + + Dst << flush; + Dst.close(); + + return; + +genericErr: + throw uhd::runtime_error("Invalid Intel .hex file detected."); + +onErrExit: + Dst.close(); + Src.close(); + boost::filesystem::remove(DstName); + throw uhd::runtime_error("Could not convert Intel .hex file to binary."); +} diff --git a/host/utils/ihexcvt.hpp b/host/utils/ihexcvt.hpp new file mode 100644 index 000000000..d577ece1f --- /dev/null +++ b/host/utils/ihexcvt.hpp @@ -0,0 +1,22 @@ +// +// Copyright 2014 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// +#ifndef _IHEXCVT_HPP_ +#define _IHEXCVT_HPP_ + +void Hex2Bin(const char* SrcName, const char* DstName, bool IgnoreChecksum); + +#endif /* _IHEXCVT_HPP_ */ diff --git a/host/utils/octoclock_burn_eeprom.cpp b/host/utils/octoclock_burn_eeprom.cpp new file mode 100644 index 000000000..033a8f499 --- /dev/null +++ b/host/utils/octoclock_burn_eeprom.cpp @@ -0,0 +1,95 @@ +// +// Copyright 2014 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#include <uhd/device.hpp> +#include <uhd/utils/safe_main.hpp> +#include <uhd/usrp_clock/octoclock_eeprom.hpp> +#include <uhd/property_tree.hpp> +#include <uhd/types/device_addr.hpp> +#include <boost/algorithm/string.hpp> +#include <boost/program_options.hpp> +#include <boost/format.hpp> +#include <iostream> +#include <vector> + +namespace po = boost::program_options; + +using namespace uhd; +using namespace uhd::usrp_clock; + +int UHD_SAFE_MAIN(int argc, char *argv[]){ + std::string args, input_str, key, val; + + po::options_description desc("Allowed options"); + desc.add_options() + ("help", "help message") + ("args", po::value<std::string>(&args)->default_value(""), "device address args [default = \"\"]") + ("values", po::value<std::string>(&input_str), "keys+values to read/write, separate multiple by \",\"") + ("read-all", "Read all motherboard EEPROM values without writing") + ; + + po::variables_map vm; + po::store(po::parse_command_line(argc, argv, desc), vm); + po::notify(vm); + + //print the help message + if (vm.count("help") or (not vm.count("values") and not vm.count("read-all"))){ + std::cout << boost::format("OctoClock Burn EEPROM %s") % desc << std::endl; + std::cout << boost::format( + "Omit the value argument to perform a readback,\n" + "Or specify a new value to burn into the EEPROM.\n" + ) << std::endl; + return EXIT_FAILURE; + } + + std::cout << "Creating OctoClock device from args: " + args << std::endl; + device::sptr oc = device::make(args, device::CLOCK); + property_tree::sptr tree = oc->get_tree(); + octoclock_eeprom_t oc_eeprom = tree->access<octoclock_eeprom_t>("/mboards/0/eeprom").get(); + std::cout << std::endl; + + std::vector<std::string> keys_vec, vals_vec; + if(vm.count("read-all")) keys_vec = oc_eeprom.keys(); //Leaving vals_vec empty will force utility to only read + else if(vm.count("values")){ + //uhd::device_addr_t properly parses input values + device_addr_t vals(input_str); + keys_vec = vals.keys(); + vals_vec = vals.vals(); + } + else throw std::runtime_error("Must specify --values or --read-all option!"); + + std::cout << "Fetching current settings from EEPROM..." << std::endl; + for(size_t i = 0; i < keys_vec.size(); i++){ + if (not oc_eeprom.has_key(keys_vec[i])){ + std::cerr << boost::format("Cannot find value for EEPROM[\"%s\"]") % keys_vec[i] << std::endl; + return EXIT_FAILURE; + } + std::cout << boost::format(" EEPROM [\"%s\"] is \"%s\"") % keys_vec[i] % oc_eeprom[keys_vec[i]] << std::endl; + } + if(!vm.count("read-all")){ + std::cout << std::endl; + for(size_t i = 0; i < vals_vec.size(); i++){ + if(vals_vec[i] != ""){ + oc_eeprom[keys_vec[i]] = vals_vec[i]; + std::cout << boost::format("Setting EEPROM [\"%s\"] to \"%s\"...") % keys_vec[i] % vals_vec[i] << std::endl; + } + } + tree->access<octoclock_eeprom_t>("/mboards/0/eeprom").set(oc_eeprom); + } + std::cout << std::endl << "Power-cycle your device to allow any changes to take effect." << std::endl; + return EXIT_SUCCESS; +} diff --git a/host/utils/octoclock_firmware_burner.cpp b/host/utils/octoclock_firmware_burner.cpp new file mode 100644 index 000000000..9551ddd20 --- /dev/null +++ b/host/utils/octoclock_firmware_burner.cpp @@ -0,0 +1,370 @@ +// +// Copyright 2014 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#include <algorithm> +#include <csignal> +#include <iostream> +#include <fstream> +#include <stdexcept> +#include <vector> + +#include <boost/foreach.hpp> +#include <boost/asio.hpp> +#include <boost/program_options.hpp> +#include <boost/assign.hpp> +#include <boost/cstdint.hpp> +#include <boost/assign/list_of.hpp> +#include <boost/format.hpp> +#include <boost/filesystem.hpp> +#include <boost/thread.hpp> + +#include <uhd/device.hpp> +#include <uhd/transport/udp_simple.hpp> +#include <uhd/types/device_addr.hpp> +#include <uhd/types/time_spec.hpp> +#include <uhd/utils/byteswap.hpp> +#include <uhd/utils/images.hpp> +#include <uhd/utils/paths.hpp> +#include <uhd/utils/safe_main.hpp> + +#include "../lib/usrp_clock/octoclock/common.h" +#include "ihexcvt.hpp" + +#define MAX_FIRMWARE_SIZE 1024*120 +#define BLOCK_SIZE 256 +#define UDP_TIMEOUT 5 + +namespace fs = boost::filesystem; +namespace po = boost::program_options; + +using namespace uhd; +using namespace uhd::transport; + +static int num_ctrl_c = 0; +void sig_int_handler(int){ + num_ctrl_c++; + if(num_ctrl_c == 1){ + std::cout << std::endl << "Are you sure you want to abort the image burning? If you do, your " + "OctoClock device will be bricked!" << std::endl + << "Press Ctrl+C again to abort the image burning procedure." << std::endl << std::endl; + } + else{ + std::cout << std::endl << "Aborting. Your OctoClock device will be bricked." << std::endl + << "Refer to http://files.ettus.com/manual/page_octoclock.html#bootloader" << std::endl + << "for details on restoring your device." << std::endl; + exit(EXIT_FAILURE); + } +} + +boost::uint8_t firmware_image[MAX_FIRMWARE_SIZE]; +size_t firmware_size = 0; +boost::uint8_t octoclock_data[udp_simple::mtu]; +octoclock_packet_t *pkt_in = reinterpret_cast<octoclock_packet_t *>(octoclock_data); +std::string firmware_path; +size_t num_blocks = 0; + +/* + * Functions + */ +void list_octoclocks(){ + device_addrs_t found_octoclocks = device::find(uhd::device_addr_t(), device::CLOCK); + + std::cout << "Available OctoClock devices:" << std::endl; + BOOST_FOREACH(const device_addr_t &oc, found_octoclocks){ + std::cout << " * " << oc["addr"] << std::endl; + } +} + +/* + * Manually find bootloader. This sends multiple packets in order to increase chances of getting + * bootloader before it switches to the application. + */ +device_addrs_t bootloader_find(const std::string &ip_addr){ + udp_simple::sptr udp_transport = udp_simple::make_connected(ip_addr, BOOST_STRINGIZE(OCTOCLOCK_UDP_CTRL_PORT)); + + octoclock_packet_t pkt_out; + pkt_out.sequence = uhd::htonx<boost::uint32_t>(std::rand()); + pkt_out.code = OCTOCLOCK_QUERY_CMD; + pkt_out.len = 0; + size_t len = 0; + + device_addrs_t addrs; + + boost::system_time comm_timeout = boost::get_system_time() + boost::posix_time::milliseconds(3000); + + while(boost::get_system_time() < comm_timeout){ + UHD_OCTOCLOCK_SEND_AND_RECV(udp_transport, OCTOCLOCK_QUERY_CMD, pkt_out, len, octoclock_data); + if(UHD_OCTOCLOCK_PACKET_MATCHES(OCTOCLOCK_QUERY_ACK, pkt_out, pkt_in, len) and + pkt_in->proto_ver == OCTOCLOCK_BOOTLOADER_PROTO_VER){ + addrs.push_back(device_addr_t()); + addrs[0]["type"] = "octoclock-bootloader"; + addrs[0]["addr"] = udp_transport->get_recv_addr(); + break; + } + } + + return addrs; +} + +void read_firmware(){ + std::ifstream firmware_file(firmware_path.c_str(), std::ios::binary); + firmware_file.seekg(0, std::ios::end); + firmware_size = firmware_file.tellg(); + if(firmware_size > MAX_FIRMWARE_SIZE){ + firmware_file.close(); + throw uhd::runtime_error(str(boost::format("Firmware file too large: %d > %d") + % firmware_size % (MAX_FIRMWARE_SIZE))); + } + firmware_file.seekg(0, std::ios::beg); + firmware_file.read((char*)firmware_image, firmware_size); + firmware_file.close(); + + num_blocks = (firmware_size % BLOCK_SIZE) ? (firmware_size / BLOCK_SIZE) + : ((firmware_size / BLOCK_SIZE) + 1); +} + +void burn_firmware(udp_simple::sptr udp_transport){ + octoclock_packet_t pkt_out; + pkt_out.sequence = uhd::htonx<boost::uint32_t>(std::rand()); + pkt_out.len = uhd::htonx<boost::uint16_t>((boost::uint16_t)firmware_size); + size_t len = 0, current_pos = 0; + + //Tell OctoClock not to jump to application, wait for us instead + std::cout << "Telling OctoClock to prepare for firmware download..." << std::flush; + UHD_OCTOCLOCK_SEND_AND_RECV(udp_transport, PREPARE_FW_BURN_CMD, pkt_out, len, octoclock_data); + if(UHD_OCTOCLOCK_PACKET_MATCHES(FW_BURN_READY_ACK, pkt_out, pkt_in, len)) std::cout << "ready." << std::endl; + else{ + std::cout << std::endl; + throw uhd::runtime_error("Could not get OctoClock in valid state for firmware download."); + } + + std::cout << std::endl << "Burning firmware." << std::endl; + pkt_out.code = FILE_TRANSFER_CMD; + + //Actual burning below + size_t num_tries = 0; + for(size_t i = 0; i < num_blocks; i++){ + num_tries = 0; + pkt_out.sequence++; + pkt_out.addr = i*BLOCK_SIZE; + std::cout << "\r * Progress: " << int(double(i)/double(num_blocks)*100) + << "% (" << (i+1) << "/" << num_blocks << " blocks)" << std::flush; + + memset(pkt_out.data, 0, BLOCK_SIZE); + memcpy((void*)(pkt_out.data), &firmware_image[i*BLOCK_SIZE], std::min(int(firmware_size-current_pos), BLOCK_SIZE)); + + bool success = false; + while(num_tries <= 5){ + UHD_OCTOCLOCK_SEND_AND_RECV(udp_transport, FILE_TRANSFER_CMD, pkt_out, len, octoclock_data); + if(UHD_OCTOCLOCK_PACKET_MATCHES(FILE_TRANSFER_ACK, pkt_out, pkt_in, len)){ + success = true; + break; + } + else{ + num_tries++; + boost::this_thread::sleep(boost::posix_time::milliseconds(100)); + } + } + if(not success){ + std::cout << std::endl; + throw uhd::runtime_error("Failed to burn firmware to OctoClock!"); + } + + current_pos += BLOCK_SIZE; + } + + std::cout << "\r * Progress: 100% (" << num_blocks << "/" << num_blocks << " blocks)" << std::endl; +} + +void verify_firmware(udp_simple::sptr udp_transport){ + octoclock_packet_t pkt_out; + pkt_out.proto_ver = OCTOCLOCK_FW_COMPAT_NUM; + pkt_out.sequence = uhd::htonx<boost::uint32_t>(std::rand()); + size_t len = 0, current_pos = 0; + + + for(size_t i = 0; i < num_blocks; i++){ + pkt_out.sequence++; + pkt_out.addr = i*BLOCK_SIZE; + std::cout << "\r * Progress: " << int(double(i)/double(num_blocks)*100) + << "% (" << (i+1) << "/" << num_blocks << " blocks)" << std::flush; + + UHD_OCTOCLOCK_SEND_AND_RECV(udp_transport, READ_FW_CMD, pkt_out, len, octoclock_data); + if(UHD_OCTOCLOCK_PACKET_MATCHES(READ_FW_ACK, pkt_out, pkt_in, len)){ + if(memcmp((void*)(pkt_in->data), &firmware_image[i*BLOCK_SIZE], + std::min(int(firmware_size-current_pos), BLOCK_SIZE))){ + std::cout << std::endl; + throw uhd::runtime_error("Failed to verify OctoClock firmware!"); + } + } + else{ + std::cout << std::endl; + throw uhd::runtime_error("Failed to verify OctoClock firmware!"); + } + } + + std::cout << "\r * Progress: 100% (" << num_blocks << "/" << num_blocks << " blocks)" << std::endl; +} + +bool reset_octoclock(const std::string &ip_addr){ + udp_simple::sptr udp_transport = udp_simple::make_connected(ip_addr, BOOST_STRINGIZE(OCTOCLOCK_UDP_CTRL_PORT)); + + octoclock_packet_t pkt_out; + pkt_out.sequence = uhd::htonx<boost::uint32_t>(std::rand()); + size_t len; + + UHD_OCTOCLOCK_SEND_AND_RECV(udp_transport, RESET_CMD, pkt_out, len, octoclock_data); + if(not UHD_OCTOCLOCK_PACKET_MATCHES(RESET_ACK, pkt_out, pkt_in, len)){ + std::cout << std::endl; + throw uhd::runtime_error("Failed to place device in state to receive firmware."); + } + + boost::this_thread::sleep(boost::posix_time::milliseconds(3000)); + return (bootloader_find(ip_addr).size() == 1); +} + +void finalize(udp_simple::sptr udp_transport){ + octoclock_packet_t pkt_out; + pkt_out.len = 0; + pkt_out.sequence = uhd::htonx<boost::uint32_t>(std::rand()); + size_t len = 0; + + UHD_OCTOCLOCK_SEND_AND_RECV(udp_transport, FINALIZE_BURNING_CMD, pkt_out, len, octoclock_data); + if(not UHD_OCTOCLOCK_PACKET_MATCHES(FINALIZE_BURNING_ACK, pkt_out, pkt_in, len)){ + std::cout << std::endl; + std::cout << "no ACK. Bootloader may not have loaded application." << std::endl; + } +} + +int UHD_SAFE_MAIN(int argc, char *argv[]){ + std::string ip_addr; + po::options_description desc("Allowed options"); + desc.add_options() + ("help", "Display this help message.") + ("addr", po::value<std::string>(&ip_addr), "Specify an IP address.") + ("fw-path", po::value<std::string>(&firmware_path), "Specify a custom firmware path.") + ("list", "List all available OctoClock devices.") + ; + po::variables_map vm; + po::store(po::parse_command_line(argc, argv, desc), vm); + po::notify(vm); + + //Print help message + if(vm.count("help")){ + std::cout << "OctoClock Firmware Burner" << std::endl << std::endl; + + std::cout << "Burns a firmware image file onto an OctoClock device. Specify" << std::endl + << "the address of the OctoClock with the --addr option. To burn" << std::endl + << "a custom firmware image, use the --fw-path option. Otherwise, the" << std::endl + << "utility will use the default image. To list all available" << std::endl + << "OctoClock devices without burning firmware, use the --list" << std::endl + << "option." << std::endl << std::endl; + + std::cout << desc << std::endl; + return EXIT_SUCCESS; + } + + //List all available devices + if(vm.count("list")){ + list_octoclocks(); + return EXIT_SUCCESS; + } + + if(not (vm.count("addr"))){ + throw uhd::runtime_error("You must specify an address with the --addr option!"); + } + udp_simple::sptr udp_transport = udp_simple::make_connected(ip_addr, BOOST_STRINGIZE(OCTOCLOCK_UDP_FW_PORT)); + + //If custom path given, make sure it exists + if(vm.count("fw-path")){ + //Expand tilde usage if applicable + #ifndef UHD_PLATFORM_WIN32 + if(firmware_path.find("~/") == 0) firmware_path.replace(0,1,getenv("HOME")); + #endif + + if(not fs::exists(firmware_path)){ + throw uhd::runtime_error(str(boost::format("This filepath does not exist: %s") % firmware_path)); + } + } + else firmware_path = find_image_path("octoclock_r4_fw.bin"); + + //If Intel hex file detected, convert to binary + std::string ext = fs::extension(firmware_path); + if(ext == ".hex"){ + std::cout << "Found firmware at path: " << firmware_path << std::endl; + + //Write firmware .bin file to temporary directory + fs::path temp_bin = fs::path(fs::path(get_tmp_path()) / str(boost::format("octoclock_fw_%d.bin") + % time_spec_t::get_system_time().get_full_secs())); + Hex2Bin(firmware_path.c_str(), temp_bin.string().c_str(), false); + + firmware_path = temp_bin.string(); + } + else if(ext == ".bin"){ + std::cout << "Found firmware at path: " << firmware_path << std::endl; + } + else throw uhd::runtime_error("The firmware file has in improper extension (must be .hex or .bin)."); + + std::cout << std::endl << boost::format("Searching for OctoClock with IP address %s...") % ip_addr << std::flush; + device_addrs_t octoclocks = device::find(str(boost::format("addr=%s") % ip_addr), device::CLOCK); + if(octoclocks.size() == 1){ + if(octoclocks[0]["type"] == "octoclock"){ + std::cout << "found. Resetting..." << std::flush; + if(reset_octoclock(ip_addr)) std::cout << "successful." << std::endl; + else{ + std::cout << "failed." << std::endl; + throw uhd::runtime_error("Failed to reset OctoClock device into its bootloader."); + } + } + else std::cout << "found." << std::endl; + } + else{ + std::cout << "failed." << std::endl; + throw uhd::runtime_error("Could not find OctoClock with given IP address!"); + } + + read_firmware(); + + std::signal(SIGINT, &sig_int_handler); + + burn_firmware(udp_transport); + std::cout << "Verifying firmware." << std::endl; + verify_firmware(udp_transport); + std::cout << std::endl << "Telling OctoClock bootloader to load application..." << std::flush; + finalize(udp_transport); + std::cout << "done." << std::endl; + + std::cout << "Waiting for OctoClock to reinitialize..." << std::flush; + boost::this_thread::sleep(boost::posix_time::milliseconds(5000)); + octoclocks = device::find(str(boost::format("addr=%s") % ip_addr), device::CLOCK); + if(octoclocks.size() == 1){ + if(octoclocks[0]["type"] == "octoclock-bootloader"){ + std::cout << std::endl; + throw uhd::runtime_error("OctoClock failed to leave bootloader state."); + } + else{ + std::cout << "found." << std::endl << std::endl + << "Successfully burned firmware." << std::endl << std::endl; + } + } + else{ + std::cout << std::endl; + throw uhd::runtime_error("Failed to reinitialize OctoClock."); + } + + return EXIT_SUCCESS; +} diff --git a/host/utils/uhd_usrp_probe.cpp b/host/utils/uhd_usrp_probe.cpp index 98ed84850..cfbfe5f20 100644 --- a/host/utils/uhd_usrp_probe.cpp +++ b/host/utils/uhd_usrp_probe.cpp @@ -192,6 +192,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ ("args", po::value<std::string>()->default_value(""), "device address args") ("tree", "specify to print a complete property tree") ("string", po::value<std::string>(), "query a string value from the properties tree") + ("init-only", "skip all queries, only initialize device") ; po::variables_map vm; @@ -209,7 +210,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ return EXIT_SUCCESS; } - device::sptr dev = device::make(vm["args"].as<std::string>()); + device::sptr dev = device::make(vm["args"].as<std::string>(), device::USRP); property_tree::sptr tree = dev->get_tree(); if (vm.count("string")){ @@ -218,7 +219,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ } if (vm.count("tree") != 0) print_tree("/", tree); - else std::cout << make_border(get_device_pp_string(tree)) << std::endl; + else if (not vm.count("init-only")) std::cout << make_border(get_device_pp_string(tree)) << std::endl; return EXIT_SUCCESS; } diff --git a/host/utils/usrp_burn_db_eeprom.cpp b/host/utils/usrp_burn_db_eeprom.cpp index 3ca953115..7b483d2e7 100644 --- a/host/utils/usrp_burn_db_eeprom.cpp +++ b/host/utils/usrp_burn_db_eeprom.cpp @@ -62,7 +62,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ } //make the device and extract the dboard w/ property - device::sptr dev = device::make(args); + device::sptr dev = device::make(args, device::USRP); uhd::property_tree::sptr tree = dev->get_tree(); const uhd::fs_path db_root = "/mboards/0/dboards"; std::vector<std::string> dboard_names = tree->list(db_root); diff --git a/host/utils/usrp_burn_mb_eeprom.cpp b/host/utils/usrp_burn_mb_eeprom.cpp index f3e12c765..92df9d7d4 100644 --- a/host/utils/usrp_burn_mb_eeprom.cpp +++ b/host/utils/usrp_burn_mb_eeprom.cpp @@ -1,5 +1,5 @@ // -// Copyright 2010,2013 Ettus Research LLC +// Copyright 2010,2013-2014 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -19,6 +19,7 @@ #include <uhd/device.hpp> #include <uhd/property_tree.hpp> #include <uhd/usrp/mboard_eeprom.hpp> +#include <uhd/types/device_addr.hpp> #include <boost/algorithm/string.hpp> #include <boost/program_options.hpp> #include <boost/format.hpp> @@ -28,14 +29,16 @@ namespace po = boost::program_options; int UHD_SAFE_MAIN(int argc, char *argv[]){ - std::string args, key, val; + std::string args, input_str, key, val; po::options_description desc("Allowed options"); desc.add_options() ("help", "help message") ("args", po::value<std::string>(&args)->default_value(""), "device address args [default = \"\"]") - ("key", po::value<std::string>(&key), "identifiers for new values in EEPROM, separate multiple by \",\"") - ("val", po::value<std::string>(&val), "the new values to set, omit for readback, separate multiple by \",\"") + ("values", po::value<std::string>(&input_str), "keys+values to read/write, separate multiple by \",\"") + ("key", po::value<std::string>(&key), "identifiers for new values in EEPROM, separate multiple by \",\" (DEPRECATED)") + ("val", po::value<std::string>(&val), "the new values to set, omit for readback, separate multiple by \",\" (DEPRECATED)") + ("read-all", "Read all motherboard EEPROM values without writing") ; po::variables_map vm; @@ -43,7 +46,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ po::notify(vm); //print the help message - if (vm.count("help") or not vm.count("key")){ + if (vm.count("help") or (not vm.count("key") and not vm.count("values") and not vm.count("read-all"))){ std::cout << boost::format("USRP Burn Motherboard EEPROM %s") % desc << std::endl; std::cout << boost::format( "Omit the value argument to perform a readback,\n" @@ -53,25 +56,35 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ } std::cout << "Creating USRP device from address: " + args << std::endl; - uhd::device::sptr dev = uhd::device::make(args); + uhd::device::sptr dev = uhd::device::make(args, uhd::device::USRP); uhd::property_tree::sptr tree = dev->get_tree(); + uhd::usrp::mboard_eeprom_t mb_eeprom = tree->access<uhd::usrp::mboard_eeprom_t>("/mboards/0/eeprom").get(); std::cout << std::endl; - //remove whitespace, split arguments and values - boost::algorithm::erase_all(key, " "); - boost::algorithm::erase_all(val, " "); - std::vector<std::string> keys_vec, vals_vec; - boost::split(keys_vec, key, boost::is_any_of("\"',")); - boost::split(vals_vec, val, boost::is_any_of("\"',")); + if(vm.count("read-all")) keys_vec = mb_eeprom.keys(); //Leaving vals_vec empty will force utility to only read + else if(vm.count("values")){ + //uhd::device_addr_t properly parses input values + uhd::device_addr_t vals(input_str); + keys_vec = vals.keys(); + vals_vec = vals.vals(); + } + else{ + std::cout << "WARNING: Use of --key and --val is deprecated!" << std::endl; + //remove whitespace, split arguments and values + boost::algorithm::erase_all(key, " "); + boost::algorithm::erase_all(val, " "); + + boost::split(keys_vec, key, boost::is_any_of("\"',")); + boost::split(vals_vec, val, boost::is_any_of("\"',")); - if((keys_vec.size() != vals_vec.size()) and val != "") { - //If zero values are given, then user just wants values read to them - throw std::runtime_error("Number of keys must match number of values!"); + if((keys_vec.size() != vals_vec.size()) and val != "") { + //If zero values are given, then user just wants values read to them + throw std::runtime_error("Number of keys must match number of values!"); + } } std::cout << "Fetching current settings from EEPROM..." << std::endl; - uhd::usrp::mboard_eeprom_t mb_eeprom = tree->access<uhd::usrp::mboard_eeprom_t>("/mboards/0/eeprom").get(); for(size_t i = 0; i < keys_vec.size(); i++){ if (not mb_eeprom.has_key(keys_vec[i])){ std::cerr << boost::format("Cannot find value for EEPROM[%s]") % keys_vec[i] << std::endl; @@ -80,16 +93,16 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ std::cout << boost::format(" EEPROM [\"%s\"] is \"%s\"") % keys_vec[i] % mb_eeprom[keys_vec[i]] << std::endl; } std::cout << std::endl; - if (vm.count("val")){ - mb_eeprom = uhd::usrp::mboard_eeprom_t(); - for(size_t i = 0; i < vals_vec.size(); i++){ + mb_eeprom = uhd::usrp::mboard_eeprom_t(); + for(size_t i = 0; i < vals_vec.size(); i++){ + if(vals_vec[i] != ""){ mb_eeprom[keys_vec[i]] = vals_vec[i]; std::cout << boost::format("Setting EEPROM [\"%s\"] to \"%s\"...") % keys_vec[i] % vals_vec[i] << std::endl; } - tree->access<uhd::usrp::mboard_eeprom_t>("/mboards/0/eeprom").set(mb_eeprom); - std::cout << "Power-cycle the USRP device for the changes to take effect." << std::endl; - std::cout << std::endl; } + tree->access<uhd::usrp::mboard_eeprom_t>("/mboards/0/eeprom").set(mb_eeprom); + std::cout << "Power-cycle the USRP device for the changes to take effect." << std::endl; + std::cout << std::endl; std::cout << "Done" << std::endl; return EXIT_SUCCESS; diff --git a/host/utils/usrp_n2xx_simple_net_burner.cpp b/host/utils/usrp_n2xx_simple_net_burner.cpp index 2a766a345..fe437a2e5 100644 --- a/host/utils/usrp_n2xx_simple_net_burner.cpp +++ b/host/utils/usrp_n2xx_simple_net_burner.cpp @@ -57,9 +57,11 @@ using namespace uhd::transport; #define FLASH_DATA_PACKET_SIZE 256 #define FPGA_IMAGE_SIZE_BYTES 1572864 #define FW_IMAGE_SIZE_BYTES 31744 + #define PROD_FPGA_IMAGE_LOCATION_ADDR 0x00180000 -#define PROD_FW_IMAGE_LOCATION_ADDR 0x00300000 #define SAFE_FPGA_IMAGE_LOCATION_ADDR 0x00000000 + +#define PROD_FW_IMAGE_LOCATION_ADDR 0x00300000 #define SAFE_FW_IMAGE_LOCATION_ADDR 0x003F0000 typedef enum { @@ -113,6 +115,7 @@ typedef struct { //Mapping revision numbers to filenames uhd::dict<boost::uint32_t, std::string> filename_map = boost::assign::map_list_of + (0, "N2XX") (0xa, "n200_r3") (0x100a, "n200_r4") (0x10a, "n210_r3") @@ -181,25 +184,39 @@ void list_usrps(){ /*********************************************************************** * Find USRP N2XX with specified IP address and return type **********************************************************************/ -boost::uint32_t find_usrp(udp_simple::sptr udp_transport){ +boost::uint32_t find_usrp(udp_simple::sptr udp_transport, bool check_rev){ boost::uint32_t hw_rev; bool found_it = false; + // If the user chooses to not care about the rev, simply check + // for the presence of a USRP N2XX. + boost::uint32_t cmd_id = (check_rev) ? GET_HW_REV_CMD + : USRP2_QUERY; + boost::uint32_t ack_id = (check_rev) ? GET_HW_REV_ACK + : USRP2_ACK; + const usrp2_fw_update_data_t *update_data_in = reinterpret_cast<const usrp2_fw_update_data_t *>(usrp2_update_data_in_mem); usrp2_fw_update_data_t hw_info_pkt = usrp2_fw_update_data_t(); hw_info_pkt.proto_ver = htonx<boost::uint32_t>(USRP2_FW_PROTO_VERSION); - hw_info_pkt.id = htonx<boost::uint32_t>(GET_HW_REV_CMD); + hw_info_pkt.id = htonx<boost::uint32_t>(cmd_id); udp_transport->send(boost::asio::buffer(&hw_info_pkt, sizeof(hw_info_pkt))); //Loop and receive until the timeout size_t len = udp_transport->recv(boost::asio::buffer(usrp2_update_data_in_mem), UDP_TIMEOUT); - if(len > offsetof(usrp2_fw_update_data_t, data) and ntohl(update_data_in->id) == GET_HW_REV_ACK){ + if(len > offsetof(usrp2_fw_update_data_t, data) and ntohl(update_data_in->id) == ack_id){ hw_rev = ntohl(update_data_in->data.hw_rev); if(filename_map.has_key(hw_rev)){ std::cout << boost::format("Found %s.\n\n") % filename_map[hw_rev]; found_it = true; } - else throw std::runtime_error("Invalid revision found."); + else{ + if(check_rev) throw std::runtime_error("Invalid revision found."); + else{ + hw_rev = 0; + std::cout << "Found USRP N2XX." << std::endl; + found_it = true; + } + } } if(not found_it) throw std::runtime_error("No USRP N2XX found."); @@ -210,27 +227,27 @@ boost::uint32_t find_usrp(udp_simple::sptr udp_transport){ * Custom filename validation functions **********************************************************************/ -void validate_custom_fpga_file(std::string rev_str, std::string& fpga_path){ +void validate_custom_fpga_file(std::string rev_str, std::string& fpga_path, bool check_rev){ //Check for existence of file if(not fs::exists(fpga_path)) throw std::runtime_error(str(boost::format("No file at specified FPGA path: %s") % fpga_path)); - //Check to find rev_str in filename + //If user cares about revision, use revision string to detect invalid image filename uhd::fs_path custom_fpga_path(fpga_path); - if(custom_fpga_path.leaf().find(rev_str) == std::string::npos){ + if(custom_fpga_path.leaf().find(rev_str) == std::string::npos and check_rev){ throw std::runtime_error(str(boost::format("Invalid FPGA image filename at path: %s\nFilename must contain '%s' to be considered valid for this model.") % fpga_path % rev_str)); } } -void validate_custom_fw_file(std::string rev_str, std::string& fw_path){ +void validate_custom_fw_file(std::string rev_str, std::string& fw_path, bool check_rev){ //Check for existence of file if(not fs::exists(fw_path)) throw std::runtime_error(str(boost::format("No file at specified firmware path: %s") % fw_path)); - //Check to find truncated rev_str in filename + //If user cares about revision, use revision string to detect invalid image filename uhd::fs_path custom_fw_path(fw_path); - if(custom_fw_path.leaf().find(erase_tail_copy(rev_str,3)) == std::string::npos){ + if(custom_fw_path.leaf().find(erase_tail_copy(rev_str,3)) == std::string::npos and check_rev){ throw std::runtime_error(str(boost::format("Invalid firmware image filename at path: %s\nFilename must contain '%s' to be considered valid for this model.") % fw_path % erase_tail_copy(rev_str,3))); } @@ -329,10 +346,12 @@ boost::uint32_t* get_flash_info(std::string& ip_addr){ * Image burning functions **********************************************************************/ -void erase_image(udp_simple::sptr udp_transport, bool is_fw, boost::uint32_t memory_size){ +void erase_image(udp_simple::sptr udp_transport, bool is_fw, boost::uint32_t memory_size, bool overwrite_safe){ - boost::uint32_t image_location_addr = is_fw ? PROD_FW_IMAGE_LOCATION_ADDR - : PROD_FPGA_IMAGE_LOCATION_ADDR; + boost::uint32_t image_location_addr = is_fw ? overwrite_safe ? SAFE_FW_IMAGE_LOCATION_ADDR + : PROD_FW_IMAGE_LOCATION_ADDR + : overwrite_safe ? SAFE_FPGA_IMAGE_LOCATION_ADDR + : PROD_FPGA_IMAGE_LOCATION_ADDR; boost::uint32_t image_size = is_fw ? FW_IMAGE_SIZE_BYTES : FPGA_IMAGE_SIZE_BYTES; @@ -378,10 +397,13 @@ void erase_image(udp_simple::sptr udp_transport, bool is_fw, boost::uint32_t mem } } -void write_image(udp_simple::sptr udp_transport, bool is_fw, boost::uint8_t* image, boost::uint32_t memory_size, int image_size){ +void write_image(udp_simple::sptr udp_transport, bool is_fw, boost::uint8_t* image, + boost::uint32_t memory_size, int image_size, bool overwrite_safe){ - boost::uint32_t begin_addr = is_fw ? PROD_FW_IMAGE_LOCATION_ADDR - : PROD_FPGA_IMAGE_LOCATION_ADDR; + boost::uint32_t begin_addr = is_fw ? overwrite_safe ? SAFE_FW_IMAGE_LOCATION_ADDR + : PROD_FW_IMAGE_LOCATION_ADDR + : overwrite_safe ? SAFE_FPGA_IMAGE_LOCATION_ADDR + : PROD_FPGA_IMAGE_LOCATION_ADDR; boost::uint32_t current_addr = begin_addr; std::string type = is_fw ? "firmware" : "FPGA"; @@ -418,11 +440,14 @@ void write_image(udp_simple::sptr udp_transport, bool is_fw, boost::uint8_t* ima std::cout << boost::format(" * Successfully wrote %d bytes.\n") % image_size; } -void verify_image(udp_simple::sptr udp_transport, bool is_fw, boost::uint8_t* image, boost::uint32_t memory_size, int image_size){ +void verify_image(udp_simple::sptr udp_transport, bool is_fw, boost::uint8_t* image, + boost::uint32_t memory_size, int image_size, bool overwrite_safe){ int current_index = 0; - boost::uint32_t begin_addr = is_fw ? PROD_FW_IMAGE_LOCATION_ADDR - : PROD_FPGA_IMAGE_LOCATION_ADDR; + boost::uint32_t begin_addr = is_fw ? overwrite_safe ? SAFE_FW_IMAGE_LOCATION_ADDR + : PROD_FW_IMAGE_LOCATION_ADDR + : overwrite_safe ? SAFE_FPGA_IMAGE_LOCATION_ADDR + : PROD_FPGA_IMAGE_LOCATION_ADDR; boost::uint32_t current_addr = begin_addr; std::string type = is_fw ? "firmware" : "FPGA"; @@ -501,6 +526,8 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ ("no_fw", "Do not burn a firmware image (DEPRECATED).") ("no-fpga", "Do not burn an FPGA image.") ("no_fpga", "Do not burn an FPGA image (DEPRECATED).") + ("overwrite-safe", "Overwrite safe images (not recommended).") + ("dont-check-rev", "Don't verify images are for correct model before burning.") ("auto-reboot", "Automatically reboot N2XX without prompting.") ("auto_reboot", "Automatically reboot N2XX without prompting (DEPRECATED).") ("list", "List available N2XX USRP devices.") @@ -518,25 +545,52 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ return EXIT_SUCCESS; } - //List option + //List options if(vm.count("list")){ list_usrps(); return EXIT_SUCCESS; } - //Process user options + //Store user options bool burn_fpga = (vm.count("no-fpga") == 0) and (vm.count("no_fpga") == 0); bool burn_fw = (vm.count("no-fw") == 0) and (vm.count("no_fw") == 0); bool use_custom_fpga = (vm.count("fpga") > 0); bool use_custom_fw = (vm.count("fw") > 0); bool auto_reboot = (vm.count("auto-reboot") > 0) or (vm.count("auto_reboot") > 0); + bool check_rev = (vm.count("dont-check-rev") == 0); + bool overwrite_safe = (vm.count("overwrite-safe") > 0); int fpga_image_size = 0; int fw_image_size = 0; + //Process options and detect invalid option combinations if(not burn_fpga && not burn_fw){ std::cout << "No images will be burned." << std::endl; return EXIT_FAILURE; } + if(not check_rev){ + //Without knowing a revision, the utility cannot automatically generate a filepath, so the user + //must specify one. The user must also burn both types of images for consistency. + if(not (burn_fpga and burn_fw)) + throw std::runtime_error("If the --dont-check-rev option is used, both FPGA and firmware images need to be burned."); + if(not (use_custom_fpga and use_custom_fw)) + throw std::runtime_error("If the --dont-check-rev option is used, the user must specify image filepaths."); + } + if(overwrite_safe){ + //If the user specifies overwriting safe images, both image types must be burned for consistency. + if(not (burn_fpga and burn_fw)) + throw std::runtime_error("If the --overwrite-safe option is used, both FPGA and firmware images need to be burned."); + + std::cout << "Are you REALLY sure you want to overwrite the safe images?" << std::endl; + std::cout << "This is ALMOST ALWAYS a terrible idea." << std::endl; + std::cout << "Type \"yes\" to continue, or anything else to quit: " << std::flush; + std::string safe_response; + std::getline(std::cin, safe_response); + if(safe_response != "yes"){ + std::cout << "Exiting." << std::endl; + return EXIT_SUCCESS; + } + else std::cout << std::endl; //Formatting + } //Print deprecation messages if necessary if(vm.count("no_fpga") > 0) std::cout << "WARNING: --no_fpga option is deprecated! Use --no-fpga instead." << std::endl << std::endl; @@ -546,7 +600,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ //Find USRP and establish connection std::cout << boost::format("Searching for USRP N2XX with IP address %s.\n") % ip_addr; udp_simple::sptr udp_transport = udp_simple::make_connected(ip_addr, BOOST_STRINGIZE(USRP2_UDP_UPDATE_PORT)); - boost::uint32_t hw_rev = find_usrp(udp_transport); + boost::uint32_t hw_rev = find_usrp(udp_transport, check_rev); //Check validity of file locations and binaries before attempting burn std::cout << "Searching for specified images." << std::endl << std::endl; @@ -556,7 +610,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ #ifndef UHD_PLATFORM_WIN32 if(fpga_path.find("~/") == 0) fpga_path.replace(0,1,getenv("HOME")); #endif - validate_custom_fpga_file(filename_map[hw_rev], fpga_path); + validate_custom_fpga_file(filename_map[hw_rev], fpga_path, check_rev); } else{ std::string default_fpga_filename = str(boost::format("usrp_%s_fpga.bin") % filename_map[hw_rev]); @@ -571,7 +625,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ #ifndef UHD_PLATFORM_WIN32 if(fw_path.find("~/") == 0) fw_path.replace(0,1,getenv("HOME")); #endif - validate_custom_fw_file(filename_map[hw_rev], fw_path); + validate_custom_fw_file(filename_map[hw_rev], fw_path, check_rev); } else{ std::string default_fw_filename = str(boost::format("usrp_%s_fw.bin") % erase_tail_copy(filename_map[hw_rev],3)); @@ -594,15 +648,15 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ //Burning images std::signal(SIGINT, &sig_int_handler); if(burn_fpga){ - erase_image(udp_transport, false, flash_info[1]); - write_image(udp_transport, false, fpga_image, flash_info[1], fpga_image_size); - verify_image(udp_transport, false, fpga_image, flash_info[1], fpga_image_size); + erase_image(udp_transport, false, flash_info[1], overwrite_safe); + write_image(udp_transport, false, fpga_image, flash_info[1], fpga_image_size, overwrite_safe); + verify_image(udp_transport, false, fpga_image, flash_info[1], fpga_image_size, overwrite_safe); } if(burn_fpga and burn_fw) std::cout << std::endl; //Formatting if(burn_fw){ - erase_image(udp_transport, true, flash_info[1]); - write_image(udp_transport, true, fw_image, flash_info[1], fw_image_size); - verify_image(udp_transport, true, fw_image, flash_info[1], fw_image_size); + erase_image(udp_transport, true, flash_info[1], overwrite_safe); + write_image(udp_transport, true, fw_image, flash_info[1], fw_image_size, overwrite_safe); + verify_image(udp_transport, true, fw_image, flash_info[1], fw_image_size, overwrite_safe); } delete(flash_info); diff --git a/host/utils/usrp_x3xx_fpga_burner.cpp b/host/utils/usrp_x3xx_fpga_burner.cpp index ea24c4c15..b849cfb92 100644 --- a/host/utils/usrp_x3xx_fpga_burner.cpp +++ b/host/utils/usrp_x3xx_fpga_burner.cpp @@ -118,7 +118,7 @@ boost::uint8_t bitswap(uint8_t b){ } void list_usrps(){ - device_addrs_t found_devices = device::find(device_addr_t("type=x300")); + device_addrs_t found_devices = device::find(device_addr_t("type=x300"), device::USRP); std::cout << "Available X3x0 devices:" << std::endl; BOOST_FOREACH(const device_addr_t &dev, found_devices){ @@ -142,7 +142,7 @@ void list_usrps(){ device_addr_t find_usrp_with_ethernet(std::string ip_addr, bool output){ if(output) std::cout << "Attempting to find X3x0 with IP address: " << ip_addr << std::endl; const device_addr_t dev = device_addr_t(str(boost::format("addr=%s") % ip_addr)); - device_addrs_t found_devices = device::find(dev); + device_addrs_t found_devices = device::find(dev, device::USRP); if(found_devices.size() < 1) { throw std::runtime_error("Could not find X3x0 with the specified address!"); @@ -161,7 +161,7 @@ device_addr_t find_usrp_with_ethernet(std::string ip_addr, bool output){ device_addr_t find_usrp_with_pcie(std::string resource, bool output){ if(output) std::cout << "Attempting to find X3x0 with resource: " << resource << std::endl; const device_addr_t dev = device_addr_t(str(boost::format("resource=%s") % resource)); - device_addrs_t found_devices = device::find(dev); + device_addrs_t found_devices = device::find(dev, device::USRP); if(found_devices.size() < 1) { throw std::runtime_error("Could not find X3x0 with the specified resource!"); diff --git a/images/Makefile b/images/Makefile index 6b1cfcfc4..85501459a 100644 --- a/images/Makefile +++ b/images/Makefile @@ -289,13 +289,14 @@ endif ifdef HAS_AVR_UTILS _octoclock_fw_dir = $(TOP_FW_DIR)/octoclock -_octoclock_fw_bin = $(BUILT_IMAGES_DIR)/octoclock_fw.hex +_octoclock_fw_bin = $(BUILT_IMAGES_DIR)/octoclock_r4_fw.hex IMAGES_LIST += $(_octoclock_fw_bin) $(_octoclock_fw_bin): $(GLOBAL_DEPS) - cd $(_octoclock_fw_dir) && make -f Makefile clean - cd $(_octoclock_fw_dir) && make -f Makefile all - cp $(TOP_FW_DIR)/octoclock/octoclock_fw.hex $@ + cd $(_octoclock_fw_dir) && mkdir build + cd $(_octoclock_fw_dir)/build && cmake .. + cd $(_octoclock_fw_dir)/build && make + cp $(TOP_FW_DIR)/octoclock/build/octoclock_r4_fw.hex $@ endif ######################################################################## |
