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-rw-r--r--usrp2/control_lib/Makefile.srcs1
-rw-r--r--usrp2/control_lib/bootram.v246
-rw-r--r--usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v4
-rw-r--r--usrp2/top/u2plus/u2plus.v6
-rw-r--r--usrp2/top/u2plus/u2plus_core.v72
5 files changed, 289 insertions, 40 deletions
diff --git a/usrp2/control_lib/Makefile.srcs b/usrp2/control_lib/Makefile.srcs
index 60fb2516d..ad491b83d 100644
--- a/usrp2/control_lib/Makefile.srcs
+++ b/usrp2/control_lib/Makefile.srcs
@@ -44,4 +44,5 @@ longfifo.v \
shortfifo.v \
medfifo.v \
s3a_icap_wb.v \
+bootram.v \
))
diff --git a/usrp2/control_lib/bootram.v b/usrp2/control_lib/bootram.v
new file mode 100644
index 000000000..648ccc9ed
--- /dev/null
+++ b/usrp2/control_lib/bootram.v
@@ -0,0 +1,246 @@
+
+// Boot RAM for S3A, 8KB, dual port
+
+// RAMB16BWE_S36_S36: 512 x 32 + 4 Parity bits byte-wide write Dual-Port RAM
+// Spartan-3A Xilinx HDL Libraries Guide, version 10.1.1
+
+module bootram
+ (input clk,
+ input [12:0] if_adr,
+ output [31:0] if_data,
+
+ input [12:0] dwb_adr_i,
+ input [31:0] dwb_dat_i,
+ output [31:0] dwb_dat_o,
+ input dwb_we_i,
+ output reg dwb_ack_o,
+ input dwb_stb_i,
+ input [3:0] dwb_sel_i);
+
+ wire [31:0] DOA0, DOA1, DOA2, DOA3;
+ wire [31:0] DOB0, DOB1, DOB2, DOB3;
+ wire ENB0, ENB1, ENB2, ENB3;
+ wire [3:0] WEB;
+
+ assign if_data = if_adr[12] ? (if_adr[11] ? DOA3 : DOA2) : (if_adr[11] ? DOA1 : DOA0);
+ assign dwb_dat_o = dwb_adr_i[12] ? (dwb_adr_i[11] ? DOA3 : DOA2) : (dwb_adr_i[11] ? DOA1 : DOA0);
+
+ always @(posedge clk)
+ if(dwb_stb_i & ~dwb_ack_o)
+ dwb_ack_o <= 1;
+ else
+ dwb_ack_o <= 0;
+
+ assign ENB0 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b00);
+ assign ENB1 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b01);
+ assign ENB2 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b10);
+ assign ENB3 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b11);
+
+ assign WEB = {4{dwb_we_i}} & dwb_sel_i;
+
+ RAMB16BWE_S36_S36
+ #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+ .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+ .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+ .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+ .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
+ .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ RAM0
+ (.DOA(DOA0), // Port A 32-bit Data Output
+ .DOPA(), // Port A 4-bit Parity Output
+ .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+ .CLKA(clk), // Port A 1-bit Clock
+ .DIA(32'd0), // Port A 32-bit Data Input
+ .DIPA(4'd0), // Port A 4-bit parity Input
+ .ENA(1'b1), // Port A 1-bit RAM Enable Input
+ .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
+ .WEA(1'b0), // Port A 4-bit Write Enable Input
+
+ .DOB(DOB0), // Port B 32-bit Data Output
+ .DOPB(), // Port B 4-bit Parity Output
+ .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+ .CLKB(clk), // Port B 1-bit Clock
+ .DIB(dwb_dat_i), // Port B 32-bit Data Input
+ .DIPB(4'd0), // Port-B 4-bit parity Input
+ .ENB(ENB0), // Port B 1-bit RAM Enable Input
+ .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
+ .WEB(WEB) // Port B 4-bit Write Enable Input
+ ); // End of RAMB16BWE_S36_S36_inst instantiation
+
+ RAMB16BWE_S36_S36
+ #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+ .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+ .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+ .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+ .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
+ .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ RAM1
+ (.DOA(DOA1), // Port A 32-bit Data Output
+ .DOPA(), // Port A 4-bit Parity Output
+ .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+ .CLKA(clk), // Port A 1-bit Clock
+ .DIA(32'd0), // Port A 32-bit Data Input
+ .DIPA(4'd0), // Port A 4-bit parity Input
+ .ENA(1'b1), // Port A 1-bit RAM Enable Input
+ .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
+ .WEA(1'b0), // Port A 4-bit Write Enable Input
+
+ .DOB(DOB1), // Port B 32-bit Data Output
+ .DOPB(), // Port B 4-bit Parity Output
+ .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+ .CLKB(clk), // Port B 1-bit Clock
+ .DIB(dwb_dat_i), // Port B 32-bit Data Input
+ .DIPB(4'd0), // Port-B 4-bit parity Input
+ .ENB(ENB1), // Port B 1-bit RAM Enable Input
+ .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
+ .WEB(WEB) // Port B 4-bit Write Enable Input
+ ); // End of RAMB16BWE_S36_S36_inst instantiation
+
+ RAMB16BWE_S36_S36
+ #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+ .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+ .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+ .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+ .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
+ .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ RAM2
+ (.DOA(DOA2), // Port A 32-bit Data Output
+ .DOPA(), // Port A 4-bit Parity Output
+ .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+ .CLKA(clk), // Port A 1-bit Clock
+ .DIA(32'd0), // Port A 32-bit Data Input
+ .DIPA(4'd0), // Port A 4-bit parity Input
+ .ENA(1'b1), // Port A 1-bit RAM Enable Input
+ .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
+ .WEA(1'b0), // Port A 4-bit Write Enable Input
+
+ .DOB(DOB2), // Port B 32-bit Data Output
+ .DOPB(), // Port B 4-bit Parity Output
+ .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+ .CLKB(clk), // Port B 1-bit Clock
+ .DIB(dwb_dat_i), // Port B 32-bit Data Input
+ .DIPB(4'd0), // Port-B 4-bit parity Input
+ .ENB(ENB2), // Port B 1-bit RAM Enable Input
+ .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
+ .WEB(WEB) // Port B 4-bit Write Enable Input
+ ); // End of RAMB16BWE_S36_S36_inst instantiation
+
+ RAMB16BWE_S36_S36
+ #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+ .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+ .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+ .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+ .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
+ .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ RAM3
+ (.DOA(DOA3), // Port A 32-bit Data Output
+ .DOPA(), // Port A 4-bit Parity Output
+ .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+ .CLKA(clk), // Port A 1-bit Clock
+ .DIA(32'd0), // Port A 32-bit Data Input
+ .DIPA(4'd0), // Port A 4-bit parity Input
+ .ENA(1'b1), // Port A 1-bit RAM Enable Input
+ .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
+ .WEA(1'b0), // Port A 4-bit Write Enable Input
+
+ .DOB(DOB3), // Port B 32-bit Data Output
+ .DOPB(), // Port B 4-bit Parity Output
+ .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+ .CLKB(clk), // Port B 1-bit Clock
+ .DIB(dwb_dat_i), // Port B 32-bit Data Input
+ .DIPB(4'd0), // Port-B 4-bit parity Input
+ .ENB(ENB3), // Port B 1-bit RAM Enable Input
+ .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
+ .WEB(WEB) // Port B 4-bit Write Enable Input
+ ); // End of RAMB16BWE_S36_S36_inst instantiation
+
+endmodule // bootram
+
+/*
+ // The following INIT_xx declarations specify the initial contents of the RAM
+ // Address 0 to 127
+ .INIT_00(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_01(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_02(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_03(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_04(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_05(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_06(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_07(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_08(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_09(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_0A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_0B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_0C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_0D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_0E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_0F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ // Address 128 to 255
+ .INIT_10(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_11(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_12(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_13(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_14(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_15(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_16(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_17(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_18(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_19(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_1A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_1B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_1C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_1D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_1E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_1F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ // Address 256 to 383
+ .INIT_20(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_21(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_22(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_23(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_24(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_25(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_26(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_27(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_28(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_29(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_2A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_2B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_2C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_2D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_2E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_2F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ // Address 384 to 511
+ .INIT_30(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_31(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_32(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_33(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_34(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_35(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_36(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_37(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_38(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_39(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_3A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_3B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_3C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_3D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_3E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_3F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ // The next set of INITP_xx are for the parity bits
+ // Address 0 to 127
+ .INITP_00(256’h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_01(256’h0000000000000000000000000000000000000000000000000000000000000000),
+ // Address 128 to 255
+ .INITP_02(256’h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_03(256’h0000000000000000000000000000000000000000000000000000000000000000),
+ // Address 256 to 383
+ .INITP_04(256’h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_05(256’h0000000000000000000000000000000000000000000000000000000000000000),
+ // Address 384 to 511
+ .INITP_06(256’h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_07(256’h0000000000000000000000000000000000000000000000000000000000000000)
+*/
diff --git a/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v b/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v
index 38ca3a023..6c066d5d9 100644
--- a/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v
+++ b/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v
@@ -11,7 +11,7 @@ module aeMB_core_BE
(input sys_clk_i,
input sys_rst_i,
// Instruction port
- output [14:0] if_adr,
+ output [ISIZ-1:0] if_adr,
input [31:0] if_dat,
// Data port
output dwb_we_o,
@@ -34,7 +34,7 @@ module aeMB_core_BE
assign dwb_cyc_o = dwb_stb_o;
assign iwb_ack_i = 1'b1;
- assign if_adr = iwb_adr_o[14:0];
+ assign if_adr = iwb_adr_o[ISIZ-1:0];
assign iwb_dat_i = if_dat;
// Note some "wishbone" instruction fetch signals pruned on external interface
diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v
index 32dfb0331..ac0f6bbd1 100644
--- a/usrp2/top/u2plus/u2plus.v
+++ b/usrp2/top/u2plus/u2plus.v
@@ -364,8 +364,8 @@ module u2plus
.RAM_WEn (RAM_WEn),
.RAM_OEn (RAM_OEn),
.RAM_LDn (RAM_LDn),
- .uart_tx_o (TXD[0]),
- .uart_rx_i (RXD[0]),
+ .uart_tx_o (TXD[1]),
+ .uart_rx_i (RXD[1]),
.uart_baud_o (),
.sim_mode (1'b0),
.clock_divider (2),
@@ -377,6 +377,6 @@ module u2plus
assign RAM_ZZ = 1;
assign RAM_BWn = 4'b1111;
- assign TXD[2:1] = 2'b11;
+ assign TXD[3:2] = 2'b11;
endmodule // u2plus
diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v
index d49c461cb..bf6bf8b3e 100644
--- a/usrp2/top/u2plus/u2plus_core.v
+++ b/usrp2/top/u2plus/u2plus_core.v
@@ -3,7 +3,6 @@
// ////////////////////////////////////////////////////////////////////////////////
module u2plus_core
- #(parameter RAM_SIZE=32768)
(// Clocks
input dsp_clk,
input wb_clk,
@@ -191,23 +190,23 @@ module u2plus_core
wire m0_err, m0_rty;
wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we;
- wb_1master #(.decode_w(6),
- .s0_addr(6'b0000_00),.s0_mask(6'b100000),
- .s1_addr(6'b1000_00),.s1_mask(6'b110000),
- .s2_addr(6'b1100_00),.s2_mask(6'b111111),
- .s3_addr(6'b1100_01),.s3_mask(6'b111111),
- .s4_addr(6'b1100_10),.s4_mask(6'b111111),
- .s5_addr(6'b1100_11),.s5_mask(6'b111111),
- .s6_addr(6'b1101_00),.s6_mask(6'b111111),
- .s7_addr(6'b1101_01),.s7_mask(6'b111111),
- .s8_addr(6'b1101_10),.s8_mask(6'b111111),
- .s9_addr(6'b1101_11),.s9_mask(6'b111111),
- .sa_addr(6'b1110_00),.sa_mask(6'b111111),
- .sb_addr(6'b1110_01),.sb_mask(6'b111111),
- .sc_addr(6'b1110_10),.sc_mask(6'b111111),
- .sd_addr(6'b1110_11),.sd_mask(6'b111111),
- .se_addr(6'b1111_00),.se_mask(6'b111111),
- .sf_addr(6'b1111_01),.sf_mask(6'b111111),
+ wb_1master #(.decode_w(8),
+ .s0_addr(8'b0000_0000),.s0_mask(8'b1110_0000), // 0-8K, Boot RAM
+ .s1_addr(8'b0100_0000),.s1_mask(8'b1100_0000), // 16K-32K, Buffer Pool
+ .s2_addr(8'b0011_0000),.s2_mask(8'b1111_1111), // SPI
+ .s3_addr(8'b0011_0001),.s3_mask(8'b1111_1111), // I2C
+ .s4_addr(8'b0011_0010),.s4_mask(8'b1111_1111), // GPIO
+ .s5_addr(8'b0011_0011),.s5_mask(8'b1111_1111), // Readback
+ .s6_addr(8'b0011_0100),.s6_mask(8'b1111_1111), // Ethernet MAC
+ .s7_addr(8'b0010_0000),.s7_mask(8'b1111_0000), // 8-12K, Settings Bus (only uses 1K)
+ .s8_addr(8'b0011_0101),.s8_mask(8'b1111_1111), // PIC
+ .s9_addr(8'b0011_0110),.s9_mask(8'b1111_1111), // Unused
+ .sa_addr(8'b0011_0111),.sa_mask(8'b1111_1111), // UART
+ .sb_addr(8'b0011_1000),.sb_mask(8'b1111_1111), // ATR
+ .sc_addr(8'b0011_1001),.sc_mask(8'b1111_1111), // Unused
+ .sd_addr(8'b0011_1010),.sd_mask(8'b1111_1111), // ICAP
+ .se_addr(8'b0011_1011),.se_mask(8'b1111_1111), // SPI Flash
+ .sf_addr(8'b1000_0000),.sf_mask(8'b1000_0000), // 32-64K, Main RAM
.dw(dw),.aw(aw),.sw(sw)) wb_1master
(.clk_i(wb_clk),.rst_i(wb_rst),
.m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
@@ -251,7 +250,7 @@ module u2plus_core
// /////////////////////////////////////////////////////////////////////////
// Processor
wire [31:0] if_dat;
- wire [14:0] if_adr;
+ wire [15:0] if_adr;
aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1))
aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
@@ -267,15 +266,23 @@ module u2plus_core
assign bus_error = m0_err | m0_rty;
// /////////////////////////////////////////////////////////////////////////
- // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone
+ // Dual Ported Boot RAM -- D-Port is Slave #0 on main Wishbone
+ // Dual Ported Main RAM -- D-Port is Slave #F on main Wishbone
// I-port connects directly to processor
- wire flush_icache;
- ram_harvard2 #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE))
- sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
- .if_adr(if_adr), .if_data(if_dat),
- .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
- .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel));
+ wire [31:0] if_dat_boot, if_dat_main;
+ assign if_dat = if_adr[15] ? if_dat_main : if_dat_boot;
+
+ bootram bootram(.clk(wb_clk),
+ .if_adr(if_adr[12:0]), .if_data(if_dat_boot),
+ .dwb_adr_i(s0_adr[12:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
+ .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel));
+
+ ram_harvard2 #(.AWIDTH(15),.RAM_SIZE(32768))
+ sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+ .if_adr(if_adr[14:0]), .if_data(if_dat_main),
+ .dwb_adr_i(sf_adr[14:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i),
+ .dwb_we_i(sf_we), .dwb_ack_o(sf_ack), .dwb_stb_i(sf_stb), .dwb_sel_i(sf_sel));
// /////////////////////////////////////////////////////////////////////////
// Buffer Pool, slave #1
@@ -522,16 +529,11 @@ module u2plus_core
.we_i(sd_we), .ack_o(sd_ack), .dat_i(sd_dat_o), .dat_o(sd_dat_i));
// /////////////////////////////////////////////////////////////////////////
- // Unused -- Slave #14 (E)
-
- assign se_ack = 0;
-
- // /////////////////////////////////////////////////////////////////////////
- // SPI for Flash -- Slave #15 (F)
+ // SPI for Flash -- Slave #14 (E)
spi_top flash_spi
- (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(sf_adr[4:0]),.wb_dat_i(sf_dat_o),
- .wb_dat_o(sf_dat_i),.wb_sel_i(sf_sel),.wb_we_i(sf_we),.wb_stb_i(sf_stb),
- .wb_cyc_i(sf_cyc),.wb_ack_o(sf_ack),.wb_err_o(sf_err),.wb_int_o(spiflash_int),
+ (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(se_adr[4:0]),.wb_dat_i(se_dat_o),
+ .wb_dat_o(se_dat_i),.wb_sel_i(se_sel),.wb_we_i(se_we),.wb_stb_i(se_stb),
+ .wb_cyc_i(se_cyc),.wb_ack_o(se_ack),.wb_err_o(se_err),.wb_int_o(spiflash_int),
.ss_pad_o(spiflash_cs),
.sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) );
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 19:25:58 +0000