diff options
| -rw-r--r-- | usrp2/control_lib/ram_2port_mixed_width.v | 44 | ||||
| -rw-r--r-- | usrp2/gpmc/gpmc.v | 24 | ||||
| -rw-r--r-- | usrp2/top/u1e/Makefile | 1 |
3 files changed, 63 insertions, 6 deletions
diff --git a/usrp2/control_lib/ram_2port_mixed_width.v b/usrp2/control_lib/ram_2port_mixed_width.v new file mode 100644 index 000000000..3fa43114f --- /dev/null +++ b/usrp2/control_lib/ram_2port_mixed_width.v @@ -0,0 +1,44 @@ + + +module ram_2port_mixed_width + #(parameter AWIDTH=9) + (input clk16, + input en16, + input we16, + input [10:0] addr16, + input [15:0] di16, + output reg [15:0] do16, + + input clk32, + input en32, + input we32, + input [9:0] addr32, + input [31:0] di32, + output reg [31:0] do32); + + reg [31:0] ram [(1<<AWIDTH)-1:0]; + integer i; + initial + for(i=0;i<512;i=i+1) + ram[i] <= 32'b0; + + always @(posedge clk16) + if (en16) + begin + if (we16) + if(addr16[0]) + ram[addr16[10:1]][15:0] <= di16; + else + ram[addr16[10:1]][31:16] <= di16; + do16 <= addr16[0] ? ram[addr16[10:1]][15:0] : ram[addr16[10:1]][31:16]; + end + + always @(posedge clk32) + if (en32) + begin + if (we32) + ram[addr32] <= di32; + do32 <= ram[addr32]; + end + +endmodule // ram_2port_mixed_width diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v index 56f879abc..88f6809f8 100644 --- a/usrp2/gpmc/gpmc.v +++ b/usrp2/gpmc/gpmc.v @@ -2,12 +2,19 @@ ////////////////////////////////////////////////////////////////////////////////// module gpmc - (input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + (// GPMC signals + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + // Wishbone signals input wb_clk, input wb_rst, output reg [10:0] wb_adr_o, output reg [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, - output reg [1:0] wb_sel_o, output wb_cyc_o, output reg wb_stb_o, output reg wb_we_o, input wb_ack_i + output reg [1:0] wb_sel_o, output wb_cyc_o, output reg wb_stb_o, output reg wb_we_o, input wb_ack_i, + + // RAM Interface signals + input ram_clk, + input read_en, input read_sel, input [8:0] read_addr, output [31:0] read_data, output read_rdy, + input write_en, input write_sel, input [8:0] write_addr, input [31:0] write_data, output write_rdy ); wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); @@ -17,9 +24,15 @@ module gpmc assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_ram : EM_D_wb; // CS4 is RAM_2PORT for high-speed data - ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port - (.clka(wb_clk), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_ram), - .clkb(wb_clk), .enb(0), .web(0), .addrb(0), .dib(0), .dob()); + // Writes go into one RAM, reads come from the other + + ram_2port_mixed_width buffer_from_host + (.clk16(wb_clk), .en16(~EM_NCS4), .we16(~EM_NWE), .addr16({store_pg,EM_A}), .di16(EM_D), .do16(), + .clk32(ram_clk), .en32(read_en), .we32(0), .addr32({read_sel,read_addr}), .di32(0), .do32(read_data)); + + ram_2port_mixed_width buffer_to_host + (.clk16(wb_clk), .en16(~EM_NCS4), .we16(0), .addr16({retr_page,EM_A}), .di16(0), .do16(EM_D_ram), + .clk32(ram_clk), .en32(write_en), .we32(write_en), .addr32({write_sel,write_addr}), .di32(write_data), .do32()); // CS6 is Control, Wishbone bus bridge (wb master) // Sync version @@ -51,7 +64,6 @@ module gpmc assign EM_D_wb = wb_ack_i ? wb_dat_miso : EM_D_wb_reg; - // stb, oe_del, we_del assign wb_cyc_o = wb_stb_o; always @(posedge wb_clk) diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index bcd80df6a..306ab5bae 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -66,6 +66,7 @@ control_lib/mux4.v \ control_lib/mux8.v \ control_lib/nsgpio16LE.v \ control_lib/ram_2port.v \ +control_lib/ram_2port_mixed_width.v \ control_lib/ram_harv_cache.v \ control_lib/ram_loader.v \ control_lib/setting_reg.v \ |