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-rw-r--r--usrp2/top/u1e/Makefile2
-rw-r--r--usrp2/top/u1e/u1e.ucf64
-rw-r--r--usrp2/top/u1e/u1e.v6
-rw-r--r--usrp2/top/u1e/u1e_core.v19
4 files changed, 54 insertions, 37 deletions
diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile
index cdbdf995e..9381789a7 100644
--- a/usrp2/top/u1e/Makefile
+++ b/usrp2/top/u1e/Makefile
@@ -64,7 +64,7 @@ control_lib/gray_send.v \
control_lib/icache.v \
control_lib/mux4.v \
control_lib/mux8.v \
-control_lib/nsgpio.v \
+control_lib/nsgpio16LE.v \
control_lib/ram_2port.v \
control_lib/ram_harv_cache.v \
control_lib/ram_loader.v \
diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf
index 40d458034..f237eb60c 100644
--- a/usrp2/top/u1e/u1e.ucf
+++ b/usrp2/top/u1e/u1e.ucf
@@ -203,39 +203,39 @@ NET "dip_sw<0>" LOC = "J7" ;
#NET "PPS_IN" LOC = "M17" ;
-#NET "io_tx<0>" LOC = "AB20" ;
-#NET "io_tx<1>" LOC = "Y17" ;
-#NET "io_tx<2>" LOC = "Y16" ;
-#NET "io_tx<3>" LOC = "U16" ;
-#NET "io_tx<4>" LOC = "V16" ;
-#NET "io_tx<5>" LOC = "AB19" ;
-#NET "io_tx<6>" LOC = "AA19" ;
-#NET "io_tx<7>" LOC = "U14" ;
-#NET "io_tx<8>" LOC = "U15" ;
-#NET "io_tx<9>" LOC = "AB17" ;
-#NET "io_tx<10>" LOC = "AB18" ;
-#NET "io_tx<11>" LOC = "Y13" ;
-#NET "io_tx<12>" LOC = "W14" ;
-#NET "io_tx<13>" LOC = "U13" ;
-#NET "io_tx<14>" LOC = "AA15" ;
-#NET "io_tx<15>" LOC = "AB14" ;
+NET "io_tx<0>" LOC = "AB20" ;
+NET "io_tx<1>" LOC = "Y17" ;
+NET "io_tx<2>" LOC = "Y16" ;
+NET "io_tx<3>" LOC = "U16" ;
+NET "io_tx<4>" LOC = "V16" ;
+NET "io_tx<5>" LOC = "AB19" ;
+NET "io_tx<6>" LOC = "AA19" ;
+NET "io_tx<7>" LOC = "U14" ;
+NET "io_tx<8>" LOC = "U15" ;
+NET "io_tx<9>" LOC = "AB17" ;
+NET "io_tx<10>" LOC = "AB18" ;
+NET "io_tx<11>" LOC = "Y13" ;
+NET "io_tx<12>" LOC = "W14" ;
+NET "io_tx<13>" LOC = "U13" ;
+NET "io_tx<14>" LOC = "AA15" ;
+NET "io_tx<15>" LOC = "AB14" ;
-#NET "io_rx<0>" LOC = "Y8" ;
-#NET "io_rx<1>" LOC = "Y9" ;
-#NET "io_rx<2>" LOC = "V7" ;
-#NET "io_rx<3>" LOC = "U8" ;
-#NET "io_rx<4>" LOC = "V10" ;
-#NET "io_rx<5>" LOC = "U9" ;
-#NET "io_rx<6>" LOC = "AB7" ;
-#NET "io_rx<7>" LOC = "AA8" ;
-#NET "io_rx<8>" LOC = "W8" ;
-#NET "io_rx<9>" LOC = "V8" ;
-#NET "io_rx<10>" LOC = "AB5" ;
-#NET "io_rx<11>" LOC = "AB6" ;
-#NET "io_rx<12>" LOC = "AB4" ;
-#NET "io_rx<13>" LOC = "AA4" ;
-#NET "io_rx<14>" LOC = "W5" ;
-#NET "io_rx<15>" LOC = "Y4" ;
+NET "io_rx<0>" LOC = "Y8" ;
+NET "io_rx<1>" LOC = "Y9" ;
+NET "io_rx<2>" LOC = "V7" ;
+NET "io_rx<3>" LOC = "U8" ;
+NET "io_rx<4>" LOC = "V10" ;
+NET "io_rx<5>" LOC = "U9" ;
+NET "io_rx<6>" LOC = "AB7" ;
+NET "io_rx<7>" LOC = "AA8" ;
+NET "io_rx<8>" LOC = "W8" ;
+NET "io_rx<9>" LOC = "V8" ;
+NET "io_rx<10>" LOC = "AB5" ;
+NET "io_rx<11>" LOC = "AB6" ;
+NET "io_rx<12>" LOC = "AB4" ;
+NET "io_rx<13>" LOC = "AA4" ;
+NET "io_rx<14>" LOC = "W5" ;
+NET "io_rx<15>" LOC = "Y4" ;
#NET "CLKOUT2_CODEC" LOC = "U12" ;
#NET "CLKOUT1_CODEC" LOC = "V12" ;
diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v
index 326476b21..667372434 100644
--- a/usrp2/top/u1e/u1e.v
+++ b/usrp2/top/u1e/u1e.v
@@ -11,7 +11,8 @@ module u1e
input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
inout db_sda, inout db_scl, // I2C
- output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147 // Fifo controls
+ output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls
+ inout [15:0] io_tx, inout [15:0] io_rx
);
// FPGA-specific pins connections
@@ -27,6 +28,7 @@ module u1e
.EM_NWE(EM_NWE), .EM_NOE(EM_NOE),
.db_sda(db_sda), .db_scl(db_scl),
.tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145),
- .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147) );
+ .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147),
+ .io_tx(io_tx), .io_rx(io_rx) );
endmodule // u1e
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 257156d4b..ad3234b56 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -10,7 +10,8 @@ module u1e_core
input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
inout db_sda, inout db_scl,
- output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun
+ output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun,
+ inout [15:0] io_tx, inout [15:0] io_rx
);
wire wb_clk, wb_rst;
@@ -102,7 +103,7 @@ module u1e_core
.sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb),
.sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) );
- assign s4_ack = 0; assign s5_ack = 0; assign s6_ack = 0; assign s7_ack = 0;
+ assign s5_ack = 0; assign s6_ack = 0; assign s7_ack = 0;
assign s8_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0;
assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0;
@@ -172,6 +173,20 @@ module u1e_core
IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o));
IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o));
+ // /////////////////////////////////////////////////////////////////////////
+ // GPIOs -- Slave #4
+
+ wire [31:0] atr_lines;
+ wire [31:0] debug_gpio_0, debug_gpio_1;
+
+ nsgpio16LE
+ nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst),
+ .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
+ .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
+ .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
+ .gpio( {io_tx,io_rx} ) );
+
+
// /////////////////////////////////////////////////////////////////////////////////////
// Debug Pins
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 22:23:59 +0000