diff options
| -rw-r--r-- | CHANGELOG | 3 | ||||
| -rw-r--r-- | host/docs/images.dox | 2 | ||||
| -rw-r--r-- | host/lib/usrp/common/ad9361_driver/ad9361_device.cpp | 20 |
3 files changed, 13 insertions, 12 deletions
@@ -8,11 +8,12 @@ Change Log for Releases RSSI Sensor * B200: RSSI sensor * AD9361: Better handling of different interpolation rates in FIR, - fix for gain value truncation + fix for gain value truncation, removed gain value offset * UBX: Added drivers * Manual/Docs: Numerous updates, minimum compiler versions now specified, * Converters: Multiple fixes for sc12 * Examples: Fixes to txrx_loopback_to_file +* Path handling vastly improved, made more consistent * Minor UHD fixes ## 003.008.001 diff --git a/host/docs/images.dox b/host/docs/images.dox index bd2ffacf6..1ff9fa7c3 100644 --- a/host/docs/images.dox +++ b/host/docs/images.dox @@ -85,7 +85,7 @@ depending on the device. The build requires that you have a UNIX-like environment with `Make`. Make sure that `xtclsh` from the Xilinx ISE bin directory is in your `$PATH`. -- Xilinx ISE 14.4: USRP X3x0 Series, USRP B2x0 +- Xilinx ISE 14.7: USRP X3x0 Series, USRP B2x0 See `<uhd-repo-path>/fpga/usrp3/top/`. diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp index 1ea771db0..f1a82d71c 100644 --- a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp +++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp @@ -1049,7 +1049,7 @@ double ad9361_device_t::_tune_bbvco(const double rate) const double vcomin = 672e6; double vcorate; int vcodiv; - + /* Iterate over VCO dividers until appropriate divider is found. */ int i = 1; for (; i <= 6; i++) { @@ -1306,7 +1306,7 @@ double ad9361_device_t::_setup_rates(const double rate) divfactor = 16; _tfir_factor = 2; _rfir_factor = 2; - } else if ((rate >= 41e6) && (rate <= 56e6)) { + } else if ((rate >= 41e6) && (rate <= 58e6)) { // RX1 + RX2 enabled, 3, 1, 2, 2 _regs.rxfilt = B8(11100110); @@ -1316,15 +1316,15 @@ double ad9361_device_t::_setup_rates(const double rate) divfactor = 12; _tfir_factor = 2; _rfir_factor = 2; - } else if ((rate > 56e6) && (rate <= 61.44e6)) { - // RX1 + RX2 enabled, 3, 1, 1, 2 - _regs.rxfilt = B8(11100010); + } else if ((rate > 58e6) && (rate <= 61.44e6)) { + // RX1 + RX2 enabled, 2, 1, 2, 2 + _regs.rxfilt = B8(11010110); - // TX1 + TX2 enabled, 3, 1, 1, 1 - _regs.txfilt = B8(11100001); + // TX1 + TX2 enabled, 2, 1, 1, 2 + _regs.txfilt = B8(11010010); - divfactor = 6; - _tfir_factor = 1; + divfactor = 8; + _tfir_factor = 2; _rfir_factor = 2; } else { // should never get in here @@ -1340,7 +1340,7 @@ double ad9361_device_t::_setup_rates(const double rate) /* The DAC clock must be <= 336e6, and is either the ADC clock or 1/2 the * ADC clock.*/ if (adcclk > 336e6) { - /* Make the DAC clock = ADC/2, and bypass the TXFIR. */ + /* Make the DAC clock = ADC/2 */ _regs.bbpll = _regs.bbpll | 0x08; dacclk = adcclk / 2.0; } else { |