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authorMatt Ettus <matt@ettus.com>2009-12-11 17:53:10 -0800
committerMatt Ettus <matt@ettus.com>2009-12-11 17:53:10 -0800
commit42d8dc7e476be7da305f7718f20b3758ddd4313a (patch)
tree3459f59cb0f777dac908e844927d80411a361434 /vrt/vita_tx_deframer.v
parente252b782f39a78cb3472f014a6a81fe0a14bff8d (diff)
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fixed typo in u2_core.v resulting in unconnected net. added debug pins
Diffstat (limited to 'vrt/vita_tx_deframer.v')
-rw-r--r--vrt/vita_tx_deframer.v8
1 files changed, 7 insertions, 1 deletions
diff --git a/vrt/vita_tx_deframer.v b/vrt/vita_tx_deframer.v
index f6f9f3da8..470ba3f3e 100644
--- a/vrt/vita_tx_deframer.v
+++ b/vrt/vita_tx_deframer.v
@@ -17,7 +17,8 @@ module vita_tx_deframer
// FIFO Levels
output [15:0] fifo_occupied,
output fifo_full,
- output fifo_empty
+ output fifo_empty,
+ output [31:0] debug
);
wire [1:0] numchan;
@@ -177,5 +178,10 @@ module vita_tx_deframer
assign fifo_i = {sample_d,sample_c,sample_b,sample_a,has_secs_reg,is_sob_reg,is_eob_reg,eop,send_time};
assign dst_rdy_o = (vita_state != VITA_PAYLOAD);
+
+ assign debug = { { 8'b0 },
+ { 8'b0 },
+ { eof, line_done, store, fifo_space, src_rdy_i, dst_rdy_o, vector_phase[1:0] },
+ { has_secs_reg, is_sob_reg, is_eob_reg, eop, vita_state[3:0] } };
endmodule // vita_tx_deframer