diff options
| author | Matt Ettus <matt@ettus.com> | 2009-12-08 22:59:43 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2009-12-08 22:59:43 -0800 |
| commit | 4603b62e3d1069a1dba649eb53248f3a7725c23f (patch) | |
| tree | 127ab1f6fb6823bef19930cdc7cd9c7e0dada892 /vrt/vita_tx.build | |
| parent | 2de05770dfa11bfbe787a9d9e442d898980fb06a (diff) | |
| download | uhd-4603b62e3d1069a1dba649eb53248f3a7725c23f.tar.gz uhd-4603b62e3d1069a1dba649eb53248f3a7725c23f.tar.bz2 uhd-4603b62e3d1069a1dba649eb53248f3a7725c23f.zip | |
progress on vita_tx. it compiles now, need to work on vita_tx_control.
Diffstat (limited to 'vrt/vita_tx.build')
| -rwxr-xr-x | vrt/vita_tx.build | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/vrt/vita_tx.build b/vrt/vita_tx.build index 2d65537d5..902929c08 100755 --- a/vrt/vita_tx.build +++ b/vrt/vita_tx.build @@ -1 +1 @@ -iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_tx_tb vita_tx_tb.v +iverilog -Wimplict -Wportbind -y ../sdr_lib -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_tx_tb vita_tx_tb.v |