diff options
| author | Matt Ettus <matt@ettus.com> | 2009-11-18 15:24:02 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2009-11-18 15:24:02 -0800 |
| commit | 72cc0e23976c03627877f9bdfc26e81b333ae012 (patch) | |
| tree | eb07c18cc7bf9c2524d59d4d33696bd0e4912539 /vrt/vita_tx.build | |
| parent | 80610d42fc8b0a7e9ee424fb6c01d5f34f925fc3 (diff) | |
| download | uhd-72cc0e23976c03627877f9bdfc26e81b333ae012.tar.gz uhd-72cc0e23976c03627877f9bdfc26e81b333ae012.tar.bz2 uhd-72cc0e23976c03627877f9bdfc26e81b333ae012.zip | |
mostly just copied over from the rx side. Still needs a lot of work.
Diffstat (limited to 'vrt/vita_tx.build')
| -rwxr-xr-x | vrt/vita_tx.build | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/vrt/vita_tx.build b/vrt/vita_tx.build new file mode 100755 index 000000000..2d65537d5 --- /dev/null +++ b/vrt/vita_tx.build @@ -0,0 +1 @@ +iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_tx_tb vita_tx_tb.v |