From 72cc0e23976c03627877f9bdfc26e81b333ae012 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Wed, 18 Nov 2009 15:24:02 -0800
Subject: mostly just copied over from the rx side.  Still needs a lot of work.

---
 vrt/vita_tx.build | 1 +
 1 file changed, 1 insertion(+)
 create mode 100755 vrt/vita_tx.build

(limited to 'vrt/vita_tx.build')

diff --git a/vrt/vita_tx.build b/vrt/vita_tx.build
new file mode 100755
index 000000000..2d65537d5
--- /dev/null
+++ b/vrt/vita_tx.build
@@ -0,0 +1 @@
+iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_tx_tb vita_tx_tb.v
-- 
cgit v1.2.3