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| author | Josh Blum <josh@joshknows.com> | 2010-12-14 13:11:09 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-12-14 13:11:09 -0800 |
| commit | e4dc2a1c5688ab5c14285628a32212333b84f46f (patch) | |
| tree | fb826bd00d5054459b756964a72b82ec21ce2556 /usrp2 | |
| parent | ab9edbfbcb065b3ec380992b3b5836833ce92b4b (diff) | |
| download | uhd-e4dc2a1c5688ab5c14285628a32212333b84f46f.tar.gz uhd-e4dc2a1c5688ab5c14285628a32212333b84f46f.tar.bz2 uhd-e4dc2a1c5688ab5c14285628a32212333b84f46f.zip | |
zpu: working, modified top level sizes, disable interrupt
Diffstat (limited to 'usrp2')
| -rw-r--r-- | usrp2/top/u2_rev3/u2_core.v | 11 | ||||
| -rw-r--r-- | usrp2/top/u2_rev3/u2_rev3.v | 2 |
2 files changed, 5 insertions, 8 deletions
diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v index fff7ab914..97de38a82 100644 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -286,12 +286,10 @@ module u2_core // /////////////////////////////////////////////////////////////////// // RAM Loader - wire [31:0] ram_loader_dat, if_dat; + wire [31:0] ram_loader_dat; wire [15:0] ram_loader_adr; - wire [14:0] if_adr; wire [3:0] ram_loader_sel; wire ram_loader_stb, ram_loader_we; - wire iwb_ack, iwb_stb; ram_loader #(.AWIDTH(aw),.RAM_SIZE(RAM_SIZE)) ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst), .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr), @@ -323,12 +321,12 @@ module u2_core wire [63:0] zpu_status; zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) - zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(1'b1), + zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(ram_loader_done), // Data Wishbone bus to system bus fabric .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr), .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), // Interrupts and exceptions - .zpu_status(zpu_status), .interrupt(proc_int)); + .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); // ///////////////////////////////////////////////////////////////////////// // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone @@ -343,8 +341,7 @@ module u2_core .ram_loader_we_i(ram_loader_we), .ram_loader_done_i(ram_loader_done), - .if_adr(if_adr), - .if_data(if_dat), + .if_adr(16'b0), .if_data(), .dwb_adr_i(s0_adr[RAM_AW-1:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index f2bba6c50..759f7b7b8 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -471,7 +471,7 @@ module u2_rev3 // - u2_core #(.RAM_SIZE(32768)) + u2_core #(.RAM_SIZE(16384), .RAM_AW(14)) u2_core(.dsp_clk (dsp_clk), .wb_clk (wb_clk), .clock_ready (clock_ready), |