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| author | Matt Ettus <matt@ettus.com> | 2011-03-16 12:45:57 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-03-16 12:45:57 -0700 |
| commit | a44d249503cdc3767ef37895ce903c1024f96007 (patch) | |
| tree | dfc3d3ea5fa90b62ab939330f1dd1df5c74bbc83 /usrp2 | |
| parent | 8f0b80498ecfc16004d3e5dad19c69b20a3b89fb (diff) | |
| download | uhd-a44d249503cdc3767ef37895ce903c1024f96007.tar.gz uhd-a44d249503cdc3767ef37895ce903c1024f96007.tar.bz2 uhd-a44d249503cdc3767ef37895ce903c1024f96007.zip | |
udp: alternate udp ports
Diffstat (limited to 'usrp2')
| -rw-r--r-- | usrp2/udp/prot_eng_tx.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/udp/prot_eng_tx.v b/usrp2/udp/prot_eng_tx.v index 7d6454c01..b4f6e55b8 100644 --- a/usrp2/udp/prot_eng_tx.v +++ b/usrp2/udp/prot_eng_tx.v @@ -30,7 +30,7 @@ module prot_eng_tx reg [15:0] pre_checksums [0:3]; always @(posedge clk) - if(set_stb & (set_addr == (BASE+7))) + if(set_stb & ((set_addr & 8'hCF)== (BASE+7))) pre_checksums[set_addr[5:4]] <= set_data[15:0]; wire [15:0] pre_checksum = pre_checksums[port_sel[1:0]]; |