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author | Josh Blum <josh@joshknows.com> | 2012-10-09 17:49:12 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2012-10-09 17:49:12 -0700 |
commit | 60d3f8d448336b8a39299e8317e87cc231dda9d7 (patch) | |
tree | 4e3e8b516b2885a67b502a10d49898bbd31b5c90 /usrp2 | |
parent | 248743ac83ec72b4b09f325c0ea4dcff9ef2cdb0 (diff) | |
download | uhd-60d3f8d448336b8a39299e8317e87cc231dda9d7.tar.gz uhd-60d3f8d448336b8a39299e8317e87cc231dda9d7.tar.bz2 uhd-60d3f8d448336b8a39299e8317e87cc231dda9d7.zip |
b100: added final fifo for min occupancy check
Diffstat (limited to 'usrp2')
-rw-r--r-- | usrp2/gpif/fifo36_to_gpmc16.v | 27 |
1 files changed, 22 insertions, 5 deletions
diff --git a/usrp2/gpif/fifo36_to_gpmc16.v b/usrp2/gpif/fifo36_to_gpmc16.v index 508cd319c..4b4dc3109 100644 --- a/usrp2/gpif/fifo36_to_gpmc16.v +++ b/usrp2/gpif/fifo36_to_gpmc16.v @@ -17,7 +17,10 @@ module fifo36_to_gpmc16 #( - parameter FIFO_SIZE = 9 + parameter FIFO_SIZE = 9, + + //not ready until minimum xfers of occupancy available + parameter MIN_OCC16 = 2 ) ( //input fifo interface @@ -31,22 +34,36 @@ module fifo36_to_gpmc16 output [15:0] out_data, output valid, input enable, - output eof + output eof, + output reg has_data ); + wire [15:0] fifo_occ; + + always @(posedge gpif_clk) + has_data <= (fifo_occ >= MIN_OCC16); + wire [35:0] data_int; wire src_rdy_int, dst_rdy_int; - fifo_2clock_cascade #(.WIDTH(36), .SIZE(FIFO_SIZE)) fifo_2clk + fifo_2clock_cascade #(.WIDTH(36), .SIZE(6)) fifo_2clk (.wclk(fifo_clk), .datain(in_data), .src_rdy_i(in_src_rdy), .dst_rdy_o(in_dst_rdy), .space(), .rclk(gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(), .arst(fifo_rst | gpif_rst)); - wire [18:0] data18_int; + wire [18:0] data19_int; + wire data19_src_rdy_int, data19_dst_rdy_int; + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 (.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0), .f36_datain(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int), - .f19_dataout(data18_int), .f19_src_rdy_o(valid), .f19_dst_rdy_i(enable) ); + .f19_dataout(data19_int), .f19_src_rdy_o(data19_src_rdy_int), .f19_dst_rdy_i(data19_dst_rdy_int) ); + + wire [17:0] data18_int; + fifo_cascade #(.WIDTH(18), .SIZE(FIFO_SIZE+1)) occ_ctrl_fifo + (.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0), + .datain(data19_int[17:0]), .src_rdy_i(data19_src_rdy_int), .dst_rdy_o(data19_dst_rdy_int), .space(), + .dataout(data18_int), .src_rdy_o(valid), .dst_rdy_i(enable), .occupied(fifo_occ)); assign out_data = data18_int[15:0]; assign eof = data18_int[17]; |