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| author | Matt Ettus <matt@ettus.com> | 2010-11-04 14:26:16 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-11-04 14:26:16 -0700 |
| commit | 57fcaa242088516813a178713f9316e8ef7657a1 (patch) | |
| tree | f2d148cce33db1e05ce4f37a26043b1479eb5d97 /usrp2 | |
| parent | 1f77494788fa4fa8450aaf170055553bd0e5fe8e (diff) | |
| download | uhd-57fcaa242088516813a178713f9316e8ef7657a1.tar.gz uhd-57fcaa242088516813a178713f9316e8ef7657a1.tar.bz2 uhd-57fcaa242088516813a178713f9316e8ef7657a1.zip | |
duh
Diffstat (limited to 'usrp2')
| -rw-r--r-- | usrp2/top/u1e/u1e_core.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 619e44b8a..256146a99 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -36,7 +36,7 @@ module u1e_core localparam SR_TX_CTRL = 24; // 2 regs localparam SR_TIME64 = 28; // 4 regs - wire COMPAT_NUM = 8'd2; + wire [7:0] COMPAT_NUM = 8'd2; wire wb_clk = clk_fpga; wire wb_rst = rst_fpga; |