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authorMatt Ettus <matt@ettus.com>2011-03-16 16:42:51 -0700
committerMatt Ettus <matt@ettus.com>2011-03-16 16:42:51 -0700
commitb357b627fb3f519408ca38ebadc9f4ae6d57de80 (patch)
treed7f11bc309111c65f0e705e2e39f70a44101b941 /usrp2/vrt
parent74979af6a089c67ac6579cb08040aec305032018 (diff)
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clean up a bunch of warnings and incorrect bus widths
Diffstat (limited to 'usrp2/vrt')
-rw-r--r--usrp2/vrt/trigger_context_pkt.v2
-rw-r--r--usrp2/vrt/vita_tx_chain.v5
-rw-r--r--usrp2/vrt/vita_tx_control.v2
-rw-r--r--usrp2/vrt/vita_tx_deframer.v4
4 files changed, 7 insertions, 6 deletions
diff --git a/usrp2/vrt/trigger_context_pkt.v b/usrp2/vrt/trigger_context_pkt.v
index 226ec45f2..1d456814b 100644
--- a/usrp2/vrt/trigger_context_pkt.v
+++ b/usrp2/vrt/trigger_context_pkt.v
@@ -10,7 +10,7 @@ module trigger_context_pkt
wire [15:0] packets;
wire [6:0] dummy1;
wire [14:0] dummy2;
- wire enable_timed, enable_consumed;
+ wire enable_cycle, enable_consumed;
reg [30:0] cycle_count, packet_count;
diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v
index 6f567668d..fa84d7a2f 100644
--- a/usrp2/vrt/vita_tx_chain.v
+++ b/usrp2/vrt/vita_tx_chain.v
@@ -27,16 +27,17 @@ module vita_tx_chain
wire trigger, sent;
wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp;
- wire error, packet_consumed;
+ wire error, packet_consumed, ack;
wire [31:0] error_code;
wire clear_seqnum;
wire [31:0] current_seqnum;
+ wire strobe_tx;
assign underrun = error;
assign message = error_code;
setting_reg #(.my_addr(BASE_CTRL+1)) sr
- (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(),.changed(clear_vita));
setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid
diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v
index e966d987c..14b97a215 100644
--- a/usrp2/vrt/vita_tx_control.v
+++ b/usrp2/vrt/vita_tx_control.v
@@ -71,7 +71,7 @@ module vita_tx_control
wire [31:0] error_policy;
setting_reg #(.my_addr(BASE+3)) sr_error_policy
- (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(error_policy),.changed());
wire policy_wait = error_policy[0];
diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v
index eb39feaec..163c2af20 100644
--- a/usrp2/vrt/vita_tx_deframer.v
+++ b/usrp2/vrt/vita_tx_deframer.v
@@ -38,8 +38,8 @@ module vita_tx_deframer
assign has_secs = ~(data_i[23:22]==2'b00);
assign has_tics = ~(data_i[21:20]==2'b00);
assign has_trailer = data_i[26];
- assign is_sob = data_i[25];
- assign is_eob = data_i[24];
+ wire is_sob = data_i[25];
+ wire is_eob = data_i[24];
wire eof = data_i[33];
reg has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg;
reg has_trailer_reg, is_sob_reg, is_eob_reg;