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author | Matt Ettus <matt@ettus.com> | 2010-12-09 12:32:10 -0800 |
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committer | Matt Ettus <matt@ettus.com> | 2010-12-09 12:32:10 -0800 |
commit | 0abb502d9e9aefc33ead200002906f70b7c982d5 (patch) | |
tree | 434351c4d2c9ad9509912c9e47ff2c60469b41f7 /usrp2/vrt/vita_tx_control.v | |
parent | 355382f4c687f5d997f4589a34915d6e465bd387 (diff) | |
parent | ac41c5a7adaf7f004c535b3a8b13aa5343562f50 (diff) | |
download | uhd-0abb502d9e9aefc33ead200002906f70b7c982d5.tar.gz uhd-0abb502d9e9aefc33ead200002906f70b7c982d5.tar.bz2 uhd-0abb502d9e9aefc33ead200002906f70b7c982d5.zip |
Merge branch 'time_compare_speedup' into ise12
* time_compare_speedup:
should safely delay the late signal which was causing timing problems
Diffstat (limited to 'usrp2/vrt/vita_tx_control.v')
-rw-r--r-- | usrp2/vrt/vita_tx_control.v | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index 20ad6b995..ab6da8bd0 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -40,7 +40,21 @@ module vita_tx_control time_compare time_compare (.time_now(vita_time), .trigger_time(send_time), .now(now), .early(early), .late(late), .too_early()); + + reg late_qual, late_del; + + always @(posedge clk) + if(reset | clear) + late_del <= 0; + else + late_del <= late; + always @(posedge clk) + if(reset | clear) + late_qual <= 0; + else + late_qual <= (sample_fifo_src_rdy_i & ~sample_fifo_dst_rdy_o); + localparam IBS_IDLE = 0; localparam IBS_RUN = 1; // FIXME do we need this? localparam IBS_CONT_BURST = 2; @@ -87,7 +101,7 @@ module vita_tx_control end else if(~send_at | now) ibs_state <= IBS_RUN; - else if(late | too_early) + else if((late_qual & late_del) | too_early) begin ibs_state <= IBS_ERROR; error_code <= CODE_TIME_ERROR; @@ -166,7 +180,7 @@ module vita_tx_control else packet_consumed <= eop & sample_fifo_src_rdy_i & sample_fifo_dst_rdy_o; - assign debug = { { now,early,late,ack,eop,eob,sob,send_at }, + assign debug = { { now,late_qual,late_del,ack,eop,eob,sob,send_at }, { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, error, ibs_state[2:0] }, { 8'b0 }, { 8'b0 } }; |