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authorMatt Ettus <matt@ettus.com>2011-03-27 22:11:51 -0700
committerMatt Ettus <matt@ettus.com>2011-03-27 22:11:51 -0700
commit81e5fd49a57a6875d89737da3f1c2e203c3fa0b7 (patch)
treec91e133f2f0a0d5d694bb8d426a65578b9431278 /usrp2/vrt/vita_tx_chain.v
parentbe2c1b95c1d6f4ad2ea663bb926a04463edb9358 (diff)
parent8fa7187ca8ea16207e93f27b46406f20f75da8d8 (diff)
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Merge branch 'master' into next
* master: u2p: N200 Makefile u1e: use icarus verilog for lint clean up a bunch of warnings and incorrect bus widths
Diffstat (limited to 'usrp2/vrt/vita_tx_chain.v')
-rw-r--r--usrp2/vrt/vita_tx_chain.v5
1 files changed, 3 insertions, 2 deletions
diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v
index 6f567668d..fa84d7a2f 100644
--- a/usrp2/vrt/vita_tx_chain.v
+++ b/usrp2/vrt/vita_tx_chain.v
@@ -27,16 +27,17 @@ module vita_tx_chain
wire trigger, sent;
wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp;
- wire error, packet_consumed;
+ wire error, packet_consumed, ack;
wire [31:0] error_code;
wire clear_seqnum;
wire [31:0] current_seqnum;
+ wire strobe_tx;
assign underrun = error;
assign message = error_code;
setting_reg #(.my_addr(BASE_CTRL+1)) sr
- (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(),.changed(clear_vita));
setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid