From b357b627fb3f519408ca38ebadc9f4ae6d57de80 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 16 Mar 2011 16:42:51 -0700 Subject: clean up a bunch of warnings and incorrect bus widths --- usrp2/vrt/vita_tx_chain.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'usrp2/vrt/vita_tx_chain.v') diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 6f567668d..fa84d7a2f 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -27,16 +27,17 @@ module vita_tx_chain wire trigger, sent; wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp; - wire error, packet_consumed; + wire error, packet_consumed, ack; wire [31:0] error_code; wire clear_seqnum; wire [31:0] current_seqnum; + wire strobe_tx; assign underrun = error; assign message = error_code; setting_reg #(.my_addr(BASE_CTRL+1)) sr - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(clear_vita)); setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid -- cgit v1.2.3