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authorMatt Ettus <matt@ettus.com>2011-03-15 19:21:20 -0700
committerMatt Ettus <matt@ettus.com>2011-03-16 12:26:38 -0700
commit487f693e2c7d19132e56f3d3674bfc6e267b57ab (patch)
tree3e7b3c0f3837d7819871a91c7c6afed6d5f452c7 /usrp2/udp/prot_eng_tx.v
parent8ec25602f279951fa6332503e27813f1ff72ea3a (diff)
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udp: fix precomputation of ip header checksum
Diffstat (limited to 'usrp2/udp/prot_eng_tx.v')
-rw-r--r--usrp2/udp/prot_eng_tx.v12
1 files changed, 9 insertions, 3 deletions
diff --git a/usrp2/udp/prot_eng_tx.v b/usrp2/udp/prot_eng_tx.v
index 3adaaa32b..0c3e58892 100644
--- a/usrp2/udp/prot_eng_tx.v
+++ b/usrp2/udp/prot_eng_tx.v
@@ -19,7 +19,6 @@ module prot_eng_tx
// Store header values in a small dual-port (distributed) ram
reg [31:0] header_ram[0:63];
- wire [31:0] header_word;
reg [3:0] state;
reg [1:0] port_sel;
@@ -27,7 +26,14 @@ module prot_eng_tx
if(set_stb & ((set_addr & 8'hC0) == BASE))
header_ram[set_addr[5:0]] <= set_data;
- assign header_word = header_ram[{port_sel[1:0],state[3:0]}];
+ wire [31:0] header_word = header_ram[{port_sel[1:0],state[3:0]}];
+
+ reg [15:0] pre_checksums [0:3];
+ always @(posedge clk)
+ if(set_stb & (set_addr == (BASE+6)))
+ pre_checksums[set_addr[5:4]] <= set_data[15:0];
+
+ wire [15:0] pre_checksum = header_ram[port_sel[1:0]];
// Protocol State Machine
reg [15:0] length;
@@ -70,7 +76,7 @@ module prot_eng_tx
wire [15:0] ip_checksum;
add_onescomp #(.WIDTH(16)) add_onescomp
- (.A(header_word[15:0]),.B(ip_length),.SUM(ip_checksum));
+ (.A(pre_checksum),.B(ip_length),.SUM(ip_checksum));
reg [15:0] ip_checksum_reg;
always @(posedge clk) ip_checksum_reg <= ip_checksum;