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| author | Matt Ettus <matt@ettus.com> | 2011-03-16 16:42:51 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-03-16 16:42:51 -0700 |
| commit | b357b627fb3f519408ca38ebadc9f4ae6d57de80 (patch) | |
| tree | d7f11bc309111c65f0e705e2e39f70a44101b941 /usrp2/top | |
| parent | 74979af6a089c67ac6579cb08040aec305032018 (diff) | |
| download | uhd-b357b627fb3f519408ca38ebadc9f4ae6d57de80.tar.gz uhd-b357b627fb3f519408ca38ebadc9f4ae6d57de80.tar.bz2 uhd-b357b627fb3f519408ca38ebadc9f4ae6d57de80.zip | |
clean up a bunch of warnings and incorrect bus widths
Diffstat (limited to 'usrp2/top')
| -rw-r--r-- | usrp2/top/u1e/u1e_core.v | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index b3d71b4ab..1e3b08465 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -11,7 +11,7 @@ module u1e_core input EM_NWE, input EM_NOE, inout db_sda, inout db_scl, - output sclk, output [7:0] sen, output mosi, input miso, + output sclk, output [15:0] sen, output mosi, input miso, input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, @@ -127,7 +127,7 @@ module u1e_core wire [31:0] sample_rx, sample_tx; wire strobe_rx, strobe_tx; wire rx1_dst_rdy, rx1_src_rdy; - wire [99:0] rx1_data; + wire [100:0] rx1_data; wire run_rx; wire [35:0] vita_rx_data; wire vita_rx_src_rdy, vita_rx_dst_rdy; @@ -368,7 +368,7 @@ module u1e_core atr_controller16 atr_controller16 (.clk_i(wb_clk), .rst_i(wb_rst), - .adr_i(s6_adr), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), + .adr_i(s6_adr[5:0]), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines)); @@ -383,7 +383,7 @@ module u1e_core wb_readback_mux_16LE readback_mux_32 (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s7_stb), - .wb_adr_i(s7_adr), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack), + .wb_adr_i({5'b0,s7_adr}), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack), .word00(vita_time[63:32]), .word01(vita_time[31:0]), .word02(vita_time_pps[63:32]), .word03(vita_time_pps[31:0]), @@ -400,7 +400,8 @@ module u1e_core time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int)); + .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), + .exp_time_in(0)); // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry |