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| author | Matt Ettus <matt@ettus.com> | 2011-03-23 19:35:29 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-03-25 11:34:59 -0700 |
| commit | a82830bf030c01d40226900ab0cb87c2811f82d5 (patch) | |
| tree | e47ea3c3e5cc9cd32a2941ba681b399386248348 /usrp2/top/u2plus | |
| parent | 74979af6a089c67ac6579cb08040aec305032018 (diff) | |
| download | uhd-a82830bf030c01d40226900ab0cb87c2811f82d5.tar.gz uhd-a82830bf030c01d40226900ab0cb87c2811f82d5.tar.bz2 uhd-a82830bf030c01d40226900ab0cb87c2811f82d5.zip | |
u2p: N200 Makefile
Diffstat (limited to 'usrp2/top/u2plus')
| -rw-r--r-- | usrp2/top/u2plus/Makefile.N200 | 98 |
1 files changed, 98 insertions, 0 deletions
diff --git a/usrp2/top/u2plus/Makefile.N200 b/usrp2/top/u2plus/Makefile.N200 new file mode 100644 index 000000000..9175f9304 --- /dev/null +++ b/usrp2/top/u2plus/Makefile.N200 @@ -0,0 +1,98 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u2plus +BUILD_DIR = $(abspath build$(ISE)-N200) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extramfifo/Makefile.srcs + + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package fg676 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u2plus_core.v \ +u2plus.v \ +u2plus.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +SIM_MODEL_PROPERTIES = "" |