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| author | Matt Ettus <matt@ettus.com> | 2011-03-03 18:10:37 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-03-03 18:10:37 -0800 |
| commit | 8e27fc0c3c1e14e23f6f66911eb2e1aaaf061484 (patch) | |
| tree | c03979f27afa6aa54cd6d5d926e75358e14a8710 /usrp2/top/u2_rev3_iad | |
| parent | 985d82f1c24983cf6809a052cb190ba55f673f30 (diff) | |
| download | uhd-8e27fc0c3c1e14e23f6f66911eb2e1aaaf061484.tar.gz uhd-8e27fc0c3c1e14e23f6f66911eb2e1aaaf061484.tar.bz2 uhd-8e27fc0c3c1e14e23f6f66911eb2e1aaaf061484.zip | |
remove references to old directory
Diffstat (limited to 'usrp2/top/u2_rev3_iad')
| -rw-r--r-- | usrp2/top/u2_rev3_iad/Makefile | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/usrp2/top/u2_rev3_iad/Makefile b/usrp2/top/u2_rev3_iad/Makefile index 5ae8846dd..15df9e43e 100644 --- a/usrp2/top/u2_rev3_iad/Makefile +++ b/usrp2/top/u2_rev3_iad/Makefile @@ -120,7 +120,6 @@ eth/rtl/verilog/flow_ctrl_tx.v \ eth/rtl/verilog/miim/eth_clockgen.v \ eth/rtl/verilog/miim/eth_outputcontrol.v \ eth/rtl/verilog/miim/eth_shiftreg.v \ -extram/wb_zbt16_b.v \ opencores/8b10b/decode_8b10b.v \ opencores/8b10b/encode_8b10b.v \ opencores/aemb/rtl/verilog/aeMB_bpcu.v \ |