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author | Ian Buckley <ianb@server2.(none)> | 2010-07-29 21:25:26 -0700 |
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committer | Ian Buckley <ianb@server2.(none)> | 2010-07-29 21:25:26 -0700 |
commit | 8cd762bdbcbd6a43a2fcc1c0b523cc14bfd7ab69 (patch) | |
tree | ae72deb4fb98b50438fc660a081dbf89fffbebd5 /usrp2/top/u2_rev3/u2_core.v | |
parent | 886606f55da066b66d214e512a2226b19a1073df (diff) | |
download | uhd-8cd762bdbcbd6a43a2fcc1c0b523cc14bfd7ab69.tar.gz uhd-8cd762bdbcbd6a43a2fcc1c0b523cc14bfd7ab69.tar.bz2 uhd-8cd762bdbcbd6a43a2fcc1c0b523cc14bfd7ab69.zip |
Checkpoint checkin.
Loopback is running via the external ZBT SRAM...HOWEVER, its not running well, its stable but the data is corrupted sometimes.
Not clear if its a logic or AC timing/SI issue yet.
Diffstat (limited to 'usrp2/top/u2_rev3/u2_core.v')
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