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| author | Matt Ettus <matt@ettus.com> | 2011-03-05 23:28:54 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-03-05 23:28:54 -0800 |
| commit | 8a49d85f0b26a0ab459d41831dc2b03c91744458 (patch) | |
| tree | 95b6686d273102858c47efbb3b569daa14feac7e /usrp2/top/u2_rev3/u2_core.v | |
| parent | 354b55e52ed4edd4f417e7cb28b93960bebaf762 (diff) | |
| download | uhd-8a49d85f0b26a0ab459d41831dc2b03c91744458.tar.gz uhd-8a49d85f0b26a0ab459d41831dc2b03c91744458.tar.bz2 uhd-8a49d85f0b26a0ab459d41831dc2b03c91744458.zip | |
u2/u2p: moved dsp framer into vita_rx_chain
Diffstat (limited to 'usrp2/top/u2_rev3/u2_core.v')
| -rw-r--r-- | usrp2/top/u2_rev3/u2_core.v | 24 |
1 files changed, 6 insertions, 18 deletions
diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v index 7504efeb3..eb07ed42f 100644 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -569,8 +569,7 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // DSP RX 0 wire [31:0] sample_rx0; - wire [35:0] rx0_data; - wire clear_rx0, strobe_rx0, rx0_dst_rdy, rx0_src_rdy; + wire clear_rx0, strobe_rx0; always @(posedge dsp_clk) run_rx0_d1 <= run_rx0; @@ -587,24 +586,18 @@ module u2_core .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), .out(),.changed(clear_rx0)); - vita_rx_chain #(.BASE(SR_RX_CTRL0)) vita_rx_chain0 + vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain0 (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .vita_time(vita_time), .overrun(overrun0), .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), - .rx_data_o(rx0_data), .rx_src_rdy_o(rx0_src_rdy), .rx_dst_rdy_i(rx0_dst_rdy), + .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o), .debug() ); - fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade0 - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0), - .datain(rx0_data), .src_rdy_i(rx0_src_rdy), .dst_rdy_o(rx0_dst_rdy), - .dataout(wr1_dat), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o)); - // ///////////////////////////////////////////////////////////////////////// // DSP RX 1 wire [31:0] sample_rx1; - wire [35:0] rx1_data; - wire clear_rx1, strobe_rx1, rx1_dst_rdy, rx1_src_rdy; + wire clear_rx1, strobe_rx1; always @(posedge dsp_clk) run_rx1_d1 <= run_rx1; @@ -621,19 +614,14 @@ module u2_core .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), .out(),.changed(clear_rx1)); - vita_rx_chain #(.BASE(SR_RX_CTRL1)) vita_rx_chain1 + vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(1),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain1 (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .vita_time(vita_time), .overrun(overrun1), .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), - .rx_data_o(rx1_data), .rx_src_rdy_o(rx1_src_rdy), .rx_dst_rdy_i(rx1_dst_rdy), + .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o), .debug() ); - fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade1 - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1), - .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy), - .dataout(wr3_dat), .src_rdy_o(wr3_ready_i), .dst_rdy_i(wr3_ready_o)); - // /////////////////////////////////////////////////////////////////////////////////// // DSP TX |