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| author | Matt Ettus <matt@ettus.com> | 2010-05-27 16:30:42 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-05-27 16:30:42 -0700 |
| commit | d87035457d623fde5b141068f83bb891b7d6978e (patch) | |
| tree | de639616c82eb8cf20e9c26084477dfdc6eba68e /usrp2/top/u2_rev1/u2_fpga.ise | |
| parent | 6f63773d7425dd952c5ca24da618c22c486ae294 (diff) | |
| parent | 621ad7cc9e68b4e304b616d8f840d3a03a047c8b (diff) | |
| download | uhd-d87035457d623fde5b141068f83bb891b7d6978e.tar.gz uhd-d87035457d623fde5b141068f83bb891b7d6978e.tar.bz2 uhd-d87035457d623fde5b141068f83bb891b7d6978e.zip | |
Merge branch 'master' into u1e_merge_with_master
* master:
get rid of some warnings by declaring setting reg width
added width parameter to avoid warnings (thanks IJB) and default value parameter
added pragmas suggested by Ian Buckley to help ISE12 synthesis
get rid of old CVS linkage
settings bus to dsp_clk now uses clock crossing fifo
remove files for old prototypes, they were confusing people
revert commit 9899b81f920 which should have improved timing but didn't
Conflicts:
usrp2/control_lib/setting_reg.v
usrp2/top/u2_core/u2_core.v
usrp2/top/u2_rev3/Makefile
Diffstat (limited to 'usrp2/top/u2_rev1/u2_fpga.ise')
| -rw-r--r-- | usrp2/top/u2_rev1/u2_fpga.ise | bin | 477678 -> 0 bytes |
1 files changed, 0 insertions, 0 deletions
diff --git a/usrp2/top/u2_rev1/u2_fpga.ise b/usrp2/top/u2_rev1/u2_fpga.ise Binary files differdeleted file mode 100644 index f90caf024..000000000 --- a/usrp2/top/u2_rev1/u2_fpga.ise +++ /dev/null |