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| author | Matt Ettus <matt@ettus.com> | 2010-05-26 18:45:01 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-05-26 18:45:01 -0700 |
| commit | a1284e5d02fbb9e0b7cf541a9ffe501707d37c8c (patch) | |
| tree | 6d4071f3c3a200b3ca75c0ccb84e52023dcb3566 /usrp2/top/u2_core | |
| parent | d32cedbf00eb342d999832737f9f1ba2109ef2ad (diff) | |
| download | uhd-a1284e5d02fbb9e0b7cf541a9ffe501707d37c8c.tar.gz uhd-a1284e5d02fbb9e0b7cf541a9ffe501707d37c8c.tar.bz2 uhd-a1284e5d02fbb9e0b7cf541a9ffe501707d37c8c.zip | |
experimental mods to make ram loader fully synchronous. Based on IJB's work
Diffstat (limited to 'usrp2/top/u2_core')
| -rwxr-xr-x | usrp2/top/u2_core/u2_core.v | 29 |
1 files changed, 14 insertions, 15 deletions
diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v index 600bd7f3f..a90e2ced6 100755 --- a/usrp2/top/u2_core/u2_core.v +++ b/usrp2/top/u2_core/u2_core.v @@ -263,23 +263,22 @@ module u2_core wire [15:0] ram_loader_adr; wire [14:0] if_adr; wire [3:0] ram_loader_sel; - wire ram_loader_stb, ram_loader_we, ram_loader_ack; + wire ram_loader_stb, ram_loader_we; wire iwb_ack, iwb_stb; ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) - ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), + ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst), + .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr), + .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel), + .wb_we(ram_loader_we), + .ram_loader_done(ram_loader_done), // CPLD Interface - .cfg_clk_i(cpld_clk), - .cfg_data_i(cpld_din), - .start_o(cpld_start_int), - .mode_o(cpld_mode_int), - .done_o(cpld_done_int), - .detached_i(cpld_detached), - // Wishbone Interface - .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr), - .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel), - .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack), - .ram_loader_done_o(ram_loader_done)); - + .cpld_clk(cpld_clk), + .cpld_din(cpld_din), + .cpld_start(cpld_start_int), + .cpld_mode(cpld_mode_int), + .cpld_done(cpld_done_int), + .cpld_detached(cpld_detached)); + // ///////////////////////////////////////////////////////////////////////// // Processor aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) @@ -305,7 +304,7 @@ module u2_core .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), - .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), + .ram_loader_we_i(ram_loader_we), .ram_loader_done_i(ram_loader_done), .if_adr(if_adr), |