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| author | Matt Ettus <matt@ettus.com> | 2010-06-02 14:57:09 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-05-26 17:31:18 -0700 |
| commit | 6f172696365d5ac2887c7c08f3f0c5e561121c87 (patch) | |
| tree | 063b74f48a8dfc97304a9fa4c866bc59c51df1fb /usrp2/top/u1plus/timing.ucf | |
| parent | 9b4fa86af2d0ed59d0881a3d153b309c94c7e4e5 (diff) | |
| download | uhd-6f172696365d5ac2887c7c08f3f0c5e561121c87.tar.gz uhd-6f172696365d5ac2887c7c08f3f0c5e561121c87.tar.bz2 uhd-6f172696365d5ac2887c7c08f3f0c5e561121c87.zip | |
copied over from other repo. Beginnings of a skeleton fpga image for USRP1-Plus
Diffstat (limited to 'usrp2/top/u1plus/timing.ucf')
| -rw-r--r-- | usrp2/top/u1plus/timing.ucf | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/usrp2/top/u1plus/timing.ucf b/usrp2/top/u1plus/timing.ucf new file mode 100644 index 000000000..ca5ebf8e3 --- /dev/null +++ b/usrp2/top/u1plus/timing.ucf @@ -0,0 +1,2 @@ +NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; +TIMESPEC "TS_CLK_FPGA_P" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; |