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authorMatt Ettus <matt@ettus.com>2010-02-16 18:47:22 -0800
committerMatt Ettus <matt@ettus.com>2010-02-16 18:47:22 -0800
commitb115e4d7661d64c6d20f0421908622b56a91e950 (patch)
treeb684f1b1266640ab146bdb399c8e82ca3769a329 /usrp2/top/u1e/u1e.v
parentc1ddc5c082c053eaa46c8bc87064d3e3e56b0d9e (diff)
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first cut at gpmc <-> wb bridge, split u1e into core, top, and tb
Diffstat (limited to 'usrp2/top/u1e/u1e.v')
-rw-r--r--usrp2/top/u1e/u1e.v33
1 files changed, 8 insertions, 25 deletions
diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v
index e28a6a582..8832d6e11 100644
--- a/usrp2/top/u1e/u1e.v
+++ b/usrp2/top/u1e/u1e.v
@@ -2,13 +2,12 @@
//////////////////////////////////////////////////////////////////////////////////
module u1e
- (
- input CLK_FPGA_P, input CLK_FPGA_N, // Diff
+ (input CLK_FPGA_P, input CLK_FPGA_N, // Diff
output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
// GPMC
- input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A,
- input EM_WAIT0, input EM_NCS4, input EM_NWP, input EM_NWE, input EM_NOE, input EM_NADV_ALE
+ input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
+ input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE
);
// FPGA-specific pins connections
@@ -17,25 +16,9 @@ module u1e
IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE"))
clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
- // Debug circuitry
- reg [31:0] ctr;
- always @(posedge clk_fpga)
- ctr <= ctr + 1;
-
-
- assign debug_led = ctr[27:25];
- assign debug_clk = { EM_CLK, clk_fpga };
- assign debug = { { EM_WAIT0, EM_NADV_ALE, EM_NWP, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] },
- { EM_D } };
-
- wire EM_output_enable = (~EM_NOE & ~EM_NCS4);
- wire [15:0] EM_D_out;
-
- assign EM_D = EM_output_enable ? EM_D_out : 16'bz;
-
- ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port
- (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_out),
- .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob());
+ u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+ .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+ .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6),
+ .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
-
-endmodule // u2plus
+endmodule // u1e