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| author | Matt Ettus <matt@ettus.com> | 2011-05-09 12:44:06 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-05-09 12:48:06 -0700 |
| commit | d5a97d111b9f7baeee0fb9f2e1efbad9a16a83d4 (patch) | |
| tree | 846d21d04cdbad6272066c6008307fc98d23de85 /usrp2/top/u1e/core_compile | |
| parent | 4834b1a1d1de308c06c01aa5a700dd62d0e1d3b3 (diff) | |
| download | uhd-d5a97d111b9f7baeee0fb9f2e1efbad9a16a83d4.tar.gz uhd-d5a97d111b9f7baeee0fb9f2e1efbad9a16a83d4.tar.bz2 uhd-d5a97d111b9f7baeee0fb9f2e1efbad9a16a83d4.zip | |
u1e: switch to vita_rx_chain module just like other toplevels
Diffstat (limited to 'usrp2/top/u1e/core_compile')
| -rwxr-xr-x | usrp2/top/u1e/core_compile | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/usrp2/top/u1e/core_compile b/usrp2/top/u1e/core_compile index fb1b2a854..dc0cd081e 100755 --- a/usrp2/top/u1e/core_compile +++ b/usrp2/top/u1e/core_compile @@ -1,2 +1,3 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1e_core.v 2>&1 +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models + |