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| author | Matt Ettus <matt@ettus.com> | 2011-03-27 22:11:51 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-03-27 22:11:51 -0700 |
| commit | 81e5fd49a57a6875d89737da3f1c2e203c3fa0b7 (patch) | |
| tree | c91e133f2f0a0d5d694bb8d426a65578b9431278 /usrp2/top/u1e/core_compile | |
| parent | be2c1b95c1d6f4ad2ea663bb926a04463edb9358 (diff) | |
| parent | 8fa7187ca8ea16207e93f27b46406f20f75da8d8 (diff) | |
| download | uhd-81e5fd49a57a6875d89737da3f1c2e203c3fa0b7.tar.gz uhd-81e5fd49a57a6875d89737da3f1c2e203c3fa0b7.tar.bz2 uhd-81e5fd49a57a6875d89737da3f1c2e203c3fa0b7.zip | |
Merge branch 'master' into next
* master:
u2p: N200 Makefile
u1e: use icarus verilog for lint
clean up a bunch of warnings and incorrect bus widths
Diffstat (limited to 'usrp2/top/u1e/core_compile')
| -rwxr-xr-x | usrp2/top/u1e/core_compile | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/usrp2/top/u1e/core_compile b/usrp2/top/u1e/core_compile new file mode 100755 index 000000000..fb1b2a854 --- /dev/null +++ b/usrp2/top/u1e/core_compile @@ -0,0 +1,2 @@ +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1e_core.v 2>&1 + |