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| author | Josh Blum <josh@joshknows.com> | 2012-03-07 19:14:34 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-03-16 11:29:18 -0700 |
| commit | f031d37713d47c5478e65587f7c095bd62ed9870 (patch) | |
| tree | e939f58c3b0dfb1651c7d961439676bb2fb7789e /usrp2/top/USRP2/u2_core.v | |
| parent | 9f1c107bcae18b9bddfaf1101e20db06fc58e5d1 (diff) | |
| download | uhd-f031d37713d47c5478e65587f7c095bd62ed9870.tar.gz uhd-f031d37713d47c5478e65587f7c095bd62ed9870.tar.bz2 uhd-f031d37713d47c5478e65587f7c095bd62ed9870.zip | |
fifo ctrl: simplified perfs, added spi clock idle phase
Diffstat (limited to 'usrp2/top/USRP2/u2_core.v')
| -rw-r--r-- | usrp2/top/USRP2/u2_core.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v index 120b8c888..63509906c 100644 --- a/usrp2/top/USRP2/u2_core.v +++ b/usrp2/top/USRP2/u2_core.v @@ -456,7 +456,7 @@ module u2_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd9, 16'd0}; //major, minor + localparam compat_num = {16'd10, 16'd0}; //major, minor wire [31:0] irq_readback = {19'b0, spi_ready, clk_status, serdes_link_up, 10'b0}; @@ -523,7 +523,7 @@ module u2_core wire [31:0] srb_debug; wire srb_clear; - settings_readback_bus_fifo_ctrl #(.PROT_DEST(3), .NUM_PERFS(1)) srb + settings_readback_bus_fifo_ctrl #(.PROT_DEST(3)) srb ( .clock(dsp_clk), .reset(dsp_rst), .clear(srb_clear), .vita_time(vita_time), .perfs_ready(spi_ready), |