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| author | Josh Blum <josh@joshknows.com> | 2012-02-04 16:38:54 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-02-04 16:38:54 -0800 |
| commit | a9d307124faa679df8180b5624e9250555306d67 (patch) | |
| tree | 2bf8fc15ee0e078699ba555729aed882aeb8d266 /usrp2/top/USRP2/u2_core.v | |
| parent | 89ce89c9aca6daf7e293b80c70e14a3e2710e137 (diff) | |
| download | uhd-a9d307124faa679df8180b5624e9250555306d67.tar.gz uhd-a9d307124faa679df8180b5624e9250555306d67.tar.bz2 uhd-a9d307124faa679df8180b5624e9250555306d67.zip | |
dsp rework: pass vita clears into dsp modules, unified fifo clears
Diffstat (limited to 'usrp2/top/USRP2/u2_core.v')
| -rw-r--r-- | usrp2/top/USRP2/u2_core.v | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v index 4b2276e4a..7461ded68 100644 --- a/usrp2/top/USRP2/u2_core.v +++ b/usrp2/top/USRP2/u2_core.v @@ -566,13 +566,13 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // DSP RX 0 wire [31:0] sample_rx0; - wire strobe_rx0; + wire strobe_rx0, clear_rx0; always @(posedge dsp_clk) run_rx0_d1 <= run_rx0; ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0 - (.clk(dsp_clk),.rst(dsp_rst), + (.clk(dsp_clk), .rst(dsp_rst), .clr(clear_rx0), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q), @@ -584,20 +584,20 @@ module u2_core .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), .vita_time(vita_time), .overrun(overrun0), - .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), + .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), .clear_o(clear_rx0), .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o), .debug() ); // ///////////////////////////////////////////////////////////////////////// // DSP RX 1 wire [31:0] sample_rx1; - wire strobe_rx1; + wire strobe_rx1, clear_rx1; always @(posedge dsp_clk) run_rx1_d1 <= run_rx1; ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1 - (.clk(dsp_clk),.rst(dsp_rst), + (.clk(dsp_clk), .rst(dsp_rst), .clr(clear_rx1), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q), @@ -609,7 +609,7 @@ module u2_core .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), .vita_time(vita_time), .overrun(overrun1), - .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), + .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), .clear_o(clear_rx1), .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o), .debug() ); @@ -660,12 +660,11 @@ module u2_core .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), .sample(sample_tx), .strobe(strobe_tx), - .underrun(underrun), .run(run_tx), - .clear_vita(clear_tx), //output internal vita clear signal + .underrun(underrun), .run(run_tx), .clear_o(clear_tx), .debug(debug_vt)); duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain - (.clk(dsp_clk),.rst(dsp_rst), + (.clk(dsp_clk),.rst(dsp_rst), .clr(clear_tx), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q), |