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| author | Matt Ettus <matt@ettus.com> | 2011-06-16 11:31:27 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-06-16 11:31:27 -0700 |
| commit | 10d489c3aee1b09dec3171f70251c95e744c5afc (patch) | |
| tree | 361892a7b46c1d53df522983199264cd198b4d1b /usrp2/top/E1x0/u1e_core.v | |
| parent | 471c6cd2a040d705ded1c7db646bf3e9cf56049e (diff) | |
| download | uhd-10d489c3aee1b09dec3171f70251c95e744c5afc.tar.gz uhd-10d489c3aee1b09dec3171f70251c95e744c5afc.tar.bz2 uhd-10d489c3aee1b09dec3171f70251c95e744c5afc.zip | |
u1p/u1e: cleanup some warnings, connect the correct clocks
Diffstat (limited to 'usrp2/top/E1x0/u1e_core.v')
| -rw-r--r-- | usrp2/top/E1x0/u1e_core.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v index dff712a2f..b74f51d3c 100644 --- a/usrp2/top/E1x0/u1e_core.v +++ b/usrp2/top/E1x0/u1e_core.v @@ -76,8 +76,8 @@ module u1e_core wire [31:0] debug_vt; wire rx_overrun_dsp0, rx_overrun_dsp1, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc; - assign rx_overrun = rx_overrun_gpmc | rx_overrun_dsp0 | rx_overrun_dsp1; - assign tx_underrun = tx_underrun_gpmc | tx_underrun_dsp; + wire rx_overrun = rx_overrun_gpmc | rx_overrun_dsp0 | rx_overrun_dsp1; + wire tx_underrun = tx_underrun_gpmc | tx_underrun_dsp; setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), @@ -241,7 +241,7 @@ module u1e_core .debug(debug_vt)); tx_frontend #(.BASE(SR_TX_FRONT), .WIDTH_OUT(14)) tx_frontend - (.clk(dsp_clk), .rst(dsp_rst), + (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .tx_i(tx_i_int), .tx_q(tx_q_int), .run(1'b1), .dac_a(tx_i), .dac_b(tx_q)); |