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| author | Josh Blum <josh@joshknows.com> | 2011-07-08 12:14:53 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-07-08 12:14:53 -0700 |
| commit | 4ea6f7431e09d9f27ecaa1c1b187d2c2f613e8f4 (patch) | |
| tree | d2e66eb4e5f7cf7f8ab033f5482a6f2477aa88b6 /usrp2/top/E1x0/core_compile | |
| parent | dd41da159157afe417e7f3b77ba30e189eb510fe (diff) | |
| parent | fbc01138d5f943b06ce1bf3f746287b9d6c7789d (diff) | |
| download | uhd-4ea6f7431e09d9f27ecaa1c1b187d2c2f613e8f4.tar.gz uhd-4ea6f7431e09d9f27ecaa1c1b187d2c2f613e8f4.tar.bz2 uhd-4ea6f7431e09d9f27ecaa1c1b187d2c2f613e8f4.zip | |
Merge branch 'b100_shrink' into next
Diffstat (limited to 'usrp2/top/E1x0/core_compile')
| -rwxr-xr-x | usrp2/top/E1x0/core_compile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/top/E1x0/core_compile b/usrp2/top/E1x0/core_compile index dc0cd081e..02d7f006e 100755 --- a/usrp2/top/E1x0/core_compile +++ b/usrp2/top/E1x0/core_compile @@ -1,3 +1,3 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac -y $XILINX/verilog/src/unisims u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models |