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| author | Josh Blum <josh@joshknows.com> | 2012-07-02 13:24:13 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-07-16 20:37:02 -0700 |
| commit | 0ff64ba45e9d26359297242504d0c06e47a36a38 (patch) | |
| tree | 557ba78ea5385dd817969f10bf7b7480de74e77f /usrp2/top/E1x0/core_compile | |
| parent | 3e87c6ba2f4de72926cefa6aa833cb0f2191f053 (diff) | |
| download | uhd-0ff64ba45e9d26359297242504d0c06e47a36a38.tar.gz uhd-0ff64ba45e9d26359297242504d0c06e47a36a38.tar.bz2 uhd-0ff64ba45e9d26359297242504d0c06e47a36a38.zip | |
E100: squash E100/E110 top level work
Implements timed commands and FIFO control.
Uses control and data FIFOs for GPMC.
Uses the common core for E100/B100.
Diffstat (limited to 'usrp2/top/E1x0/core_compile')
| -rwxr-xr-x | usrp2/top/E1x0/core_compile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/top/E1x0/core_compile b/usrp2/top/E1x0/core_compile index 14e138fa3..dd88094ff 100755 --- a/usrp2/top/E1x0/core_compile +++ b/usrp2/top/E1x0/core_compile @@ -1,3 +1,3 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac -y $XILINX/verilog/src/unisims u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models +iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../B100 -y $XILINX/verilog/src/unisims E100.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models |