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| author | Josh Blum <josh@joshknows.com> | 2012-01-27 21:19:47 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-01-27 21:19:47 -0800 |
| commit | 0ff51a352d13f2ce6c59c82c90e853720936c88f (patch) | |
| tree | a055faeff34681138c92ded460358478749e035f /usrp2/top/E1x0/core_compile | |
| parent | 4f94819a4422a71251661fb501412565ffaea8be (diff) | |
| download | uhd-0ff51a352d13f2ce6c59c82c90e853720936c88f.tar.gz uhd-0ff51a352d13f2ce6c59c82c90e853720936c88f.tar.bz2 uhd-0ff51a352d13f2ce6c59c82c90e853720936c88f.zip | |
dsp rework: top level fixes B100/E100
Diffstat (limited to 'usrp2/top/E1x0/core_compile')
| -rwxr-xr-x | usrp2/top/E1x0/core_compile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/top/E1x0/core_compile b/usrp2/top/E1x0/core_compile index 02d7f006e..14e138fa3 100755 --- a/usrp2/top/E1x0/core_compile +++ b/usrp2/top/E1x0/core_compile @@ -1,3 +1,3 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac -y $XILINX/verilog/src/unisims u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models +iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac -y $XILINX/verilog/src/unisims u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models |