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| author | Josh Blum <josh@joshknows.com> | 2012-07-02 13:24:13 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-07-16 20:37:02 -0700 |
| commit | 0ff64ba45e9d26359297242504d0c06e47a36a38 (patch) | |
| tree | 557ba78ea5385dd817969f10bf7b7480de74e77f /usrp2/top/E1x0/Makefile.E110 | |
| parent | 3e87c6ba2f4de72926cefa6aa833cb0f2191f053 (diff) | |
| download | uhd-0ff64ba45e9d26359297242504d0c06e47a36a38.tar.gz uhd-0ff64ba45e9d26359297242504d0c06e47a36a38.tar.bz2 uhd-0ff64ba45e9d26359297242504d0c06e47a36a38.zip | |
E100: squash E100/E110 top level work
Implements timed commands and FIFO control.
Uses control and data FIFOs for GPMC.
Uses the common core for E100/B100.
Diffstat (limited to 'usrp2/top/E1x0/Makefile.E110')
| -rw-r--r-- | usrp2/top/E1x0/Makefile.E110 | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/usrp2/top/E1x0/Makefile.E110 b/usrp2/top/E1x0/Makefile.E110 index 89e51b523..8de0714c3 100644 --- a/usrp2/top/E1x0/Makefile.E110 +++ b/usrp2/top/E1x0/Makefile.E110 @@ -48,9 +48,9 @@ simulator "ISE Simulator (VHDL/Verilog)" \ # Sources ################################################## TOP_SRCS = \ -u1e_core.v \ -u1e.v \ -u1e.ucf \ +../B100/u1plus_core.v \ +E100.v \ +E100.ucf \ timing.ucf SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ |