From 0ff64ba45e9d26359297242504d0c06e47a36a38 Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Mon, 2 Jul 2012 13:24:13 -0700
Subject: E100: squash E100/E110 top level work

Implements timed commands and FIFO control.
Uses control and data FIFOs for GPMC.
Uses the common core for E100/B100.
---
 usrp2/top/E1x0/Makefile.E110 | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'usrp2/top/E1x0/Makefile.E110')

diff --git a/usrp2/top/E1x0/Makefile.E110 b/usrp2/top/E1x0/Makefile.E110
index 89e51b523..8de0714c3 100644
--- a/usrp2/top/E1x0/Makefile.E110
+++ b/usrp2/top/E1x0/Makefile.E110
@@ -48,9 +48,9 @@ simulator "ISE Simulator (VHDL/Verilog)" \
 # Sources
 ##################################################
 TOP_SRCS = \
-u1e_core.v \
-u1e.v \
-u1e.ucf \
+../B100/u1plus_core.v \
+E100.v \
+E100.ucf \
 timing.ucf
 
 SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
-- 
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