diff options
author | Matt Ettus <matt@ettus.com> | 2011-06-07 16:48:30 -0700 |
---|---|---|
committer | Matt Ettus <matt@ettus.com> | 2011-06-07 16:48:30 -0700 |
commit | e4be5c906e8c1f0901ff7206b4b965a0abc7d8d2 (patch) | |
tree | 7c7d2f9697d9d873e3d6917da6a87e31cabbbc93 /usrp2/top/B100/core_compile | |
parent | f0a9f021120eae604321edb9a97a7a5d8716da47 (diff) | |
download | uhd-e4be5c906e8c1f0901ff7206b4b965a0abc7d8d2.tar.gz uhd-e4be5c906e8c1f0901ff7206b4b965a0abc7d8d2.tar.bz2 uhd-e4be5c906e8c1f0901ff7206b4b965a0abc7d8d2.zip |
lots of renaming and moving around of toplevel directories to reflect product names
Diffstat (limited to 'usrp2/top/B100/core_compile')
-rwxr-xr-x | usrp2/top/B100/core_compile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/usrp2/top/B100/core_compile b/usrp2/top/B100/core_compile new file mode 100755 index 000000000..b2ccc8b49 --- /dev/null +++ b/usrp2/top/B100/core_compile @@ -0,0 +1 @@ +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models |