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authorMatt Ettus <matt@ettus.com>2011-06-07 16:48:30 -0700
committerMatt Ettus <matt@ettus.com>2011-06-07 16:48:30 -0700
commite4be5c906e8c1f0901ff7206b4b965a0abc7d8d2 (patch)
tree7c7d2f9697d9d873e3d6917da6a87e31cabbbc93 /usrp2/top/B100/core_compile
parentf0a9f021120eae604321edb9a97a7a5d8716da47 (diff)
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lots of renaming and moving around of toplevel directories to reflect product names
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+iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models