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| author | Josh Blum <josh@joshknows.com> | 2012-03-08 17:23:56 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-03-08 17:23:56 -0800 |
| commit | b4173387dd0adb27cc267b22dc57258d44fafa84 (patch) | |
| tree | 02aa6694ad692d1be912761b5b46c5ddaee94993 /usrp2/top/B100/Makefile.B100 | |
| parent | e230fefb32ad5ec2a861fdfef876da068a702b6a (diff) | |
| download | uhd-b4173387dd0adb27cc267b22dc57258d44fafa84.tar.gz uhd-b4173387dd0adb27cc267b22dc57258d44fafa84.tar.bz2 uhd-b4173387dd0adb27cc267b22dc57258d44fafa84.zip | |
fpga: fix custom defs in some top level makefiles
Diffstat (limited to 'usrp2/top/B100/Makefile.B100')
| -rw-r--r-- | usrp2/top/B100/Makefile.B100 | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/top/B100/Makefile.B100 b/usrp2/top/B100/Makefile.B100 index 3cdbb62c0..48dc7dfd3 100644 --- a/usrp2/top/B100/Makefile.B100 +++ b/usrp2/top/B100/Makefile.B100 @@ -71,7 +71,7 @@ SYNTHESIZE_PROPERTIES = \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ "Use Synchronous Set" Auto \ -"Verilog Macros" "$(CUSTOM_MOD_DEFS)" +"Verilog Macros" "$(CUSTOM_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" |